From da937983e5a5eacc9baba6b5f2a225613449ae18 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Tue, 31 Aug 2010 18:11:19 +0000 Subject: [PATCH] Start of project for the RDK board. Not yet complete. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1074 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp | 4 + Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.hws | 41 + Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws | 15 + .../RTOSDemo/DefaultSession.hsf | 101 + .../RTOSDemo/FreeRTOSConfig.h | 149 + .../RTOSDemo/HighFrequencyTimerTest.c | 162 + .../RTOSDemo/IntQueueTimer.c | 143 + .../RTOSDemo/ParTest.c | 268 + .../RTOSDemo/RTOSDemo.hwp | 516 ++ .../RTOSDemo/RTOSDemo.nav | Bin 0 -> 99980 bytes .../RTOSDemo/RTOSDemo.tps | 68 + .../RTOSDemo/Renesas-Files/dbsct.c | 66 + .../RTOSDemo/Renesas-Files/hwsetup.c | 107 + .../RTOSDemo/Renesas-Files/intprg.c | 53 + .../RTOSDemo/Renesas-Files/lowlvl.src | 120 + .../RTOSDemo/Renesas-Files/lowsrc.c | 329 + .../RTOSDemo/Renesas-Files/resetprg.c | 129 + .../RTOSDemo/Renesas-Files/sbrk.c | 28 + .../RTOSDemo/Renesas-Files/vecttbl.c | 64 + .../RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf | 407 + .../RTOSDemo/SessionRX600_E1_E20_SYSTEM.ini | 30 + .../RTOSDemo/SimSessionRX600.hsf | 72 + .../RTOSDemo/include/IntQueueTimer.h | 62 + .../RTOSDemo/include/iodefine.h | 7139 +++++++++++++++++ .../RTOSDemo/include/lowsrc.h | 13 + .../RTOSDemo/include/stacksct.h | 13 + .../RTOSDemo/include/typedefine.h | 41 + .../RTOSDemo/include/vect.h | 60 + .../RTOSDemo/include/yrdkrx62ndef.h | 89 + .../RTOSDemo/main-blinky.c | 217 + .../RTOSDemo/main-full.c | 641 ++ 31 files changed, 11147 insertions(+) create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.hws create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/DefaultSession.hsf create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/FreeRTOSConfig.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/HighFrequencyTimerTest.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/IntQueueTimer.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/ParTest.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.hwp create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.tps create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/dbsct.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/intprg.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/resetprg.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/sbrk.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.ini create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SimSessionRX600.hsf create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/IntQueueTimer.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/iodefine.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/lowsrc.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/stacksct.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/typedefine.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/vect.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/yrdkrx62ndef.h create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-blinky.c create mode 100644 Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-full.c diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp new file mode 100644 index 000000000..2a473f11a --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp @@ -0,0 +1,4 @@ +[Setting] +ToolChain=0 +[Section] +WindowSize=341,352 diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.hws b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.hws new file mode 100644 index 000000000..72a2cb2fd --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.hws @@ -0,0 +1,41 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo.hws" "RX" "Renesas RX Standard" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\RTOSDemo.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +"c:\devtools\renesas\hew\tools\renesas\rx\1_0_0\hew\stdlib.chm" "C/C++ Standard Library Help" 1 +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws new file mode 100644 index 000000000..381da059a --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws @@ -0,0 +1,15 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"RTOSDemo" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" +[WORKSPACE_FILE_STATES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" -4 -23 1442 660 1 0 +[LOADED_PROJECTS] +"RTOSDemo" +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/DefaultSession.hsf b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/DefaultSession.hsf new file mode 100644 index 000000000..49a2c5fc2 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/DefaultSession.hsf @@ -0,0 +1,101 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 289 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 206 560 340 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000025_HELPSYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N_Renesas\RTOSDemo\RTOSDemo.c" +[TARGET_NAME] +"" "" 1229201492 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/FreeRTOSConfig.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..9fa66759e --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Board specifics. */ +#include "yrdkrx62ndef.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ICLK_FREQUENCY ) /* Set in rskrx62ndef.h. */ +#define configPERIPHERAL_CLOCK_HZ ( PCLK_FREQUENCY ) /* Set in rskrx62ndef.h. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 + + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 201 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/HighFrequencyTimerTest.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/HighFrequencyTimerTest.c new file mode 100644 index 000000000..f971c4d05 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/HighFrequencyTimerTest.c @@ -0,0 +1,162 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * High frequency timer test as described in main.c. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / 8UL ) / timerINTERRUPT_FREQUENCY ) ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 15 ) + +/* Misc defines. */ +#define timerTIMER_3_COUNT_VALUE ( *( ( unsigned short * ) 0x8801a ) ) /*( CMT3.CMCNT )*/ + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +static void prvTimer2IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned short usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupHighFrequencyTimer( void ) +{ + /* Timer CMT2 is used to generate the interrupts, and CMT3 is used + to measure the jitter. */ + + /* Enable compare match timer 2 and 3. */ + MSTP( CMT2 ) = 0; + MSTP( CMT3 ) = 0; + + /* Interrupt on compare match. */ + CMT2.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT2.CMCR.BIT.CKS = 0; + CMT3.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT2_CMI2 ) = 1; + + /* ...and set its priority to the maximum possible, this is above the priority + set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */ + _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY; + + /* Start the timers. */ + CMT.CMSTR1.BIT.STR2 = 1; + CMT.CMSTR1.BIT.STR3 = 1; +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( prvTimer2IntHandler( vect = _VECT( _CMT2_CMI2 ), enable ) ) +static void prvTimer2IntHandler( void ) +{ +volatile unsigned short usCurrentCount; +static unsigned short usMaxCount = 0; +static unsigned long ulErrorCount = 0UL; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. First stop the clock. */ + CMT.CMSTR1.BIT.STR3 = 0; + nop(); + nop(); + usCurrentCount = timerTIMER_3_COUNT_VALUE; + + /* Is this the largest count we have measured yet? */ + if( usCurrentCount > usMaxCount ) + { + if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE ) + { + usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE; + } + else + { + /* This should not happen! */ + ulErrorCount++; + } + + usMaxCount = usCurrentCount; + } + + /* Clear the timer. */ + timerTIMER_3_COUNT_VALUE = 0; + + /* Then start the clock again. */ + CMT.CMSTR1.BIT.STR3 = 1; +} + + + + + + + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/IntQueueTimer.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/IntQueueTimer.c new file mode 100644 index 000000000..d25d68ef0 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/IntQueueTimer.c @@ -0,0 +1,143 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + IEN( TMR0, CMIA0 ) = 1; + IEN( TMR2, CMIA2 ) = 1; + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ); + } + portEXIT_CRITICAL(); + + /* Ensure the interrupts are clear as they are edge detected. */ + IR( TMR0, CMIA0 ) = 0; + IR( TMR2, CMIA2 ) = 0; +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) ) +void vT0_1InterruptHandler( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) ) +void vT2_3InterruptHandler( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/ParTest.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/ParTest.c new file mode 100644 index 000000000..6abffa404 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/ParTest.c @@ -0,0 +1,268 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define partestNUM_LEDS ( 12 ) + +long lParTestGetLEDState( unsigned long ulLED ); + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Port pin configuration is done by the low level set up prior to this + function being called. */ + + /* Start with all LEDs off. */ + LED0 = LED_OFF; + LED1 = LED_OFF; + LED2 = LED_OFF; + LED3 = LED_OFF; + LED4 = LED_OFF; + LED5 = LED_OFF; + LED6 = LED_OFF; + LED7 = LED_OFF; + LED8 = LED_OFF; + LED9 = LED_OFF; + LED10 = LED_OFF; + LED11 = LED_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned long ulLED, signed long xValue ) +{ + if( ulLED < partestNUM_LEDS ) + { + if( xValue != 0 ) + { + /* Turn the LED on. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED0 = LED_ON; + break; + case 1: LED1 = LED_ON; + break; + case 2: LED2 = LED_ON; + break; + case 3: LED3 = LED_ON; + break; + case 4: LED4 = LED_ON; + break; + case 5: LED5 = LED_ON; + break; + case 6: LED6 = LED_ON; + break; + case 7: LED7 = LED_ON; + break; + case 8: LED8 = LED_ON; + break; + case 9: LED9 = LED_ON; + break; + case 10:LED10 = LED_ON; + break; + case 11:LED11 = LED_ON; + break; + } + } + taskEXIT_CRITICAL(); + } + else + { + /* Turn the LED off. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED0 = LED_OFF; + break; + case 1: LED1 = LED_OFF; + break; + case 2: LED2 = LED_OFF; + break; + case 3: LED3 = LED_OFF; + break; + case 4: LED4 = LED_OFF; + break; + case 5: LED5 = LED_OFF; + break; + case 6: LED6 = LED_OFF; + break; + case 7: LED7 = LED_OFF; + break; + case 8: LED8 = LED_OFF; + break; + case 9: LED9 = LED_OFF; + break; + case 10:LED10 = LED_OFF; + break; + case 11:LED11 = LED_OFF; + break; + } + + } + taskEXIT_CRITICAL(); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned long ulLED ) +{ + if( ulLED < partestNUM_LEDS ) + { + taskENTER_CRITICAL(); + { + if( lParTestGetLEDState( ulLED ) != 0x00 ) + { + vParTestSetLED( ulLED, 0 ); + } + else + { + vParTestSetLED( ulLED, 1 ); + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +long lParTestGetLEDState( unsigned long ulLED ) +{ +long lReturn = pdFALSE; + + if( ulLED < partestNUM_LEDS ) + { + switch( ulLED ) + { + case 0 : if( LED0 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 1 : if( LED1 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 2 : if( LED2 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 3 : if( LED3 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 4 : if( LED4 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 5 : if( LED5 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 6 : if( LED6 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 7 : if( LED7 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 8 : if( LED8 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 9 : if( LED9 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 10 : if( LED10 != 0 ) + { + lReturn = pdTRUE; + } + break; + case 11 : if( LED11 != 0 ) + { + lReturn = pdTRUE; + } + break; + } + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.hwp b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.hwp new file mode 100644 index 000000000..789f0d5da --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.hwp @@ -0,0 +1,516 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.8" +[PROJECT_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\RTOSDemo.hwp" "RX" "Renesas RX Standard" "Application" "RX600" "Other" +[INFORMATION] +"No project information available" +[TOOL_CHAIN] +"Renesas RX Standard Toolchain" "1.0.0.0" +[CONFIGURATIONS] +"Blinky" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Blinky" +"Debug" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Debug" +"Debug_RX600_E1_E20_SYSTEM" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Debug_RX600_E1_E20_SYSTEM" +"Debug_with_optimisation" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Debug_with_optimisation" +"SimDebug_RX600" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\SimDebug_RX600" +[BUILD_PHASES] +"Renesas OptLinker" 1 +"Renesas RX Assembler" 1 +"Renesas RX C/C++ Compiler" 1 +"Renesas RX C/C++ Library Generator" 1 +"Renesas RX Configurator" 1 +[TOOL_ENVIRONMENT] +[EXTENSIONS] +"Absolute file" "ABS" +"Assembly include file" "INC" +"Assembly list file" "LST" +"Assembly source file" "S" +"Assembly source file" "SRC" +"Binary file" "BIN" +"C header file" "H" +"C source file" "C" +"C++ header file" "HPP" +"C++ source file" "CC" +"C++ source file" "CP" +"C++ source file" "CPP" +"CPU information file" "CPU" +"Calling information file" "CAL" +"Configuration file" "CFG" +"Debug information file" "DBG" +"Hex file" "HEX" +"Library file" "LIB" +"Library information file" "LBP" +"Linkage map file" "MAP" +"Linkage symbol file" "FSY" +"Object file" "OBJ" +"Optimize map file" "bls" +"Preprocessed C source file" "P" +"Preprocessed C++ source file" "PP" +"Relocatable file" "REL" +"Rts information file" "RTS" +"S-Record file" "MOT" +"Stack information file" "SNI" +"TD include object file" "RTI" +[FILE_GROUPS] +"Absolute file" "BIN" "NONE" "" +"Assembly include file" "TEXT" "EDITOR" "" +"Assembly list file" "TEXT" "EDITOR" "" +"Assembly source file" "TEXT" "EDITOR" "" +"Binary file" "BIN" "NONE" "" +"C header file" "TEXT" "EDITOR" "" +"C source file" "TEXT" "EDITOR" "" +"C++ header file" "TEXT" "EDITOR" "" +"C++ source file" "TEXT" "EDITOR" "" +"CPU information file" "BIN" "NONE" "" +"Calling information file" "BIN" "NONE" "" +"Configuration file" "TEXT" "EDITOR" "" +"Debug information file" "BIN" "NONE" "" +"Hex file" "TEXT" "EDITOR" "" +"Library file" "BIN" "NONE" "" +"Library information file" "TEXT" "EDITOR" "" +"Linkage map file" "TEXT" "EDITOR" "" +"Linkage symbol file" "TEXT" "EDITOR" "" +"Object file" "BIN" "NONE" "" +"Optimize map file" "BIN" "NONE" "" +"Preprocessed C source file" "TEXT" "EDITOR" "" +"Preprocessed C++ source file" "TEXT" "EDITOR" "" +"Relocatable file" "BIN" "NONE" "" +"Rts information file" "BIN" "NONE" "" +"S-Record file" "TEXT" "EDITOR" "" +"Stack information file" "BIN" "NONE" "" +"TD include object file" "BIN" "NONE" "" +[ASSOCIATED_APPLICATIONS] +[TOOLCHAIN_PHASE] +"Renesas OptLinker" +"Renesas RX Assembler" +"Renesas RX C/C++ Compiler" +"Renesas RX C/C++ Library Generator" +"Renesas RX Configurator" +[UTILITY_PHASE] +[CUSTOM_PHASES] +[CUSTOM_PHASE_INPUT_GROUP] +[CUSTOM_PHASE_OUTPUT_SYNTAX] +[BUILD_ORDER] +"Renesas RX C/C++ Library Generator" 1 +"Renesas RX C/C++ Compiler" 1 +"Renesas RX Assembler" 1 +"Renesas OptLinker" 1 +"Renesas RX Configurator" 0 +[BUILD_PHASE_DETAILS] +"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 +"Renesas RX Assembler" "Assembly source file|Linkage symbol file" 1 +"Renesas RX C/C++ Compiler" "C source file|C++ source file" 1 +"Renesas RX C/C++ Library Generator" "" 0 +"Renesas RX Configurator" "Configuration file" 0 +[BUILD_FILE_ORDER_Assembly source file] +"Renesas RX Assembler" 1 +[BUILD_FILE_ORDER_C source file] +"Renesas RX C/C++ Compiler" 1 +[BUILD_FILE_ORDER_C++ source file] +"Renesas RX C/C++ Compiler" 1 +[BUILD_FILE_ORDER_Linkage symbol file] +"Renesas RX Assembler" 1 +[SCRAP] +"Project Generator Setup File" "" +[MAPPINGS] +"Assembly source file" "Renesas RX Assembler" "Renesas RX C/C++ Compiler" +"Library file" "Renesas OptLinker" "Renesas RX C/C++ Library Generator" +"Object file" "Renesas OptLinker" "Renesas RX Assembler" +"Object file" "Renesas OptLinker" "Renesas RX C/C++ Compiler" +[PROJECT_FILES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "User" "C source file|Common demo tasks" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "User" "C source file|Renesas Files" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "User" "C source file|FreeRTOS" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "User" "C source file|FreeRTOS|Portable layer" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "User" "C source file|FreeRTOS|Portable layer" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "User" "C source file|FreeRTOS" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "User" "C source file|FreeRTOS" 2 +[FOLDER] +"C source file" "C source file" +"C source file|Common demo tasks" "" +"C source file|FreeRTOS" "" +"C source file|FreeRTOS|Portable layer" "" +"C source file|Renesas Files" "" +[GENERAL_DATA_PROJECT] +"MAKEGEN_GENERATE_MAKEFILE_FOR" "0" +"MAKEGEN_MAKEFILE_FORMAT" "0" +"MAKEGEN_MAKEFILE_RELATIVITY" "1" +"MAKEGEN_SCAN_DEPENDENCIES_WHILST_BUILDING_MAKEFILE" "1" +"MAKEGEN_USE_STATIC_SUBCOMMAND_FILES" "0" +"USE_CUSTOM_LINKAGE_ORDER" "0" +[ON_DEMAND_COMPONENTS_LOADED] +[SYNC_SESSION_NAMES] +[SESSIONS] +"DefaultSession" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\DefaultSession.hsf" 0 +"SessionRX600_E1_E20_SYSTEM" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\SessionRX600_E1_E20_SYSTEM.hsf" 0 +"SimSessionRX600" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\SimSessionRX600.hsf" 0 +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_SESSION_SimSessionRX600] +[OPTIONS_Blinky_Renesas OptLinker] +"Single Shot" "026c1f52b354bc10" 5 +[OPTIONS_Blinky_Renesas RX Assembler] +"Assembly source file" "088b30f0a993bc10" 4 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 4 +"Linkage symbol file" "088b30f0a993bc10" 4 +[OPTIONS_Blinky_Renesas RX C/C++ Compiler] +"C source file" "067b2354f2d3bc10" 2 +"C++ source file" "067b2354f2d3bc10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "090dfce07df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "0984667d4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "02b798669af3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "0fd4f0520214bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "00526507a114bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "0a762c328df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03ceac85ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "067b2354f2d3bc10" 2 +[OPTIONS_Blinky_Renesas RX C/C++ Library Generator] +"Single Shot" "0ca340787f14bc10" 1 +[OPTIONS_Blinky_Renesas RX Configurator] +"Single Shot" "02c169eb6f14bc10" 6 +[OPTIONS_Blinky] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 +"[V|VERSION|1] [B|SJIS|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 4 +"[V|VERSION|1] [S|LANG|CPP] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|0] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 3 +"[V|VERSION|1] [S|LANG|C] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|0] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 2 +"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 1 +"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(01000)|PResetPRG(0FFF80000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(0FFF81000)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1] +" 5 +[EXCLUDED_FILES_Blinky] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" +[LINKAGE_ORDER_Blinky] +[GENERAL_DATA_CONFIGURATION_Blinky] +[OPTIONS_Debug_Renesas OptLinker] +"Single Shot" "021ac70d6f14bc10" 5 +[OPTIONS_Debug_Renesas RX Assembler] +"Assembly source file" "088b30f0a993bc10" 4 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 4 +"Linkage symbol file" "088b30f0a993bc10" 4 +[OPTIONS_Debug_Renesas RX C/C++ Compiler] +"C source file" "067b2354f2d3bc10" 2 +"C++ source file" "067b2354f2d3bc10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "090dfce07df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "0984667d4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "02b798669af3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "0fd4f0520214bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "00526507a114bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "0a762c328df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03ceac85ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "067b2354f2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "067b2354f2d3bc10" 2 +[OPTIONS_Debug_Renesas RX C/C++ Library Generator] +"Single Shot" "09bd5759e094bc10" 1 +[OPTIONS_Debug_Renesas RX Configurator] +"Single Shot" "02c169eb6f14bc10" 6 +[OPTIONS_Debug] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 +"[V|VERSION|1] [B|SJIS|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 4 +"[V|VERSION|1] [S|LANG|CPP] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|0] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 3 +"[V|VERSION|1] [S|LANG|C] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|0] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 2 +"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|MATH|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 1 +"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(01000)|PResetPRG(0FFF80000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(0FFF81000)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1] +" 5 +[EXCLUDED_FILES_Debug] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" +[LINKAGE_ORDER_Debug] +[GENERAL_DATA_CONFIGURATION_Debug] +[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas OptLinker] +"Single Shot" "0fd3fdfb6f14bc10" 4 +[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX Assembler] +"Assembly source file" "0cb120ca4793bc10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 3 +"Linkage symbol file" "0cb120ca4793bc10" 3 +[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX C/C++ Compiler] +"C source file" "0cb120ca4793bc10" 2 +"C++ source file" "0cb120ca4793bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "090dfce07df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "0984667d4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "02b798669af3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "0fd4f0520214bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "00526507a114bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "0a762c328df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "08d08b78d2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03ceac85ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "04345d232893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0b083d452893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "0b8497895893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "04345d232893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "04345d232893bc10" 2 +[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX C/C++ Library Generator] +"Single Shot" "0cb120ca4793bc10" 1 +[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX Configurator] +"Single Shot" "02c169eb6f14bc10" 5 +[OPTIONS_Debug_RX600_E1_E20_SYSTEM] +"" 0 +"[S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [V|VERSION|1] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24] [S|LANG|C] [B|RUNTIME|1] [B|CTYPE|0] [B|MATH|0] [B|MATHF|0] [B|STDARG|0] [B|STDIO|0] [B|STDLIB|0] [B|STRING|0] [B|IOS|0] [B|NEW|1] [B|COMPLEX|0] [B|CPPSTRING|0] [S|MODE|BUILD/CHANGED]" 1 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 5 +"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 3 +"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24]" 2 +"[V|VERSION|6] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).abs^"] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [B|OPTIMIZE|0] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|FORM|STYPE] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(1000)|PResetPRG(FFFF8000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(FFFF8100)|FIXEDVECT(FFFFFFD0)]" 4 +[EXCLUDED_FILES_Debug_RX600_E1_E20_SYSTEM] +[LINKAGE_ORDER_Debug_RX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM] +[OPTIONS_Debug_with_optimisation_Renesas OptLinker] +"Single Shot" "0365455c6f14bc10" 5 +[OPTIONS_Debug_with_optimisation_Renesas RX Assembler] +"Assembly source file" "088b30f0a993bc10" 4 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 4 +"Linkage symbol file" "088b30f0a993bc10" 4 +[OPTIONS_Debug_with_optimisation_Renesas RX C/C++ Compiler] +"C source file" "03e2e2a06f14bc10" 2 +"C++ source file" "03e2e2a06f14bc10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "03e2e2a06f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "03e2e2a06f14bc10" 2 +[OPTIONS_Debug_with_optimisation_Renesas RX C/C++ Library Generator] +"Single Shot" "00e576febe14bc10" 1 +[OPTIONS_Debug_with_optimisation_Renesas RX Configurator] +"Single Shot" "02c169eb6f14bc10" 6 +[OPTIONS_Debug_with_optimisation] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 +"[V|VERSION|1] [B|SJIS|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 4 +"[V|VERSION|1] [S|LANG|CPP] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|DEFINE|INCLUDE_HIGH_FREQUENCY_TIMER_TEST=1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|MAX] [B|SIZE|1] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 3 +"[V|VERSION|1] [S|LANG|C] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"] [S|DEFINE|INCLUDE_HIGH_FREQUENCY_TIMER_TEST=1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|MAX] [B|SIZE|1] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +" 2 +"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|MATH|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1] +" 1 +"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|SPACE|^"FF^"] [S|OPTIMIZEITEMS|SPEED] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(01000)|PResetPRG(0FFFF8000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(0FFFF8100)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1] +" 5 +[EXCLUDED_FILES_Debug_with_optimisation] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" +[LINKAGE_ORDER_Debug_with_optimisation] +[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation] +[OPTIONS_SimDebug_RX600_Renesas OptLinker] +"Single Shot" "0fd3fdfb6f14bc10" 4 +[OPTIONS_SimDebug_RX600_Renesas RX Assembler] +"Assembly source file" "0cb120ca4793bc10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 3 +"Linkage symbol file" "0cb120ca4793bc10" 3 +[OPTIONS_SimDebug_RX600_Renesas RX C/C++ Compiler] +"C source file" "0cb120ca4793bc10" 2 +"C++ source file" "0cb120ca4793bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "090dfce07df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "0984667d4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "02b798669af3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "0fd4f0520214bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "05d6fdab4a04bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "00526507a114bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "0a762c328df3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "08d08b78d2d3bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "0cd92d23ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03ceac85ed14bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "04345d232893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0b083d452893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "0b8497895893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "04345d232893bc10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "04345d232893bc10" 2 +[OPTIONS_SimDebug_RX600_Renesas RX C/C++ Library Generator] +"Single Shot" "0cb120ca4793bc10" 1 +[OPTIONS_SimDebug_RX600_Renesas RX Configurator] +"Single Shot" "02c169eb6f14bc10" 5 +[OPTIONS_SimDebug_RX600] +"" 0 +"[S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [V|VERSION|1] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24] [S|LANG|C] [B|RUNTIME|1] [B|CTYPE|0] [B|MATH|0] [B|MATHF|0] [B|STDARG|0] [B|STDIO|0] [B|STDLIB|0] [B|STRING|0] [B|IOS|0] [B|NEW|1] [B|COMPLEX|0] [B|CPPSTRING|0] [S|MODE|BUILD/CHANGED]" 1 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 5 +"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 3 +"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24]" 2 +"[V|VERSION|6] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).abs^"] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [B|OPTIMIZE|0] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|FORM|STYPE] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(1000)|PResetPRG(FFFF8000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(FFFF8100)|FIXEDVECT(FFFFFFD0)]" 4 +[EXCLUDED_FILES_SimDebug_RX600] +[LINKAGE_ORDER_SimDebug_RX600] +[GENERAL_DATA_CONFIGURATION_SimDebug_RX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM] +[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600] +[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600] +"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600] +"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600] +"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600] +"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM] +[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM] +"MEMORY_MAPPING_OPTIONS" "Unknown Options" +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600] +[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600] +"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[EXT_DEBUGGER_INFO] +0 "" "" "" "" +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav new file mode 100644 index 0000000000000000000000000000000000000000..5d6c9a6ce4c2d0878e373a76e674bfbcbb7bdae5 GIT binary patch literal 99980 zcmcg#37lI;d3O@qxqQd5ofC%yB9Q~lJiYhyln}D3)!It-ilp_Cm?-OA*S|7PAi>AlfNPrFj{`$bMX|M}*d z??3a+H|INt-RM1U{knDM=k^X&kIgPr>+A5(+4O^d&XRw~-*YRKp>i&tIDOf=b?4x( zE=6hxu(47phFQ>N5&E29G= zgOkJD*M3{n-U2XO7_m%%4VBTs!dS|byb;NV%lWJ+9rAO<{6P8fCIIB;$A{DHl8Z&# zl#Jr@hjJs#ln&`5gTqdnpnnE)GQ^M0mDgL4LkQor6Nkv(Wi+%lLOxxF%6 z%-=DYAIlwntgpc}(KdRXz>Q9hTx~*JboAu%z{tq>!GXb%JequQUt#PHAN&yh47r%i z01u6il`DfIS$A*XIVtQh#AeJtsF>ex)gKJrYx|GNo>% z)C#rqQhtO63cs>iGbb_Z)h02N%3sqi)q1TdbyIGd9IvZTsSs+ zJhwj&T877q6-m(efqZcoUF)EqZ)dc7?(p+XOrnWpJAdhFf>$5y}%?mjAJj1hvN^# z!&xsf;T|RRyFFhV%a5RUm-EHqx2o%C727H^jt=Bx&7Ns0Ap&I2iV5V;jtR7W zEhaGioR~oSxh9}*uF-)*m8PcbJGnx>bhjzvPGzn`%CtZ~$%MY9fi4{`Z~!9?4I|NUY)jPn_@$|= z`wFEphCedmVN+?opOaZi`LUsJQOb8|MfrZNT!4!c&TIdjqoy*p%NhwR%?`$kb0+A; zK6JbcQ(?9-A+%Q`vepE4N%&+bUtvyVuuz8oL=>aOWex8ei0}g=a5G~AWwP$TMBzbS zqs#GUXn6JwB(h9Qj8NcF7>A!GLdpaC?&?qz%GcZ8Cdd+hqPg+hprSrsQ+59`q7Z;s&u;^b})qo)rHpQ}Sb~wOURD zi(}(uct3Q15p!a`St!B>jOItji-+^D5-~`@XUJyTk$r63cY6q+C&yGj(V*J^l?_?U zM)E`ZOhUH=Nb(hj2TZul0d9D5WMt3;Ylsu^uyQ<_f*bQ?jK#UXHkoQ;{t%h+<)-v= zWqRtR9RTcQCcuW_k%7|wZ<>-X6v+se;F{H3kA{E{Baks#7<-&=49#0@!Zc+<@KtIE zd0$k>rs0W!@_zJREb9f+X-(FJ0je;j##Rl~5QWK=nu}gJs;PlS%hIHi&|YOw@v)X+6P1A;DEgENwKUW= zLdni27gJQ2sUdfrs7@`R0To7}u3R=~cA8IF7h&Z*ipB^*?t%XOSroCQ5L&^y#>Z(> z`||`2D_B>V5a$$fldmv!j`g%8{!~-yCZu9An8Lq>)MGD|s%i`CK8g{FU28&ZAz4@^ zsSF~5C>DQsi9y0^4Q=8(zMpIil!^)7hISy%Z9!T3)*!7PGV|7(J6BlD6&9uU8&!o8+iM3Agdi;3igdQ7BM zST-R=a}h&JC67gnpPA}&5!FWyA^sn!!iq_#4rYZ@Ca}<8I5$}tE)1i={>Y?(Xo&(> z96DV1u?Z%63A!RSRqjabFcsR2Vi%cEqDWsBOI;od#;%A3<5$LlS&xbZOYe;Zv#&D2 zn(e`N#z9#Z$3dlc#X;G-c&{O;nd?zIN|eP7bXqEQcsG5 zglSmna6IH7OWhd{nPaKD;vt7v>PSZ|89|L3^kZ z&Jp%=3Ndi7pOcS;8+3+a;d0KtShyi)e=J!G7*Y zEZm?w+6k8t`ejP7a0fEQ7&z#cnTUlO%-qol=ZSXZ9g2ZNxn4OIZqS>Ih0A#dV&R6o zgC?8^6DP*=mGOLmO~pa+qj6BybR1NA#)J~_M6poFr7DG7K3_<^Bo?xGsE~STEMyrn zUmgz$nJ?>zWKvJ|idabK$zB-?2|d}X;~^pQRVL(Cn(Y-!6NOZzG=Zw06AM@wG zG*KMdW&(*>Nr~}+AzC9!w1?$DE_QfR_jQI*KRMkQMxEp-F<_8(rW1^jZtPb&!>DiE z-x)?7<5y$AAnmE0V4QU0PwNbWZv5$;VbF~~GX@OOp3wVrw_3X|t=w>}9 z1`N`EtrN^9-R$RfhCw&`d7WX<&3-`)7^FSF6U-sqoELV6K{w}t&M@fayf_97(q3eO ziCJBFw1~53qgWNF#=;Gzj+t=6JqUT@2MVd0Kr;z%k38y47zihUyla@e=ve{WCq$-M2_{go)YSo2hGS~j8g_*hPC;Y4$msdu!mZncs zXIAE_HE_CIJ!2~J(ojB-u`*vBt}V{voXY!6Wo^e2a7FH4(n;82WAArQbeni99TeRM z2pz?0+T(sFWQX>XFPL3eK8~&AQkkivkq?_OyyEND24mgR8IzteVJ;$l@`omH5)K>u z17oFw`Qp*GU>qbLL`BDkWnI;wOHIQqB)M?_W~QCcdxr}}91tfXiqp0yeemn?XUKfJ zA@ttRzPZqXo#-+HpEYG5gNPDPN3{>G_U1KpE+%mEuDsCZ$tKx5e0Y;+bv8j0eFb5$ zC0-fGLf1dky(}%mB_ab| zFvfkgP?ndN$`FcUTt|l7;T$fMQPizWsTCkJl6@v5{-q}IyGWzpAZlQlSDNsb5ni0> z6!$?xg{V6=npUFP&69zkoR^!*5f#B<%4p3WG-cREij9>jxX2@K@Tjh)X(N!$A)5*} zwJS7235lE-$L%T=`aWP%LRd#;5I1##%fh(EuN;k5${y0ZnBON4$+F7CKoM855cEIS zR7^MrZ{&EMDaXZB25zg!GE_ZY)E2%{kf)P_YQM|`zi1xE`WxPt8bwguFC$Z^Z*3uP z!~d!MC)F+HW=)851!8Dmzy!EJ z0_Z&G6HFLc4DL(ZVnRqM;>yI533H(+NuJca*#wdV(809ZIzrg(CWur=9OIhoj9~{% zm_Qpo(h*{fc7&wIIzsI6ju7XLju5xl5t1o&gm~qSkby!+$lyeK$i&3H)V_`ow!b|D zUN}|j2w`;-M79{QQUB!57nvfr^hq5dtkMy}r#eEc z>5dS)+7aR$H$fx|rBPJr?#>u?PiG82+8JZbbjH}nI%Av@CX8f?Hn155ZM7vb`lkHNS-*1=de!5+1=HYg!-e=mS4t%&>>fonLsppO3Qa4^J z8dB>g+9dnj@rrnh=~e`7Gy~QE5K+X-I3tJEGMa|iNQi^M5|fsWBE)k<18s^pSfnCU z1gVKQAK`lVb{ox|LJ{xQrKuV=mX>J+npP&%ip?gVLcmK2SYO6dUIUXOcwK|uyP*d` z@}-hmhtY&@nF!tKdW>HaZ8hdRfy14yN1G5EmuBd;`K^BX0sI-#?p#VADdm;5H2?%m z43tW0L9bOhtewBvRKPhnZ1<39UEzZr|OB+d(v@<0Z&Zqp+ zJ{tw^5MW%dD;MyRfml9J+c6q;v%q3HDnuSNiIn9}6vu}qbE^D%OyI3TraxK4tv$7D zuN5wVjTzJ3CW*U*#KsJiJeW7hK|6q~8u(~q=Gw!hpq z+4)M_WcLr-CTG6dHre}H+vI^iG9{y(7Ujm&{+oQFXyza4Ny4&&e{2$g)>d1l)y_)! z@I+p%PS84QND3M-V0g_A2kr{{#ztwa(JxWM?rwplCs|xbB;VRv#oX6TDxOF3a{C90 zYWl8~_-KI`$qy78yItZHn8uq0_nWj$h`i!z@nli1cooGHPvQ5M63GXA^|c-G%Y+0x zYKGT9Mk-^teN4}FVB@fy8?2d%6|@ZfiK)(eNaj$XBz7HxUD;A1xo8r2fygmFiC5m# zYP4o2QE2`fra}dAc+-y_ifb-&!Bpl>DickCmcjh`Cz9&OgjPB{7SMm8LFo6+vm$J!n>u z?wR}*ld**Q;yFIGiK?kDsFY*YzT)`7^8R~F!URJSN$##_!U=aL)|-d%fF!+JlX#{H zE4pe3i$%=w@_6DIrW`_FvEMKDnnp`gCL~7L+VW(H{7Li5qmrzxPhLoP@!Ulssm_IH z<`Vr-fEw;m9pBKvqKiwg+=ij&kzQ-!c|EO${HCePQ7U_bDRpbml;rNbat&G~FKPlR zdX%5lz!!jv+Ysb7t?FvA;_ju|sezdpI{Z{#ELNvx&fKw5U8yF1>eHgF0dLz~j6c#sfO>BoA06t~H@I1HB*5F%mWgDK04*!{T_3g!e}-hAr=I1w*+;BL zatN_$>C^<;+UV3A3Rg`{v;NLz)WF>A@rCM4;z0-^<+Oox^U~?jmF4Q`{fl!mI8J6# zZZkI3@_D?s6?*66L(w|yxOb^qJsCQxq{fOrh+;1euq0D$S*USTgKrn`=3_@AzOov0 zr+`M@0a1aBhTbgD>Rk^tB55#Le)G1H8k02WHX%_yXDY^t+f15nm-6VeQwhhGU{ z;5Vb@I#)vX-{Q-9FbdduFLj{COR{(QK&_$e5^ zJ$1PaulDUV)wcUN>5)A=WS)(n`OqR-K+- z5!Rs5CA7Dyrluc>(t4%Hgdm|@!~|K(H|-lq%eO`3lTTFQ?3@~GG~8x^Q&ZnLlekL- zjOOT?3RP2{Z6Z%oKTszeH6<<*$nrrf*U)o@qSMTq#O{i`RTpte??Aqg+uR_Q=s##0 z14T0XkSY0sV(E7A1bb!wc3&fH?PY_wUG}>s5h9uWo+v;ab~9&dul5(x%jDHCdg*dltDsZok#_U^XH{5@@x zt@pM~w%^w_*?GSyd5g5Vn3^_))TdF?P@CCU$7O)o>8JV@&?4fE@{PHKpRTQRZ$Nrs z?6Ia~%8qyCt~I4^DNPn~c-mi%Yr(~ow*wzi^PJK_miC2c=W5SIA{{zZVNh#8Ay>?r zBtSe@hdNv37H3j3rrao><2G~gCKCYSEyt9I+~UZpTFh@%zD441Hc2=iPxGO-BWkit zkd1f?8pj8pXKF4RMO+cYiKieZWdA+Om~*vS=6bJRqLyPf+{G2o})j9ZqyE?C%VH!c^eJ;Vf98 z976>3NfTVys!>8|5?9X0hVnxXnKC>^$QNHqsF-V{LQkzm7gBbA_2K!ZGOk>nov+q{ zp$G9h9w);$F7k3)WZ2Jl0oqBZsa!1bk@IbyqN(^+gYOaW#&T0|I!=v_h8$z#MS2bS zuslbK58fn_>L}Xlp;|~KSw{$2JwsxGdUXDLQ z1zm2)C|+9rg(=rwkxOhr(+lCzC%+R(idtGOnq1pHr~jyTBAGA=*wHLNOm-7A9Jeg& zQVko(r`wb*^IRbEh{vwKXR5xGE8<@{R}ZFD3A*XmQtnkkZmT>>r^`)QWtAnN(&h>E z4!6dqRIM4S#0TqrTApV4m_OotZDPWt%QjIBDW8_L5*ZWnq9&wjhG`SHS#2Mz^uF1Y zM>gG1J8!HI?>FVTT30K`rHULeWp1v$=pomekh`0Tk>{PoYxRkgDZ?dN2K6lZt)?up z7fJ*8XR75(>Z%??rktBZVPgDFB){FhnU@D{_g}WJG@AKdljQ9}vWTPnrdl>Z_e7ye z?L(#f1Z{@;BB6*J~Ls&NTfg>iUq)N!fnd)L*Y%kO5OX9RC zOOrZkxfWCIa^i$3Lz6l<=c$M z1jNQzBKeP|cGE;`kO9-5MDpKEIkqm>Pl~|{qG{{=BR)`@h!Ie_C<*+S3AhbF@lgq7 z?x*=kEkxg;kc}C-3e&XW_W;ddAQ4Qab`<#e$+y;7^so~q`s3zS=2Sy-Mlp`ilV0GnWAEAvOI zwee&0zjd|4qN#9MfY)D&P&?gPrtLD5dM*Klsc=w(ZV=z4e3r>#n<<&@V$gF>sV`kB zZJ<3Iu3+-z@JCFrtwLJk>G0Q@fLjDGcsu;PF>v&F`1@kvMpGY%furZc-yaJ%n)+Y| zoO(d~!Hzijg7|NA#EBlXsJZwE%Dcxl#nercuf5DCYNWA-iv?pJ zHo;`6!F%Gr9}mYq9S_GJj)${86AzdEY&@L(ITJ2qJ^qncFzchSVCj#=g4rLB1#>-ub*%9c!I{w#jfGFDfc0Ayq^__UYob{LSfJ4?_bp-lPkN;g9 zAS#poZam;%`g`$!x%A(}0}iGCwjP3${|WMcjRS-ooqvi4 z9CW@P514cQIUaDx`ImUWyz_7IfWywecLe$`k^fgb-~smsae%O+`ycUugYJKJ1p2R$ z|0EvpK<3ABfY34X!+5~K%#S(({TIo976*u;z5k8}9Q6Jt9x&(qG#+rs`(G1K#+m9_ z@(reOD+J>kW5KL*W5LqrnP4)qXnva9iU-9zv#E4EDBhY)IWeJ-YIlaJ=gHl8Q0U4s z@u1L^Wn)4i)iXi2iD_ih6Xm~UY8_!D-Y9=(JS3jRen&hcUMc_W&Pe~6^52Pv#5?8h ziHF29+3$*n#7pJxHX%1jd&;NEzt9Mwg^;Ha}aIt~uIOu0RE)EXzk{xmK`SR;x;Gmy)cemd}}QH{pVk{rAjw!~+gm7ny)T z$?`?>ohF=&bZGxaJ!$?XlS^-g$~Vp5Y=X-A2&wofq~2lz1~PFNQoN|n-WmrgpEZA* z2^tjdzia+>6Hrc+G~wMuSnV8qky zd6TdU6%ZyHGJ$pq5cV94D+^^DairJK>*~s?R`&S9 zq4vH#!1?7T-eZC`6rhq}EqquZ@op3P;y|!O<38%ba^hVk_$CRLo%AkKt*&TBiE{ur zT@dte^-hGwvR_FlTwMG-Vk*I}WSEm_6WSN-qp70zn4o*4>ia;k&>%R{@FY`?3uO+$ zpL4c>Kc8ns-YZNvUl^&Fc)CA$XpLcqERjI|2NM$C$FM;ohlcg5F3A;5K^>^mpnlaG zP$m40CgDwrlyTRXTF$q8GilNB z8oR z+U>2&#la#vffO0o_Af4;JmBZje9tDCO9UUmacAu$+pZ=QhSz0`2g|s?KI!YM;dl6l zoW#iCM>Zx6F7>f3#$$DgO4Irhl}Gzr%OO)SvI-df!k=kTm;JONwyPq_v(qOWeQ z7LHdd^dQ2-Xk~e^GKnV_Mi*zQQV6vHD)gLaq4XV)z0-4x^=g9t>)7mEbzw32GgFz{ zL}5cK^YdqrD9`)s(NavQ(`dn5{3?@ZN-<@iC^1%>_;_%v6uf;?0LfzJw{?9#P=_soKnaQ?)AM z)RiTvBDE;0+J>lwZSr?BTt5=t=-%ANcr|Q)t9RMd~v^KU?s826nORc}>7q>lHoHXp% z;=(Ap&D7DkYGDCiz^bh*`G%z%s4bbimXuh;XPpw$C#GtT+q*C|UzM88qczI^IyQGa z`5j+?rlRFHYkDI_98^}1rzGel5q$HBI`Z{<@npwT4YHwCJ^5c7r8e6kG}H<+?SuuR zG7%Gz_#R(9I=LH?c#BcuDKT9}!xgj892^6_9aW3S{dZsP$5$(NqP94*GOfw|+A8Gc z7U!2>KWGecNAU!C3(G#km;33czBifeAmu`=lF1@Qphpd;@jS8?p*$k=4ZRR*MTFAY zz?wBpM}%(nd#6_YbQ_zB7=Q?>N2EREtN6vJF>SLnc$(q4sd_8IPx#_q6%}{0S=8?qi@^#1U0lWsa7uq8h5{p{+-+_gh5`7o3F@DvtM7F$l zr7r$@sJgU#0+z*J$y*Bagc+)}a#|$IWs>Aq&Xq-L9{YN~Xk|9>fEBg-R_37_fK&l( z_=2(NV!w=ypnf1l-6|+oYx7vmqxeno_)e2Tqft?dOJ|0rmZxZ*BAR^Sw781(xV_VG z`OABkq*QVw~nx#^J@9@Lz=m@%WdtmLCDh zSYc^eET~CSUBCA<;izc(^ZLEfaH+hwJT>PRklbR@Y%ro(>t2$dUs^t6YGu1koiN)< zHr7i0Z-3I_i%I6Q!9TTw&qdpTida&`7}Df%4tnKspFpI;|mzpx4vy4FQU7A-9y^_HGOKD4L& zM)F0bPC6W~02)r($$yJU{(OWKB9aI_IJ$>MQQMPxw1kb!uPyV~f zjssCOXxLQ*sxh-|e|?^*zup>0bi3jBiKYQF+Q&u~?^7zb?X)lVRnhFrtvxC`pDw(e66-vYlI!) zF1CVUVxgL(`6M}3Ev8ZPO66FEXn*P3jEww^FTyTD!U40^H=aqIM~X4@xJ0;j5ro=0pq?gjX^8*O(got4V_==o-i? zo1$T=d9{h9Z~J0Dj6XvxMf-cOo-4%WurpA@%mt3kB$-S_jY*TNCPS(*g(cH`sEt$= zwQ5pBD|#3*Fd)&=1S`xh%~j{|;p?V&_1k_s*FxXNYqpd^Om+OQNsvJs-bx$GcZ_kh z;U;aqXwoL?Vf}rkg=I`fXa|W5)oO~MW}cddy*gs2673%k&(`FiCj*$T`uzV&v}HXe zl9{&BYaGicaxkyS>}UM!=XY`+lM9$#`LEr!3<^d~gZ5PsMGnta=Vn4mtoJRd*FiSk zrU!Bpb!<9UmiL}MIEB@|8QOwQzTU3`)g{!qo=k40F~dXrGJ(Hn#DcIV=7?dCm`5xw zjUN+tPNrazPP2nf|e6XG=sp~v0BrTc3)O4eBQKA|g#yw@bsH@B=5 ziG&Z0E%i>5)TY`NG3Uq83t=Xu8U0Cz7bzvFc3QRCULkAiZ{anWoc=zbN!zmXYvgA` zC&99Nqv(5(_Oj_ zdbx>M*M?iU`5Bxi6=)i&lRxy8)q(`S_k|+^d8|~Hb&+3|mNPWDJcWKWkE53&r|7?k z_NWgBDl|n4zv?Tab?AMv(xR7z4y|GZmmZ!`?p*v&K#E$L6n`sx%}Zb$vX3_Y`L0zU z-D_+9X5~u!Rn(>U!jAlmP`v|8`gCatd zdsnIp(`SSyleE%74>FM!`T7l_w0LZpHqe9dqEITzoIm$-YK`w!zY-Lts~MrNwDjf1 zK{jy7s$F~>C4}7R6PqOar}4TH{A^!kZHjSAlVGapaS9&fHfx+QL>=1rbX4JMB67vP ze3QzQocy}4)$5|UZ)(cjyb%~jrMrBgv{e?eq1z<1n>ya@3)J>Pn{C&$zZjS7nlD$| z8ua5Pgmg7I-l}z~NI3AhXbqc<9-i(u1ryKki`Ay~{#YQ2ZJaw0QAp>OTlb}YG^&%| zo62}xH0Vj8$)D0k3n5faJTuxl=kxqBwVX#J(^P4-DcCsa9tvSa09RhbDWutBXJReA zC(oExg_XW2H8)qCT9{nIHmq3J@_BoX?*p~y-XAYXUvbc0OiAh37`+>|_cZ-iy}T%r zl5aCb+lL#K7D#atKO{-*B48R^tDc%&T)|G`$tt--xgXbD;ynD`bWN=2BoCR2ygpPU z&S`{fE2jrSZzLsmnWXpwJ=IYj6Ww`^gozpI?aWho?Q;- z`mrgO-KZ!gLCrgcn1Iu#c=oCxxM_DV`8P3i53Eeam%5Lbnu#BmQ7&ADXhp|2e!zhYw1A61&=7UBwhw@K)DlWqJ>RfHYQ zT4JU`MK-PUL{~R3`A`*2{Jrl($ydhkWaQIvPN+ zmeLxbw62&65wx)S23-^d!Um1@`R3B%-WD49+es!SzvEX<3w2wx3Lztic=g)7%UA1j zQA4?U?OFuEy1-j~fm%S^Lb-5UtjnTr0>DkI)574#MwFAgIB2i6P%u2}x2cZQ73y-) zPkOaz&-pXo-rCaMRciZW0?R50Wty+@$xf$Eex8Y%_u5DeNP?UzOrNOEtjytJAvu-g zyZy2?H}VocREo$Ed~4SPTdqo6FGB2K$nX!WwTUrgQsbD->DyLt_6cX6;A4_>Er__% z)<|9(OHtb0GiWKJ60$}^SGkNQD%*|1IUMB+4##;WjgPiia*^$$v6vS&yZj z9fb^ry(o&*7Ng%!d|EYYoidiK?s^5C#;lBhcG{x%S2YDTsoa33&oxGU#Fn~jq-uvv z%Ux~5eXa<9LU&jVv`fO(Im$LHCx77&=UVY+;uNoTr9u@A4qZmIXeE(W&vT2##T8s) zsUBQBSzSn0{pdzhX}*n2WT^*Q3le?ak0;_ZAb(D?M(>vPqfCv@S9R7hCaFr%c+_gXION(s;}4vgx*v$A zZhZ1vYTc?3>LlT#xHQ;`HqgEepWTD$yDergC<`bRD zMA87QoJaC?rruZRTm~J#ictjJ)NeWJo^Dfw-))rmR=S&FgH}?B*?`OB=S@9jvK3wW zrRtV+MZJHpEtGtLiN|PwCHF#TP7{t1pKXc}CnEY%6%E&ULlabgny&_qV4o`a1K-nW zs|Yi#N}|tr(*b%pxkm}|KU&W6!{!O1B(>Bj)`vb~n!Nt<;1X;aOQY)+Z3V|SRjdV|zdC^)%B0+T&WZ zCCp5M)g8HJL?%zZ%p~I)lF_t$E!u(j3lS_z4PNMb9?d*An_E-lPPX1{k`I_xb4JZl zI}(t#n4({u!iIr>)(O_xsDh(+(ygwU1zY;_zhG2*ZuO~ z4t77!TG@2g&N^8)o5^}vmdY}gWjxEQEK6sZon=mzxmlLUGB3+hSE8%cglYjS|z@w4F^m*|eKY zXR>K8Yp1d{%i26^TUi?l*;(7k+HTg)WNk0&q_PgnIy~!GStp%!ps$m4+^mzyI$qXI zWnGqadDgYEZaVAQSr^rDvu-Bqdf7}Wn_<}u&t|M_CY{aL*^HCTpthN8#>;xCtjDq* z&w5tYOJ_Yh>p5A^&3Z5fSp()s!5%3XBn6A4V3HJUl7dlEuu2MMNdYI!1{@iVEJvmz z+mZ3edSpJ>kHLTp7Gy9XgAEys$Y4bVGcwqb!H^7=WH2RzEg6i-U`+;dGT4*BpbQpe zFe!sg8H~zcRR*&%*pe;NXLU4-P&!_~2;A9DH!_!NCUy9~^ve@WH_cr}j(@TC`~3s7+I&rdCbOn%Xrr zZ1BOs2L~STv zKGNVL4L;J~BMm;%;3Ew_(%>TvKGNVL4L;J~BMm;%;3Ew_(%>TvKGNVL4L;J~BMm;% z;3Ew_(%>TvKGNtPY4DK-A8GKB1|Mngk)|<#1_2rcXc!RV0B|%C&`>~Q0SyM=BMm;% z;3Ew_(%>TvKGNVL4L;J~BMm;%;3Ew_(%>TvKGNVL4L;J~BMm;%;3Ew_(%>TvKGNVL z4L;J~BMm;%;3Ew_(%>TvKGNVL4L;J~BMm;%;3Ew_(%>TvKGNVL4L;J~BMm;%;3Ew_ z(%>TvKGNVL4L;J~BMm;%;KK$VHu$i?hYdb#@L_`w8+_Q{!v-HV_^`o;4L)q}VS^7F zeAwW_1|K%~u)&87K5Xz|gAW^g*xaKVQQK3wqOf)5vbxZuMDA1?TC z!G{YzT=3z74;Os6;KKzUF8FZ4hYLPj@Zo|F7ks$j!v!BM_;A683qD-%;ernre7NAl z1s^W>aKVQQK3wqOf)5vbxZuMDA1?TC!G{YzT=3z74;Os6;KKzUF8FZ4hYLPj@Zo|F z7ks$j!v!BM_;A683qD-%;ernre7NAl1s^W>aKVQQK3wqOf)5vbxZuMDA1?TC!G{Yz zT=0hIY26YC4$O<=lF+yCVQ}t5bFbCfk3Pfh$RBCMj#dm#43SUCJ^fcVxd5+6o{n) zu~r}!3&d)HSS}Fj1!BQKtQd$T1F>cx77fIzfmk*W>jq-sK&%{yr30~cAQlhA>Va53 z5bFnG0Rbxrci)W#@Ze}S);z^O^ql3R@b7`??2+n`nd+${$8ayPw!BzBa^GT&HvFft zm5zk@#Ur)T2-GV0XWc%isHRX;*#0hnEwo?Drz9>G1YdTsi~6Zi8gA-dd4 z(Wk1@%Mi@2=#yZ6IRxL?OO2OtTu;72NP1t^SMi*_5PYbY+RtL$pI%TT-7o2*aJ~n^ zpVU*$7nbj(yFbgc6GZCMV?TW@f$u^IclELkwfafX-M|6WfKK-HQ9j=Z`8{z2%7hFXb`ZqFGm1t9~;_>lj6$9X1AgCykvCX=`sP^ai8P?FBs+$S#Dyv9($+G@$cM zJr~I~L*)LoYUu|`oL;x+l`ysy!q&`iosI-h14MjC;b%|$p$a|EATVtnGOzA)0sPS@ zpr;X6lX)0@AfR8u`CbU`$&jpUAB6qvQD`T{_AOXm@jF6$==3DuktMwOJTrTI{s=Cm zEmW%2BXxR0Riw{PP1hEwwOk3YPlzQ}sWiW|Qn{}-wS@P>>lB7uu~rHEa!ByH(m@47 zRQ_da$<6VtsCA`SWd~-RM*NQJ*mT9}$n@ge%(2;8wQ`Dw?8+|bk6gY7a!0$<_xSYm zk)@?+?2c7V&*G`A(_u|__gW&~1&KGt(oxJNFlsV7Y}s8Fz7tt)h*ioQZUj;x^i)Mx zIXHcmD4tr&IOtQSLg-9ScUky0Wa;G)z#b2Q)?cvxmv_f8gnG-P#{9k$|i zzP^OR4##jvA#Av-dMb|Zg}C0wHSCEH+a(#IG1ulR)AQk`%x{6LE;|OfK10WNLNBH9 zn<1^k*wKpIsoK0-nOmCX*6E0IzNyCoc@_d!H*mPofy3*WD4v0+F58FTv_<=1ZtrAq z2eMYvS!WT?ADx?e3Znj|QJdL4702n5L|tkZ8pm@Pg{sKuRkSYKS70xT&qo^mlX@wQAAz(kxl~?5i$mF6Jru_2 z5zsFE8F5JqN$FI}g`~s1mdNR0#4g(#wGoPIwE^K^?_}`Ev2+ z^D=U;!pF5o1tX2UEI{NOr#GBKaIdcG)e-b)3l5ajPh@nsBmrviOrB z%Z_C|wU;4Qh7r8Zt~Mt>ft+1-N3un$kn4EQMDb$~wF-vjr;p*Tg&p=1)!xbCGmzD# zo2cXQ+m(gtk@=%ICYz1~gVVj0$B#l@m(!4DH|Exzbl7-PJr>CCfxw=GP3&oq)M4Q* zdPGq_)}l7zf>TNSS0T1bim5{wH`1QkTY3C`$Qz2~B-HHoh&~&kjUIYcsuzOzQy}Qp z?lhXO&d=i$)<;fMrY*_HbO`Ic`(@AQg^u(+A5@q>vxmai zuR&OcfuS=MC+@>hwv{DP?m4}c$DRv$U7p?1$3xW&!w1@)*EiAZ`4HW~fpoU2(z@xK z6n{aV1hW@HaEGZ_e2vwSya)Oql)b2zCTKeK&tKdp!R)0F+$UGcUIy7~?!P#awv1W~I~J`*vF3X|XqRv7hg9|^NIl%1r}!g*vZK12 z#NXUc>Fh0#z6x(sug(kq2eRL~RtfBFkkEyVMcTYmOi$lpb8SLN5L z)AK8M8J<*l$C^d3--d`)FoE_$@1TfUK8G-Q)!zC*IeQV0j-jD37XpKkdD~E6zq`?Q)EP{OyB38k{ zy-RosoK*PG+VZpCMg9&;IIW@}VFl3$es7He*oPsY3m#Mq6nF&;Hy>HE2=-Bk=)x-~ zEtG$T5+7Tu1om-A=z?_FL<#P`D6ypTGg^A50OuX6c{o4M@Jb7do4p+@JQn2=-?vqQfcRc$Qb|Rp`fm z-g}wsn~>S%DtPM_qVEiUt8b#&UqJL-y=Wt>^qSEq+aT;t%m$%ze`|$ zg%Y~GSZ(kv^2wv-74yIDqj2`!UfCx6f=JVo72oT33G8oBLQi@?xDLUy7Ju7c`Rwod zW1*(~!oTl#3G5$GLboq3wCn+44$znV$2Q4cUiP!i0TmbuL6ws4sA3b3EUr|JtA$IFgI9v<0um5j-70>>?SK`%Z9Nta;CB%0-ShjpyFKnD9cl`^L z&}~PKQ9{s>+0Xl20RP!4D2P!5zX7rT?W=hHAFB}G(vh}oKj<;Q&#&VB;nUGAc`ZXwO@-|_$Mhg9}I zklNt|n|L!zq3cmR5OeYjokjR*f8;Xy9&;a@Ya_(k zyEM>J-^S7ayRi2%Iek&M+t8||p2me3c7ETB;OC);ZkNDX)*?K`#_`Z|`z4uggycR% zJdMc_+tBY4_aTph4)XiZk{Yoy zqkWZbLzR{m(iafFboZ0L`pf-~oYiIQrf)u|D5xo(VC$^Cx2|}PoYnii0j@;f5@Urg zax$=KCzkDa=*xG1=SN>UYZYRew^Fmu_zxjw4I4-=_{2X85#5ejEo1b?sKx(w_xBF* zCp>aiw=J}#+;9(Tv`~KKN1h{??luUCQA#5SS$F24d!D!Xk+XUqMeh09%U=E$`L26G z>-bdl1b+s@lx@1$RaPR@AyPJY=o8b_PM;9Jxhol}E#O|wZBP4*kkZ}F9OX1{l!gs@ zZ<--J`r$5uKD}mlp)?L|(6JYvd($`W9C+lc9v-%4s%NdjcQm;mu3S);CXLnhf_~X; z?{7JJs1_BD($FfNGW&0$U9F*o^PaSDzUCIrRSWOek^hOu9v(lir3Yi8*2uYPE*V_mc{bw)#-jbX(fZ>V%R+N(An9Hm2Z|7q?E zqPh3AQ*qU)R^jr|LH%>M><5>BdKE5TUDG9(|K^9^DO`THqi#zV(!6%V9{s7;e0O`H z`_QDN(Om)6)+h&YH8eWMjue9ci)N1?a z!JV($adGyMvsTgj)!9|{W_FesAA8dK%`1}EoPWWi{<&AZKTKo8!fYx1N00p`4APUz zgiC31W&Hoel?A~-w;R|k8>Mm{p)KHGv8G?%k}Gey3jd_85Wve7-~J^L(5%f_25zpO zt|S=8d)3K#4>~#j|LNrX|D}_2)ycbUwCw|l7DIghI$p5sv8H~(Rlm5a{Y*{UwruGk z!tO3uNmq-meY;>9tR(c}5g>N?;>BNi=e|eI>b8%!Y#d>eAnuaq$5!n&TNa``bMrAx z;v0ADpcrW>kRr)-&$ud3iqOQ^8b(4 z8Q7#-_tmy_wvHRR-Joh)L~xcS=wGXD{=5gxe=SqAV4n!V%j-Y(&}xI1V96L_zW0Y8 z5Mox>8M*3=9R{4pHLvJ5s&2dI9imIGdEGmdqH+3zd&@QN9e(7j zc%MpCuY<9N|DhlT?ru+T8v1tl5;Oa8`Ca$XVsE!CxutYNOYTWjr0u5%herD7^n%^P zwKzSloL;x9U@iNA^3JUe^7W)I8(l`QX4ucZ9E|Q=HX3~-R)z{i>cM<&2HCAto%S5I5@>+pzsXNgU2o2hM+E>9KcYN{Pj`9>X%j32Z2-%UroI`k-^ZmW}_ z_u`@kyWlmS6Q?n|2qV;K6ZIkq`{S?um5|XFzsi+g?XnrSo^)!yFE~roFP9Q@!|v8~ zmYTl#^3!YHEhdb;e)u+6GU(E@t=gu%bszE&LCt&CLj#Gu?4iNN<}K~R@mBpv^-1bU zSF)))DIo88N9U@euR_7#^aT_=`{NggP4Bh%3*G~N!Ii)0GRVB4?I<2Sgxr&%RgHXS zP;~9I!x!)wCOUy~>bco%8!^#eb)V*{Pj@*@Zf%2bG#@=E(QCI6O!3#e+e=X{b)5$X zFL*1hE3RS?Qm-GgZ~f%&#UQkbPSVtix$4EM5YyDxxaw;imc$G`MVx7bUA~|Hk*HI* zV^hm1g=)*K!rd+hfYz;06`*fv^rNE(t+1aRovV)Czit{Fb?8-Z;;J{rn;p|9Q0mkP z|NKMl8zwM*t$8u9#nGfSbZo9V_L{m9S6!(mQ{1q>)#eY~HkOv%HC#s2r}xVv1QAw$ zJVGG8iw2?Gih6mPeg8)v70WnX#4$>S*juERYS|0s-Y10E?SsC^8m#){+Yf&JHW86` zh;04b>da`1Z$XK#ACW$vz4a~IHV!^=R(JZS?-!l@g_&a;FMQ;zZtv8!jHuK-D)@w# zUj3ARp*W}8nO#e{YM2csuxe)ar1l&{=i9AEpKyO^u`k-4JLG+EhruDPRk$*BFc74C z;AvY$9N$M*7WC8pxw2r~TZ1d$y>JD5O|F0|SI`rOsVz@1b#1w4o`$c<)9^ld8s1k= z6RaWi)zbtK>6))~s^LnHq}Sv*xbhsUnA`*>58!~-ehHlQ=@NKwRkd59V}xKWhLmon d9x+PMuV-|*p458XQ|u=lTbY}qNMBt7|341z?)3lw literal 0 HcmV?d00001 diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.tps b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.tps new file mode 100644 index 000000000..0a45f326c --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.tps @@ -0,0 +1,68 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[CONFIGURATIONS] +"Blinky" +"Debug" +"Debug_RX600_E1_E20_SYSTEM" +"Debug_with_optimisation" +"SimDebug_RX600" +[CURRENT_CONFIGURATION] +"Debug" +[CURRENT_SESSION] +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_PROJECT] +[GENERAL_DATA_CONFIGURATION_Blinky] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Blinky] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug_RX600_E1_E20_SYSTEM] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug_with_optimisation] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_SimDebug_RX600] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_SimDebug_RX600] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_SESSION_SimSessionRX600] +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM] +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/dbsct.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/dbsct.c new file mode 100644 index 000000000..156f0b8f3 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/dbsct.c @@ -0,0 +1,66 @@ +/***********************************************************************/ +/* */ +/* FILE :dbsct.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Setting of B,R Section */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + +/********************************************************************* +* +* Device : RX +* +* File Name : dbsct.c +* +* Abstract : Setting of B,R Section. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include "typedefine.h" + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + _UBYTE *rom_s; /* Start address of the initialized data section in ROM */ + _UBYTE *rom_e; /* End address of the initialized data section in ROM */ + _UBYTE *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + _UBYTE *b_s; /* Start address of non-initialized data section */ + _UBYTE *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +_UBYTE * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W") +}; + +#pragma packoption diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c new file mode 100644 index 000000000..3cd4565f8 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c @@ -0,0 +1,107 @@ +/****************************************************************************** +* DISCLAIMER + +* This software is supplied by Renesas Technology Corp. and is only +* intended for use with Renesas products. No other uses are authorized. + +* This software is owned by Renesas Technology Corp. and is protected under +* all applicable laws, including copyright laws. + +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. + +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +****************************************************************************** +* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : hwsetup.c +* Version : 1.00 +* Description : Power up hardware initializations +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +******************************************************************************/ + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include "iodefine.h" +#include "yrdkrx62ndef.h" +// #include "lcd.h" Uncomment this if an LCD is present. + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/****************************************************************************** +* Function Name: HardwareSetup +* Description : This function does initial setting for CPG port pins used in +* : the Demo including the MII pins of the Ethernet PHY connection. +* Arguments : none +* Return Value : none +******************************************************************************/ +void HardwareSetup(void) +{ + + uint32_t sckcr = 0; + + /* Configure system clocks based on header */ + sckcr += (ICLK_MUL==8) ? (0ul << 24) : (ICLK_MUL==4) ? (1ul << 24) : (ICLK_MUL==2) ? (2ul << 24) : (3ul << 24); + sckcr += (BCLK_MUL==8) ? (0ul << 16) : (BCLK_MUL==4) ? (1ul << 16) : (BCLK_MUL==2) ? (2ul << 16) : (3ul << 16); + sckcr += (PCLK_MUL==8) ? (0ul << 8) : (PCLK_MUL==4) ? (1ul << 8) : (PCLK_MUL==2) ? (2ul << 8) : (3ul << 8); + SYSTEM.SCKCR.LONG = sckcr; + + /* Configure LED pins as outputs */ + LED0_DDR = 1; + LED1_DDR = 1; + LED2_DDR = 1; + LED3_DDR = 1; + LED4_DDR = 1; + LED5_DDR = 1; + LED6_DDR = 1; + LED7_DDR = 1; + LED8_DDR = 1; + LED9_DDR = 1; + LED10_DDR = 1; + LED11_DDR = 1; + + /* Configure LCD pins as outputs - uncomment this if an LCD is present. + LCD_RS_DDR = 1; + LCD_EN_DDR = 1; + LCD_DATA_DDR = 0xF0; */ + + /* Initialize display - uncomment this if an LCD is present. + InitialiseDisplay(); */ +} + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/intprg.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/intprg.c new file mode 100644 index 000000000..b5ef3862f --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/intprg.c @@ -0,0 +1,53 @@ +/***********************************************************************/ +/* */ +/* FILE :intprg.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Interrupt Program */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : intprg.c +* +* Abstract : Interrupt Program. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include "vect.h" +#pragma section IntPRG + +// Exception(Supervisor Instruction) +void Excep_SuperVisorInst(void){/* brk(); */} + +// Exception(Undefined Instruction) +void Excep_UndefinedInst(void){/* brk(); */} + +// Exception(Floating Point) +void Excep_FloatingPoint(void){/* brk(); */} + +// NMI +void NonMaskableInterrupt(void){/* brk(); */} + +// Dummy +void Dummy(void){/* brk(); */} + +// BRK +void Excep_BRK(void){ wait(); } + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src new file mode 100644 index 000000000..70330dadd --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src @@ -0,0 +1,120 @@ + +; Comment out the orginal code + .IF 0 + +;------------------------------------------------------------------------ +; | +; FILE :lowlvl.src | +; DATE :Wed, Jun 16, 2010 | +; DESCRIPTION :Program of Low level | +; CPU TYPE :Other | +; | +; This file is generated by Renesas Project Generator (Ver.4.50). | +; NOTE:THIS IS A TYPICAL EXAMPLE. | +; | +;------------------------------------------------------------------------ + + + .GLB _charput + .GLB _charget + +SIM_IO .EQU 0h + + .SECTION P,CODE +;----------------------------------------------------------------------- +; _charput: +;----------------------------------------------------------------------- +_charput: + MOV.L #IO_BUF,R2 + MOV.B R1,[R2] + MOV.L #1220000h,R1 + MOV.L #PARM,R3 + MOV.L R2,[R3] + MOV.L R3,R2 + MOV.L #SIM_IO,R3 + JSR R3 + RTS + +;----------------------------------------------------------------------- +; _charget: +;----------------------------------------------------------------------- +_charget: + MOV.L #1210000h,R1 + MOV.L #IO_BUF,R2 + MOV.L #PARM,R3 + MOV.L R2,[R3] + MOV.L R3,R2 + MOV.L #SIM_IO,R3 + JSR R3 + MOV.L #IO_BUF,R2 + MOVU.B [R2],R1 + RTS + +;----------------------------------------------------------------------- +; I/O Buffer +;----------------------------------------------------------------------- + .SECTION B,DATA,ALIGN=4 +PARM: .BLKL 1 + .SECTION B_1,DATA +IO_BUF: .BLKB 1 +; .END ; Commented out for conditional assembly + +; Code below is for debug console + .ELSE + +;----------------------------------------------------------------------- +; +; FILE :lowlvl.src +; DATE :Wed, Jul 01, 2009 +; DESCRIPTION :Program of Low level +; CPU TYPE :RX +; +;----------------------------------------------------------------------- + .GLB _charput + .GLB _charget + +FC2E0 .EQU 00084080h +FE2C0 .EQU 00084090h +DBGSTAT .EQU 000840C0h +RXFL0EN .EQU 00001000h +TXFL0EN .EQU 00000100h + + .SECTION P,CODE + +;----------------------------------------------------------------------- +; _charput: +;----------------------------------------------------------------------- +_charput: + .STACK _charput = 00000000h +__C2ESTART: MOV.L #TXFL0EN,R3 + MOV.L #DBGSTAT,R4 +__TXLOOP: MOV.L [R4],R5 + AND R3,R5 + BNZ __TXLOOP +__WRITEFC2E0: MOV.L #FC2E0,R2 + MOV.L R1,[R2] +__CHARPUTEXIT: RTS + +;----------------------------------------------------------------------- +; _charget: +;----------------------------------------------------------------------- +_charget: + .STACK _charget = 00000000h +__E2CSTART: MOV.L #RXFL0EN,R3 + MOV.L #DBGSTAT,R4 +__RXLOOP: MOV.L [R4],R5 + AND R3,R5 + BZ __RXLOOP +__READFE2C0: MOV.L #FE2C0,R2 + MOV.L [R2],R1 +__CHARGETEXIT: RTS + +;----------------------------------------------------------------------- + +; End of conditional code + .ENDIF + + .END + + + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c new file mode 100644 index 000000000..2d02ccad9 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c @@ -0,0 +1,329 @@ +/***********************************************************************/ +/* */ +/* FILE :lowsrc.c */ +/* DATE :Wed, Jun 16, 2010 */ +/* DESCRIPTION :Program of I/O Stream */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX +* +* File Name : lowsrc.c +* +* Abstract : Program of I/O Stream. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include +#include +#include "lowsrc.h" + +/* file number */ +#define STDIN 0 /* Standard input (console) */ +#define STDOUT 1 /* Standard output (console) */ +#define STDERR 2 /* Standard error output (console) */ + +#define FLMIN 0 /* Minimum file number */ +#define _MOPENR 0x1 +#define _MOPENW 0x2 +#define _MOPENA 0x4 +#define _MTRUNC 0x8 +#define _MCREAT 0x10 +#define _MBIN 0x20 +#define _MEXCL 0x40 +#define _MALBUF 0x40 +#define _MALFIL 0x80 +#define _MEOF 0x100 +#define _MERR 0x200 +#define _MLBF 0x400 +#define _MNBF 0x800 +#define _MREAD 0x1000 +#define _MWRITE 0x2000 +#define _MBYTE 0x4000 +#define _MWIDE 0x8000 +/* File Flags */ +#define O_RDONLY 0x0001 /* Read only */ +#define O_WRONLY 0x0002 /* Write only */ +#define O_RDWR 0x0004 /* Both read and Write */ +#define O_CREAT 0x0008 /* A file is created if it is not existed */ +#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */ +#define O_APPEND 0x0020 /* The position is set for next reading/writing */ + /* 0: Top of the file 1: End of file */ + +/* Special character code */ +#define CR 0x0d /* Carriage return */ +#define LF 0x0a /* Line feed */ + +#if defined( __RX ) +const long _nfiles = IOSTREAM; /* The number of files for input/output files */ +#else +const int _nfiles = IOSTREAM; /* The number of files for input/output files */ +#endif +char flmod[IOSTREAM]; /* The location for the mode of opened file. */ + +unsigned char sml_buf[IOSTREAM]; + +#define FPATH_STDIN "C:\\stdin" +#define FPATH_STDOUT "C:\\stdout" +#define FPATH_STDERR "C:\\stderr" + +/* H8 Normal mode ,SH and RX */ +#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +extern char fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +extern char fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); + +/* RX */ +#elif defined( __RX ) +/* Output one character to standard output */ +extern void charput(unsigned char); +/* Input one character from standard input */ +extern unsigned char charget(void); + +/* H8 Advanced mode */ +#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +/* Specified as the number of register which stored paramter is 3 */ +extern char __regparam3 fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +extern char fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); + +/* H8300 and H8300L */ +#elif defined( __300__ ) || defined( __300L__ ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +/* Specified as the number of register which stored paramter is 3 */ +extern char __regparam3 fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +/* Move the file offset */ +extern char __regparam3 fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); +#endif + +#include +FILE *_Files[IOSTREAM]; // structure for FILE +char *env_list[] = { // Array for environment variables(**environ) + "ENV1=temp01", + "ENV2=temp02", + "ENV9=end", + '\0' // Terminal for environment variables +}; + +char **environ = env_list; + +/****************************************************************************/ +/* _INIT_IOLIB */ +/* Initialize C library Functions, if necessary. */ +/* Define USES_SIMIO on Assembler Option. */ +/****************************************************************************/ +void _INIT_IOLIB( void ) +{ + /* A file for standard input/output is opened or created. Each FILE */ + /* structure members are initialized by the library. Each _Buf member */ + /* in it is re-set the end of buffer pointer. */ + + /* Standard Input File */ + if( freopen( FPATH_STDIN, "r", stdin ) == NULL ) + stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stdin->_Mode = _MOPENR; /* Read only attribute */ + stdin->_Mode |= _MNBF; /* Non-buffering for data */ + stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Output File */ + if( freopen( FPATH_STDOUT, "w", stdout ) == NULL ) + stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stdout->_Mode |= _MNBF; /* Non-buffering for data */ + stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */ + + /* Standard Error File */ + if( freopen( FPATH_STDERR, "w", stderr ) == NULL ) + stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stderr->_Mode |= _MNBF; /* Non-buffering for data */ + stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */ +} + +/****************************************************************************/ +/* _CLOSEALL */ +/****************************************************************************/ +void _CLOSEALL( void ) +{ + long i; + + for( i=0; i < _nfiles; i++ ) + { + /* Checks if the file is opened or not */ + if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) ) + fclose( _Files[i] ); /* Closes the file */ + } +} + +/**************************************************************************/ +/* open:file open */ +/* Return value:File number (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +#if defined( __RX ) +long open(const char *name, /* File name */ + long mode, /* Open mode */ + long flg) /* Open flag */ +#else +int open(char *name, /* File name */ + int mode, /* Open mode */ + int flg) /* Open flag */ +#endif +{ + + + if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */ + { + if( ( mode & O_RDONLY ) == 0 ) return -1; + flmod[STDIN] = mode; + return STDIN; + } + else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */ + { + if( ( mode & O_WRONLY ) == 0 ) return -1; + flmod[STDOUT] = mode; + return STDOUT; + } + else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */ + { + if( ( mode & O_WRONLY ) == 0 ) return -1; + flmod[STDERR] = mode; + return STDERR; + } + else return -1; /*Others */ +} + +#if defined( __RX ) +long close( long fileno ) +#else +int close( int fileno ) +#endif +{ + return 1; +} + +/**************************************************************************/ +/* write:Data write */ +/* Return value:Number of write characters (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +#if defined( __RX ) +long write(long fileno, /* File number */ + const unsigned char *buf, /* The address of destination buffer */ + long count) /* The number of chacter to write */ +#else +int write(int fileno, /* File number */ + char *buf, /* The address of destination buffer */ + int count) /* The number of chacter to write */ +#endif +{ + long i; /* A variable for counter */ + unsigned char c; /* An output character */ + + /* Checking the mode of file , output each character */ + /* Checking the attribute for Write-Only, Read-Only or Read-Write */ + if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR) + { + if( fileno == STDIN ) return -1; /* Standard Input */ + else if( (fileno == STDOUT) || (fileno == STDERR) ) + /* Standard Error/output */ + { + for( i = count; i > 0; --i ) + { + c = *buf++; + charput(c); + } + return count; /*Return the number of written characters */ + } + else return -1; /* Incorrect file number */ + } + else return -1; /* An error */ +} + +#if defined( __RX ) +long read( long fileno, unsigned char *buf, long count ) +#else +int read( int fileno, char *buf, unsigned int count ) +#endif +{ + long i; + + /* Checking the file mode with the file number, each character is input and stored the buffer */ + + if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){ + for(i = count; i > 0; i--){ + *buf = charget(); + if(*buf==CR){ /* Replace the new line character */ + *buf = LF; + } + buf++; + } + return count; + } + else { + return -1; + } +} + +#if defined( __RX ) +long lseek( long fileno, long offset, long base ) +#else +long lseek( int fileno, long offset, int base ) +#endif +{ + return -1L; +} + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/resetprg.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/resetprg.c new file mode 100644 index 000000000..58f1cc983 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/resetprg.c @@ -0,0 +1,129 @@ +/***********************************************************************/ +/* */ +/* FILE :resetprg.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Reset Program */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : resetprg.c +* +* Abstract : Reset Program. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "typedefine.h" +#include "stacksct.h" + +#pragma inline_asm Change_PSW_PM_to_UserMode +static void Change_PSW_PM_to_UserMode(void); + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset_PC(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus // Use SIM I/O +extern "C" { +#endif +extern void _INIT_IOLIB(void); +extern void _CLOSEALL(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 +#define FPSW_init 0x00000100 + +//extern void srand(_UINT); // Remove the comment when you use rand() +//extern _SBYTE *_s1ptr; // Remove the comment when you use strtok() + +//#ifdef __cplusplus // Use Hardware Setup +//extern "C" { +//#endif +//extern void HardwareSetup(void); +//#ifdef __cplusplus +//} +//#endif + +//#ifdef __cplusplus // Remove the comment when you use global class object +//extern "C" { // Sections C$INIT and C$END will be generated +//#endif +//extern void _CALL_INIT(void); +//extern void _CALL_END(void); +//#ifdef __cplusplus +//} +//#endif + +#pragma section ResetPRG + +#pragma entry PowerON_Reset_PC + +void PowerON_Reset_PC(void) +{ + set_intb((unsigned long)__sectop("C$VECT")); + set_fpsw(FPSW_init); + + _INITSCT(); + +// _INIT_IOLIB(); // Use SIM I/O + +// errno=0; // Remove the comment when you use errno +// srand((_UINT)1); // Remove the comment when you use rand() +// _s1ptr=NULL; // Remove the comment when you use strtok() + +// HardwareSetup(); // Use Hardware Setup + nop(); + +// _CALL_INIT(); // Remove the comment when you use global class object + + set_psw(PSW_init); // Set Ubit & Ibit for PSW +// Change_PSW_PM_to_UserMode(); // Change PSW PMbit (SuperVisor->User) + ( void ) Change_PSW_PM_to_UserMode; + + main(); + + _CLOSEALL(); // Use SIM I/O + +// _CALL_END(); // Remove the comment when you use global class object + + brk(); +} + +static void Change_PSW_PM_to_UserMode(void) +{ + MVFC PSW,R1 + OR #00100000h,R1 + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +} diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/sbrk.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/sbrk.c new file mode 100644 index 000000000..98e5bcbeb --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/sbrk.c @@ -0,0 +1,28 @@ +#include +#include +#define HEAPSIZE 0x400 +signed char *sbrk( size_t size ); +union HEAP_TYPE +{ + signed long dummy; + signed char heap[HEAPSIZE]; +}; +static union HEAP_TYPE heap_area; + +/* End address allocated by sbrk */ +static signed char *brk = ( signed char * ) &heap_area; +signed char *sbrk( size_t size ) +{ + signed char *p; + if( brk + size > heap_area.heap + HEAPSIZE ) + { + p = ( signed char * ) - 1; + } + else + { + p = brk; + brk += size; + } + + return p; +} diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c new file mode 100644 index 000000000..d2dec0b3b --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c @@ -0,0 +1,64 @@ +/***********************************************************************/ +/* */ +/* FILE :vecttbl.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Initialize of Vector Table */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : vecttbl.c +* +* Abstract : Initialize of Vector Table. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include "vect.h" + +#pragma section C FIXEDVECT + +void* const Fixed_Vectors[] = { +//;0xffffffd0 Exception(Supervisor Instruction) + (void*) Excep_SuperVisorInst, +//;0xffffffd4 Reserved + Dummy, +//;0xffffffd8 Reserved + Dummy, +//;0xffffffdc Exception(Undefined Instruction) + (void*) Excep_UndefinedInst, +//;0xffffffe0 Reserved + Dummy, +//;0xffffffe4 Exception(Floating Point) + (void*) Excep_FloatingPoint, +//;0xffffffe8 Reserved + Dummy, +//;0xffffffec Reserved + Dummy, +//;0xfffffff0 Reserved + Dummy, +//;0xfffffff4 Reserved + Dummy, +//;0xfffffff8 NMI + (void*) NonMaskableInterrupt, +//;0xfffffffc RESET +//;<> +//;Power On Reset PC +PowerON_Reset_PC +//;<> +}; diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf new file mode 100644 index 000000000..eab5820b9 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf @@ -0,0 +1,407 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"FIRST_CONNECTION_TAG" "NO" +"MRULABELS_DATAMANAGER_KEY" "00000000|FFFFFFFF|88218|000870B4|000870AE|88204|88208|18b8" +"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" +"{228DB593-0AB2-4EBE-A098-A2CABF094E46}RamMonitorCtrlViews" "0" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}ECXLABEL_ADDDLG_ADDR" "" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileDir" "" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileName" "" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "88218" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "FFFFFFFF" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "00000000" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SET_DEST_ADDRESS" "000870B4" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_END_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_START_ADDRESS" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshEnableTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshIntervalTopPane" "100" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DataLength" "1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispAddressTopPane" "553134" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispCode" "42208" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispColumnCount" "16" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispCode" "1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispFloat" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispLabel" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispRegister" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsRegFollowEnableTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0LabelWidth" "96" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0Radix" "16" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegFollowRegTblIDTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegisterWidth" "96" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollEndAddress" "-1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollStartAddress" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0StartUpSymbolTopPane" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshEnableTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshIntervalTopPane" "100" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DataLength" "1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispAddressTopPane" "553134" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispCode" "42208" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispColumnCount" "16" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispCode" "1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispFloat" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispLabel" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispRegister" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsRegFollowEnableTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0LabelWidth" "96" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0Radix" "16" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegFollowRegTblIDTopPane" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegisterWidth" "96" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollEndAddress" "-1" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollStartAddress" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0StartUpSymbolTopPane" "" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" +"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileDir" "" +"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileName" "" +"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlViews" "0" +"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileDir" "" +"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileName" "" +"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_DENORMAL_MODE" "16777216" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_ROUND_MODE" "768" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_0" "00000000000071F0" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_1" "0000000000006FA8" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_10" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_11" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_12" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_13" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_14" "000000000000CDBC" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_15" "0000000000006FA8" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_16" "00000000000071F0" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_17" "000000000000D354" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_18" "0000000004030001" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_19" "00000000FFF88980" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_2" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_20" "00000000FFF81644" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_21" "0000000080000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_22" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_23" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_24" "0000000000000100" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_25" "1234567887650000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "0000000000000001" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "0000000000000000" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "0000000000006A68" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_8" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_9" "00000000A5A5A5A5" +"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_COUNT" "26" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +"{855C64C3-E49C-4450-9BCA-C9822566D214}OSObjectCtrlViews" "0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_ADDRESS_NAME" "" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "47,153,35" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "33" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "47,153,35" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "33" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_PALETTE_NAME" "" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_REDRAW_CONTINUOUSLY" "0,2" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "4" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "234" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "190" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "cErrorText, 10, 0, P, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth12" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInitial_Radix" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchRecord" "" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchSave" "" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndUpdate_Interval" "100" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlDCEnable" "1" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlLocalEchoEnable" "0" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlLogFileName" "" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlPortBaudIndex" "0" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlPortName" "" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlSendDataTimeout" "50" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleCtrlViews" "1" +"{B39CE26B-928D-4241-BF8F-E15980C81200}DebugConsoleWndInstanceKey0" "{WK_00000001_DEBUGCONSOLE}RTOSDemoSessionRX600_E1_E20_SYSTEM" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopCheckAfter" "0" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopCheckBefore" "0" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopExpAfter" "" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}StartStopExpBefore" "" +"{B6AE2E1F-5221-4A44-91C2-8C3097B41A69}T_SESSION_IS_SAVED" "YES" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}ElfDwarf2Objects" "1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_ARRAY_EXPAND_LIMIT" "-1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_STATIC_MEM_EXPAND" "1" +"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" +"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlIOFile" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileDir" "$(CONFIGDIR)" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileName" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOSelection IOWnd0" "" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "108" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp0" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp1" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp10" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp11" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp12" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp13" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp14" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp15" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp16" "1" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp17" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp18" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp19" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp2" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp20" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp21" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp22" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp23" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp24" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp25" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp26" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp27" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp28" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp29" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp3" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp30" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp31" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp32" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp33" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp34" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp35" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp36" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp37" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp38" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp39" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp4" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp40" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp41" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp42" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp43" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp44" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp45" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp46" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp47" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp48" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp49" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp5" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp50" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp51" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp52" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp53" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp54" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp55" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp56" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp57" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp58" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp59" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp6" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp60" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp61" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp62" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp63" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp64" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp65" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp66" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp67" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp68" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp69" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp7" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp70" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp71" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp72" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp73" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp74" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp75" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp76" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp77" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp78" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp79" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp8" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp80" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp81" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp82" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp9" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "16" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth0" "200" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth1" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth2" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth3" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ScrollHorz" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ScrollVert" "0" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlAnalyzeViews" "0" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlFileSaveDirectory" "" +"{F923CED3-3318-4B43-B931-0AE76B289176}TaskTraceCtrlTraceViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_CmdLine}" "WINDOW" 59422 0 1 "0.07" 218 0 0 100 100 17 0 "32771|32772|32778|<>|32773|32774|<>" "0.0" +"{WK_00000001_DEBUGCONSOLE}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59421 0 1 "1.00" 307 0 0 350 200 17 0 "57634|57637|57633|<>|32781|32782|<>|32780|32785|32787" "0.0" +"{WK_00000001_DISASSEMBLY}" "WINDOW" 0 0 0 "0.00" 0 0 0 1062 571 9 0 "" "0.0" +"{WK_00000001_IO}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59422 0 3 "0.58" 218 0 0 350 200 17 0 "32817|32826|32819|32820|32821" "0.0" +"{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59422 0 0 "0.64" 289 0 0 350 200 2065 0 "42202|42203|42204|42233|<>|42206|42205|42230|42229|42207|<>|42208|42209|42210|49076|42228|42227|<>|42231|42232|42234|42235|<>|42211|<>" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 218 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59421 0 0 "1.00" 307 0 0 350 200 18 0 "" "0.0" +"{WK_00000001_WATCH}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59422 0 1 "0.03" 218 0 0 853 610 18 0 "32781|32783|<>|32771|32829|32772|32827|32773|<>|32786|<>|32810|32811" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 214 560 340 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000011_CPU}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000015_PERFORMANCE}" "TOOLBAR 0" 59419 2 10 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 11 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000025_HELPSYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000027_EVENT}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" +[TARGET_NAME] +"RX600 E1/E20 SYSTEM" "" 0 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +"SBK_TAR_EMUE100|Exception" 1 +"SBK_TAR_EMUE100|BreakCondition" 1 +"SBK_TAR_EMUE100|TaskID" 1 +"SBK_TAR_EMUE100|ExecutionTime" 1 +"SBK_TAR_EMUE100|PC" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"Unknown Options" +[DOWNLOAD_MODULES] +"$(CONFIGDIR)\$(PROJECTNAME).abs" 0 "Elf/Dwarf2" 0 1 1 0 +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"Elf/Dwarf2" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.ini b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.ini new file mode 100644 index 000000000..e2ed2bbbb --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.ini @@ -0,0 +1,30 @@ +[Init_DeviceSetting] +DebugMode=0 +PowerOut=0 +ResetRelease=0 +EmulatorSerial= +McuGroup=RX62N Group +Device=R5F562N8 +McuFileDir=RX62NGr +SupplyVoltage=-1 +[Init_CommunicationClock] +JtagClock=16.5 +JtagClockValue=10 +[Init_EmulatorSetting] +FirstStartUp=0 +HideNext=0 +ConnectionDlgAutoClose=1 +[CFG_MCU] +PrevDevice=R5F562N8 +ProcessorMode=0 +EXTAL=12.5000 +WorkRam=3000 +[CFG_SYSTEM] +CpuReWrite=0 +PerfCounterUser=0 +TraceDebugAs=0 +[CFG_FLASHCLEAR_R5F562N8_00] +BlockCount=54 +BlockData=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +[Config_Property] +HideNext=0 diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SimSessionRX600.hsf b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SimSessionRX600.hsf new file mode 100644 index 000000000..00cf3324e --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SimSessionRX600.hsf @@ -0,0 +1,72 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_FALSE_STORE_TAG" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +0 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +[TARGET_NAME] +"RX600 Simulator" "" 0 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" +[DOWNLOAD_MODULES] +"$(CONFIGDIR)\$(PROJECTNAME).abs" 0 "Elf/Dwarf2" 0 0 1 0 +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/IntQueueTimer.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/IntQueueTimer.h new file mode 100644 index 000000000..ce40d7e29 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/IntQueueTimer.h @@ -0,0 +1,62 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/iodefine.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/iodefine.h new file mode 100644 index 000000000..fd4dfcd54 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/iodefine.h @@ -0,0 +1,7139 @@ +/********************************************************************************/ +/* */ +/* Device : RX/RX600/RX62N */ +/* File Name : ioedfine.h */ +/* Abstract : Definition of I/O Register. */ +/* History : V1.1 (2010-04-21) [Hardware Manual Revision : 0.50] */ +/* Note : This is a typical example. */ +/* */ +/* Copyright(c) 2010 Renesas Electronics Corp. */ +/* And Renesas Solutions Corp. ,All Rights Reserved. */ +/* */ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX62N */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[0x53].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[0x80].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTUA,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/********************************************************************************/ +#ifndef __RX62NIODEFINE_HEADER__ +#define __RX62NIODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short MDE:1; + unsigned short :5; + unsigned short MD1:1; + unsigned short MD0:1; + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short UBTS:1; + unsigned short :1; + unsigned short BOTS:1; + unsigned short BSW:2; + unsigned short EXB:1; + unsigned short IROM:1; + } BIT; + } MDSR; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :1; + unsigned short STS:5; + unsigned short :8; + } BIT; + } SBYCR; + unsigned char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long :4; + unsigned long MSTPA23:1; + unsigned long MSTPA22:1; + unsigned long :2; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long :2; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long MSTPA8:1; + unsigned long :2; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :4; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long :1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long MSTPB20:1; + unsigned long MSTPB19:1; + unsigned long MSTPB18:1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long MSTPB15:1; + unsigned long :14; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long MSTPC1:1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long PSTOP0:1; + unsigned long :2; + unsigned long BCK:4; + unsigned long :4; + unsigned long PCK:4; + unsigned long :8; + } BIT; + } SCKCR; + unsigned char wk4[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + unsigned char wk5[15]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short OSTDE:1; + unsigned short OSTDF:1; + unsigned short :6; + } BIT; + } OSTDCR; + unsigned char wk6[49726]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char RAMCUT2:1; + unsigned char RAMCUT1:1; + unsigned char :3; + unsigned char RAMCUT0:1; + } BIT; + } DPSBYCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char WTSTS:6; + } BIT; + } DPSWCR; + union { + unsigned char BYTE; + struct { + unsigned char DNMIE:1; + unsigned char DUSBE:1; + unsigned char DRTCE:1; + unsigned char DLVDE:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER; + union { + unsigned char BYTE; + struct { + unsigned char DNMIF:1; + unsigned char DUSBF:1; + unsigned char DRTCFF:1; + unsigned char DLVDF:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR; + union { + unsigned char BYTE; + struct { + unsigned char DNMIEG:1; + unsigned char :3; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :4; + unsigned char LVD2F:1; + unsigned char LVD1F:1; + unsigned char PORF:1; + } BIT; + } RSTSR; + unsigned char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SUBSTOP:1; + } BIT; + } SUBOSCCR; + unsigned char wk8[1]; + unsigned char LVDKEYR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2E:1; + unsigned char LVD2RI:1; + unsigned char :2; + unsigned char LVD1E:1; + unsigned char LVD1RI:1; + unsigned char :2; + } BIT; + } LVDCR; + unsigned char wk9[2]; + unsigned char DPSBKR[32]; +}; + +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + unsigned char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + unsigned char wk3[7414]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + unsigned char wk4[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + unsigned char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + unsigned char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + unsigned char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + unsigned char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + unsigned char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :5; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + unsigned char wk11[1926]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + unsigned char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + unsigned char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + unsigned char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + unsigned char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + unsigned char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + unsigned char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + unsigned char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + unsigned char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + unsigned char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + unsigned char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + unsigned char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + unsigned char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + unsigned char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + unsigned char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + unsigned char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + unsigned char wk27[900]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BSIZE:2; + unsigned char :3; + unsigned char EXENB:1; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EMODE:1; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BE:1; + } BIT; + } SDAMOD; + unsigned char wk28[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SFEN:1; + } BIT; + } SDSELF; + unsigned char wk29[3]; + union { + unsigned short WORD; + struct { + unsigned short REFW:4; + unsigned short RFC:12; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RFEN:1; + } BIT; + } SDRFEN; + unsigned char wk30[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char INIRQ:1; + } BIT; + } SDICR; + unsigned char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short PRC:3; + unsigned short ARFC:4; + unsigned short ARFI:4; + } BIT; + } SDIR; + unsigned char wk32[26]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MXC:2; + } BIT; + } SDADR; + unsigned char wk33[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RAS:3; + unsigned long :2; + unsigned long RCD:2; + unsigned long RP:3; + unsigned long WR:1; + unsigned long :5; + unsigned long CL:3; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short MR:15; + } BIT; + } SDMOD; + unsigned char wk34[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SRFST:1; + unsigned char INIST:1; + unsigned char :2; + unsigned char MRSST:1; + } BIT; + } SDSR; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + unsigned char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + unsigned char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + unsigned char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + unsigned char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + unsigned char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char :1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } EDMAST; + unsigned char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[254]; + unsigned char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[254]; + unsigned char wk47[2]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + unsigned char wk50[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + unsigned char wk51[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + unsigned char wk52[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[144]; + unsigned char wk67[112]; + unsigned char DMRSR0; + unsigned char wk68[3]; + unsigned char DMRSR1; + unsigned char wk69[3]; + unsigned char DMRSR2; + unsigned char wk70[3]; + unsigned char DMRSR3; + unsigned char wk71[243]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[16]; + unsigned char wk72[112]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTST:1; + unsigned char LVDST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTEN:1; + unsigned char LVDEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OSTCLR:1; + unsigned char :1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + unsigned char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +union un_wdt { + struct { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TMS:1; + unsigned char TME:1; + unsigned char :2; + unsigned char CKS:3; + } BIT; + } TCSR; + unsigned char TCNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char WOVF:1; + unsigned char RSTE:1; + unsigned char :6; + } BIT; + } RSTCSR; + } READ; + struct { + unsigned short WINA; + unsigned short WINB; + } WRITE; +}; + +struct st_iwdt { + unsigned char IWDTRR; + unsigned char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; +}; + +struct st_ad { + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ADIE:1; + unsigned char ADST:1; + unsigned char :1; + unsigned char CH:4; + } BIT; + } ADCSR; + union { + unsigned char BYTE; + struct { + unsigned char TRGS:3; + unsigned char :1; + unsigned char CKS:2; + unsigned char MODE:2; + } BIT; + } ADCR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } ADDPR; + unsigned char ADSSTR; + unsigned char wk1[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DIAG:2; + } BIT; + } ADDIAGR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + unsigned char :5; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + unsigned char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + unsigned char wk1[1]; + unsigned char TCORA; + unsigned char wk2[1]; + unsigned char TCORB; + unsigned char wk3[1]; + unsigned char TCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_sci { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char :1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char :2; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSLP3:1; + unsigned char SSLP2:1; + unsigned char SSLP1:1; + unsigned char SSLP0:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char SPOM:1; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPR7:1; + unsigned char SPR6:1; + unsigned char SPR5:1; + unsigned char SPR4:1; + unsigned char SPR3:1; + unsigned char SPR2:1; + unsigned char SPR1:1; + unsigned char SPR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char SLSEL:2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + unsigned char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BCD:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + unsigned char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + unsigned char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + unsigned char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDRE:1; + } BIT; + } TDER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + unsigned char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + unsigned char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + unsigned char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk0[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char wk3[7]; + unsigned short TCNT; + unsigned char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu4 { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + unsigned char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + unsigned char wk3[8]; + unsigned short TCNT; + unsigned char wk4[8]; + unsigned short TGRA; + unsigned short TGRB; + unsigned char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + unsigned char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + unsigned char wk9[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; +}; + +struct st_mtu5 { + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRU; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + unsigned char wk1[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + unsigned char wk2[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCRW; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + unsigned char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + unsigned char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short POE3F:1; + unsigned short POE2F:1; + unsigned short POE1F:1; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short POE3M:2; + unsigned short POE2M:2; + unsigned short POE1M:2; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + unsigned short :8; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short POE7F:1; + unsigned short POE6F:1; + unsigned short POE5F:1; + unsigned short POE4F:1; + unsigned short :3; + unsigned short PIE2:1; + unsigned short POE7M:2; + unsigned short POE6M:2; + unsigned short POE5M:2; + unsigned short POE4M:2; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short OSF2:1; + unsigned short :5; + unsigned short OCE2:1; + unsigned short OIE2:1; + unsigned short :8; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE3:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CH6HIZ:1; + unsigned char CH910HIZ:1; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char PE7ZE:1; + unsigned char PE6ZE:1; + unsigned char PE5ZE:1; + unsigned char PE4ZE:1; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short P1CZEA:1; + unsigned short P2CZEA:1; + unsigned short P3CZEA:1; + unsigned short :1; + unsigned short P1CZEB:1; + unsigned short P2CZEB:1; + unsigned short P3CZEB:1; + unsigned short :1; + unsigned short P4CZE:1; + unsigned short P5CZE:1; + unsigned short P6CZE:1; + unsigned short :4; + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE9F:1; + unsigned short :2; + unsigned short POE9E:1; + unsigned short PIE4:1; + unsigned short :6; + unsigned short POE9M:2; + } BIT; + } ICSR4; +}; + +struct st_s12ad { + union { + unsigned char BYTE; + struct { + unsigned char ADST:1; + unsigned char ADCS:1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char CKS:2; + unsigned char TRGE:1; + unsigned char EXTRG:1; + } BIT; + } ADCSR; + unsigned char wk0[3]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANS:8; + } BIT; + } ADANS; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS:8; + } BIT; + } ADADS; + unsigned char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ADC:2; + } BIT; + } ADADC; + unsigned char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :9; + unsigned short ACE:1; + unsigned short :5; + } BIT; + } ADCER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char ADSTRS:4; + } BIT; + } ADSTRGR; + unsigned char wk4[15]; + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned short ADDRE; + unsigned short ADDRF; + unsigned short ADDRG; + unsigned short ADDRH; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; + unsigned char wk4[63]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DDR; + unsigned char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DR; + unsigned char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PORT; + unsigned char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ICR; + unsigned char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_ioport { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PF0CSE; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PF1CSS; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PF2CSS; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PF3BUS; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char ADRLE:2; + } BIT; + } PF4BUS; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char :2; + unsigned char ADRHMS:1; + unsigned char :1; + } BIT; + } PF5BUS; + union { + unsigned char BYTE; + struct { + unsigned char SDCLKE:1; + unsigned char DQM1E:1; + unsigned char :1; + unsigned char MDSDE:1; + unsigned char :2; + unsigned char WAITS:2; + } BIT; + } PF6BUS; + union { + unsigned char BYTE; + struct { + unsigned char EDMA1S:2; + unsigned char EDMA0S:2; + unsigned char :4; + } BIT; + } PF7DMA; + union { + unsigned char BYTE; + struct { + unsigned char ITS15:1; + unsigned char :1; + unsigned char ITS13:1; + unsigned char :1; + unsigned char ITS11:1; + unsigned char ITS10:1; + unsigned char ITS9:1; + unsigned char ITS8:1; + } BIT; + } PF8IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ITS7:1; + unsigned char ITS6:1; + unsigned char ITS5:1; + unsigned char ITS4:1; + unsigned char ITS3:1; + unsigned char ITS2:1; + unsigned char ITS1:1; + unsigned char ITS0:1; + } BIT; + } PF9IRQ; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ADTRG0S:1; + } BIT; + } PFAADC; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char TMR3S:1; + unsigned char TMR2S:1; + unsigned char :2; + } BIT; + } PFBTMR; + union { + unsigned char BYTE; + struct { + unsigned char TCLKS:1; + unsigned char MTUS6:1; + unsigned char MTUS5:1; + unsigned char MTUS4:1; + unsigned char MTUS3:1; + unsigned char MTUS2:1; + unsigned char MTUS1:1; + unsigned char MTUS0:1; + } BIT; + } PFCMTU; + union { + unsigned char BYTE; + struct { + unsigned char TCLKS:1; + unsigned char MTUS6:1; + unsigned char :6; + } BIT; + } PFDMTU; + union { + unsigned char BYTE; + struct { + unsigned char EE:1; + unsigned char :2; + unsigned char PHYMODE:1; + unsigned char ENETE3:1; + unsigned char ENETE2:1; + unsigned char ENETE1:1; + unsigned char ENETE0:1; + } BIT; + } PFENET; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCI6S:1; + unsigned char :2; + unsigned char SCI3S:1; + unsigned char SCI2S:1; + unsigned char SCI1S:1; + unsigned char :1; + } BIT; + } PFFSCI; + union { + unsigned char BYTE; + struct { + unsigned char SSL3E:1; + unsigned char SSL2E:1; + unsigned char SSL1E:1; + unsigned char SSL0E:1; + unsigned char MISOE:1; + unsigned char MOSIE:1; + unsigned char RSPCKE:1; + unsigned char RSPIS:1; + } BIT; + } PFGSPI; + union { + unsigned char BYTE; + struct { + unsigned char SSL3E:1; + unsigned char SSL2E:1; + unsigned char SSL1E:1; + unsigned char SSL0E:1; + unsigned char MISOE:1; + unsigned char MOSIE:1; + unsigned char RSPCKE:1; + unsigned char RSPIS:1; + } BIT; + } PFHSPI; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CAN0E:1; + } BIT; + } PFJCAN; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char USBE:1; + unsigned char PDHZS:1; + unsigned char PUPHZS:1; + unsigned char USBMD:2; + } BIT; + } PFKUSB; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char USBE:1; + unsigned char PDHZS:1; + unsigned char PUPHZS:1; + unsigned char USBMD:2; + } BIT; + } PFLUSB; + union { + unsigned char BYTE; + struct { + unsigned char POE7E:1; + unsigned char POE6E:1; + unsigned char POE5E:1; + unsigned char POE4E:1; + unsigned char POE3E:1; + unsigned char POE2E:1; + unsigned char POE1E:1; + unsigned char POE0E:1; + } BIT; + } PFMPOE; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char POE9E:1; + unsigned char POE8E:1; + } BIT; + } PFNPOE; +}; + +struct st_flash { + unsigned char DMMY; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + unsigned char wk0[7799160]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char FRDMD:1; + unsigned char :4; + } BIT; + } FMODR; + unsigned char wk1[13]; + union { + unsigned char BYTE; + struct { + unsigned char ROMAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFLAE:1; + unsigned char :1; + unsigned char DFLRPE:1; + unsigned char DFLWPE:1; + } BIT; + } FASTAT; + union { + unsigned char BYTE; + struct { + unsigned char ROMAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFLAEIE:1; + unsigned char :1; + unsigned char DFLRPEIE:1; + unsigned char DFLWPEIE:1; + } BIT; + } FAEINT; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + unsigned char wk2[45]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE07:1; + unsigned short DBRE06:1; + unsigned short DBRE05:1; + unsigned short DBRE04:1; + unsigned short DBRE03:1; + unsigned short DBRE02:1; + unsigned short DBRE01:1; + unsigned short DBRE00:1; + } BIT; + } DFLRE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE15:1; + unsigned short DBRE14:1; + unsigned short DBRE13:1; + unsigned short DBRE12:1; + unsigned short DBRE11:1; + unsigned short DBRE10:1; + unsigned short DBRE09:1; + unsigned short DBRE08:1; + } BIT; + } DFLRE1; + unsigned char wk3[12]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE07:1; + unsigned short DBWE06:1; + unsigned short DBWE05:1; + unsigned short DBWE04:1; + unsigned short DBWE03:1; + unsigned short DBWE02:1; + unsigned short DBWE01:1; + unsigned short DBWE00:1; + } BIT; + } DFLWE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE15:1; + unsigned short DBWE14:1; + unsigned short DBWE13:1; + unsigned short DBWE12:1; + unsigned short DBWE11:1; + unsigned short DBWE10:1; + unsigned short DBWE09:1; + unsigned short DBWE08:1; + } BIT; + } DFLWE1; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short FCRME:1; + } BIT; + } FCURAME; + unsigned char wk4[15194]; + union { + unsigned char BYTE; + struct { + unsigned char FRDY:1; + unsigned char ILGLERR:1; + unsigned char ERSERR:1; + unsigned char PRGERR:1; + unsigned char SUSRDY:1; + unsigned char :1; + unsigned char ERSSPD:1; + unsigned char PRGSPD:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char FCUERR:1; + unsigned char :2; + unsigned char FLOCKST:1; + unsigned char :4; + } BIT; + } FSTATR1; + union { + unsigned short WORD; + struct { + unsigned short FEKEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRY0:1; + } BIT; + } FENTRYR; + union { + unsigned short WORD; + struct { + unsigned short FPKEY:8; + unsigned short :7; + unsigned short FPROTCN:1; + } BIT; + } FPROTR; + union { + unsigned short WORD; + struct { + unsigned short FPKEY:8; + unsigned short :7; + unsigned short FRESET:1; + } BIT; + } FRESETR; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + unsigned char wk6[12]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short BCADR:8; + unsigned short :2; + unsigned short BCSIZE:1; + } BIT; + } DFLBCCNT; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PEERRST:8; + } BIT; + } FPESTAT; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short BCST:1; + } BIT; + } DFLBCSTAT; + unsigned char wk7[24]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PCKA:8; + } BIT; + } PCKAR; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char F64HZ:1; + unsigned char F32HZ:1; + unsigned char F16HZ:1; + unsigned char F8HZ:1; + unsigned char F4HZ:1; + unsigned char F2HZ:1; + unsigned char F1HZ:1; + unsigned char :1; + } BIT; + } R64CNT; + unsigned char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + unsigned char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + unsigned char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOUR10:2; + unsigned char HOUR1:4; + } BIT; + } RHRCNT; + unsigned char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAY:3; + } BIT; + } RWKCNT; + unsigned char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DAY10:2; + unsigned char DAY1:4; + } BIT; + } RDAYCNT; + unsigned char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + unsigned char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1000:4; + unsigned short YEAR100:4; + unsigned short YEAR10:4; + unsigned short YEAR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + unsigned char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + unsigned char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char HOUR10:2; + unsigned char HOUR1:4; + } BIT; + } RHRAR; + unsigned char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAY:3; + } BIT; + } RWKAR; + unsigned char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DAY10:2; + unsigned char DAY1:4; + } BIT; + } RDAYAR; + unsigned char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + unsigned char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1000:4; + unsigned short YEAR100:4; + unsigned short YEAR10:4; + unsigned short YEAR1:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + unsigned char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PES:3; + unsigned char :1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + unsigned char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCOE:1; + unsigned char ADJ:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + union { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + union { + unsigned short WORD; + struct { + unsigned char :8; + unsigned char :4; + unsigned char DLC:4; + } BIT; + } DLC; + unsigned char DATA[8]; + union{ + unsigned short WORD; + struct { + unsigned char TSH; + unsigned char TSL; + } BYTE; + } TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + unsigned long MKIVLR; + unsigned long MIER; + unsigned char wk32[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :8; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :3; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; + } BIT; + } SYSCFG; + unsigned char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short :3; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + unsigned char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + unsigned char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + unsigned char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + unsigned char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + unsigned char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } CFIFOCTR; + unsigned char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short TLN:1; + unsigned short DTLN:8; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + unsigned short :8; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :4; + } BIT; + } INTENB1; + unsigned char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + unsigned short :4; + } BIT; + } SOFCFG; + unsigned char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :4; + } BIT; + } INTSTS1; + unsigned char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BENP:1; + unsigned short PIPE8BENP:1; + unsigned short PIPE7BENP:1; + unsigned short PIPE6BENP:1; + unsigned short PIPE5BENP:1; + unsigned short PIPE4BENP:1; + unsigned short PIPE3BENP:1; + unsigned short PIPE2BENP:1; + unsigned short PIPE1BENP:1; + unsigned short PIPE0BENP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + unsigned short :15; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + unsigned char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short :4; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + unsigned char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + unsigned char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + unsigned char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short XPS:1; + unsigned short MXPS:8; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + unsigned char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + unsigned char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD5; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long DVSTS1:1; + unsigned long :1; + unsigned long DOVCB1:1; + unsigned long DOVCA1:1; + unsigned long :2; + unsigned long DM1:1; + unsigned long DP1:1; + unsigned long DVBSTS0:1; + unsigned long :1; + unsigned long DOVCB0:1; + unsigned long DOVCA0:1; + unsigned long :2; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :3; + unsigned long FIXPHY1:1; + unsigned long :3; + unsigned long SRPC1:1; + unsigned long :3; + unsigned long FIXPHY0:1; + unsigned long :3; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long DVBINT1:1; + unsigned long :1; + unsigned long DOVRCRB1:1; + unsigned long DOVRCRA1:1; + unsigned long :2; + unsigned long DMINT1:1; + unsigned long DPINT1:1; + unsigned long DVBINT0:1; + unsigned long :1; + unsigned long DOVRCRB0:1; + unsigned long DOVRCRA0:1; + unsigned long :2; + unsigned long DMINT0:1; + unsigned long DPINT0:1; + unsigned long DVBSE1:1; + unsigned long :1; + unsigned long DOVRCRBE1:1; + unsigned long DOVRCRAE1:1; + unsigned long :2; + unsigned long DMINTE1:1; + unsigned long DPINTE1:1; + unsigned long DVBSE0:1; + unsigned long :1; + unsigned long DOVRCRBE0:1; + unsigned long DOVRCRAE0:1; + unsigned long :2; + unsigned long DMINTE0:1; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + unsigned char wk2[4]; + void *TDLAR; + unsigned char wk3[4]; + void *RDLAR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long RABT:1; + unsigned long RFCOF:1; + unsigned long ADE:1; + unsigned long ECI:1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :4; + unsigned long CND:1; + unsigned long DLC:1; + unsigned long CD:1; + unsigned long TRO:1; + unsigned long RMAF:1; + unsigned long :2; + unsigned long RRF:1; + unsigned long RTLF:1; + unsigned long RTSF:1; + unsigned long PRE:1; + unsigned long CERF:1; + } BIT; + } EESR; + unsigned char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long RABTIP:1; + unsigned long RFCOFIP:1; + unsigned long ADEIP:1; + unsigned long ECIIP:1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :4; + unsigned long CNDIP:1; + unsigned long DLCIP:1; + unsigned long CDIP:1; + unsigned long TROIP:1; + unsigned long RMAFIP:1; + unsigned long :2; + unsigned long RRFIP:1; + unsigned long RTLFIP:1; + unsigned long RTSFIP:1; + unsigned long PREIP:1; + unsigned long CERFIP:1; + } BIT; + } EESIPR; + unsigned char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long CNDCE:1; + unsigned long DLCCE:1; + unsigned long CDCE:1; + unsigned long TROCE:1; + unsigned long RMAFCE:1; + unsigned long :2; + unsigned long RRFCE:1; + unsigned long RTLFCE:1; + unsigned long RTSFCE:1; + unsigned long PRECE:1; + unsigned long CERFCE:1; + } BIT; + } TRSCER; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + unsigned char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + unsigned char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long RNC:1; + unsigned long RNR:1; + } BIT; + } RMCR; + unsigned char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TLB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + unsigned char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + unsigned char wk13[72]; + void *RBWAR; + void *RDFAR; + unsigned char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TPC:1; + unsigned long ZPE:1; + unsigned long PFR:1; + unsigned long RXF:1; + unsigned long TXF:1; + unsigned long :3; + unsigned long PRCEF:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long RE:1; + unsigned long TE:1; + unsigned long :1; + unsigned long ILB:1; + unsigned long RTM:1; + unsigned long DM:1; + unsigned long PRM:1; + } BIT; + } ECMR; + unsigned char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long RFL:12; + } BIT; + } RFLR; + unsigned char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFR:1; + unsigned long PSRTO:1; + unsigned long :1; + unsigned long LCHNG:1; + unsigned long MPD:1; + unsigned long ICD:1; + } BIT; + } ECSR; + unsigned char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFSIPR:1; + unsigned long PSRTOIP:1; + unsigned long :1; + unsigned long LCHNGIP:1; + unsigned long MPDIP:1; + unsigned long ICDIP:1; + } BIT; + } ECSIPR; + unsigned char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long MDI:1; + unsigned long MDO:1; + unsigned long MMD:1; + unsigned long MDC:1; + } BIT; + } PIR; + unsigned char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LMON:1; + } BIT; + } PSR; + unsigned char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long RMD:20; + } BIT; + } RDMLR; + unsigned char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long IPG:5; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long AP:16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MP:16; + } BIT; + } MPR; + unsigned char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPAUSE:8; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TPAUSE:16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TXP:8; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long BCF:16; + } BIT; + } BCFRR; + unsigned char wk8[80]; + unsigned long MAHR; + unsigned char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MA:16; + } BIT; + } MALR; + unsigned char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + unsigned char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_ETHER_EINT, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1, +IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0, +IR_RTC_PRD=62,IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_USB_USBR0=90,IR_USB_USBR1, +IR_RTC_ALM, +IR_WDT_WOVI=96, +IR_AD0_ADI0=98, +IR_AD1_ADI1, +IR_S12AD_ADI=102, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6, +IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7, +IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8, +IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9, +IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10, +IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11, +IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4, +IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMACA_DMAC0I=198,IR_DMACA_DMAC1I,IR_DMACA_DMAC2I,IR_DMACA_DMAC3I, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3, +IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0, +IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1 +}; + +enum enum_dtce { +DTCE_BSC_BUSERR=16, +DTCE_FCU_FIFERR=21,DTCE_FCU_FRDYI=23, +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_ETHER_EINT, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,DTCE_USB0_USBI0, +DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1,DTCE_USB1_USBI1, +DTCE_RSPI0_SPEI0=44,DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0,DTCE_RSPI0_SPII0, +DTCE_RSPI1_SPEI1,DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1,DTCE_RSPI1_SPII1, +DTCE_CAN0_ERS0=56,DTCE_CAN0_RXF0,DTCE_CAN0_TXF0,DTCE_CAN0_RXM0,DTCE_CAN0_TXM0, +DTCE_RTC_PRD=62,DTCE_RTC_CUP, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_USB_USBR0=90,DTCE_USB_USBR1, +DTCE_RTC_ALM, +DTCE_WDT_WOVI=96, +DTCE_AD0_ADI0=98, +DTCE_AD1_ADI1, +DTCE_S12AD_ADI=102, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,DTCE_MTU0_TCIV0,DTCE_MTU0_TGIE0,DTCE_MTU0_TGIF0, +DTCE_MTU1_TGIA1,DTCE_MTU1_TGIB1,DTCE_MTU1_TCIV1,DTCE_MTU1_TCIU1, +DTCE_MTU2_TGIA2,DTCE_MTU2_TGIB2,DTCE_MTU2_TCIV2,DTCE_MTU2_TCIU2, +DTCE_MTU3_TGIA3,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,DTCE_MTU3_TCIV3, +DTCE_MTU4_TGIA4,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6,DTCE_MTU6_TCIV6,DTCE_MTU6_TGIE6,DTCE_MTU6_TGIF6, +DTCE_MTU7_TGIA7,DTCE_MTU7_TGIB7,DTCE_MTU7_TCIV7,DTCE_MTU7_TCIU7, +DTCE_MTU8_TGIA8,DTCE_MTU8_TGIB8,DTCE_MTU8_TCIV8,DTCE_MTU8_TCIU8, +DTCE_MTU9_TGIA9,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9,DTCE_MTU9_TCIV9, +DTCE_MTU10_TGIA10,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10, +DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11, +DTCE_POE_OEI1,DTCE_POE_OEI2,DTCE_POE_OEI3,DTCE_POE_OEI4, +DTCE_TMR0_CMIA0,DTCE_TMR0_CMIB0,DTCE_TMR0_OVI0, +DTCE_TMR1_CMIA1,DTCE_TMR1_CMIB1,DTCE_TMR1_OVI1, +DTCE_TMR2_CMIA2,DTCE_TMR2_CMIB2,DTCE_TMR2_OVI2, +DTCE_TMR3_CMIA3,DTCE_TMR3_CMIB3,DTCE_TMR3_OVI3, +DTCE_DMACA_DMAC0I=198,DTCE_DMACA_DMAC1I,DTCE_DMACA_DMAC2I,DTCE_DMACA_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_SCI0_ERI0=214,DTCE_SCI0_RXI0,DTCE_SCI0_TXI0,DTCE_SCI0_TEI0, +DTCE_SCI1_ERI1,DTCE_SCI1_RXI1,DTCE_SCI1_TXI1,DTCE_SCI1_TEI1, +DTCE_SCI2_ERI2,DTCE_SCI2_RXI2,DTCE_SCI2_TXI2,DTCE_SCI2_TEI2, +DTCE_SCI3_ERI3,DTCE_SCI3_RXI3,DTCE_SCI3_TXI3,DTCE_SCI3_TEI3, +DTCE_SCI5_ERI5=234,DTCE_SCI5_RXI5,DTCE_SCI5_TXI5,DTCE_SCI5_TEI5, +DTCE_SCI6_ERI6,DTCE_SCI6_RXI6,DTCE_SCI6_TXI6,DTCE_SCI6_TEI6, +DTCE_RIIC0_ICEEI0=246,DTCE_RIIC0_ICRXI0,DTCE_RIIC0_ICTXI0,DTCE_RIIC0_ICTEI0, +DTCE_RIIC1_ICEEI1,DTCE_RIIC1_ICRXI1,DTCE_RIIC1_ICTXI1,DTCE_RIIC1_ICTEI1 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_ETHER_EINT=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06, +IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07, +IER_RTC_PRD=0x07,IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B, +IER_RTC_ALM=0x0B, +IER_WDT_WOVI=0x0C, +IER_AD0_ADI0=0x0C, +IER_AD1_ADI1=0x0C, +IER_S12AD_ADI=0x0C, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10, +IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12, +IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13, +IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13, +IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14, +IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14, +IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMACA_DMAC0I=0x18,IER_DMACA_DMAC1I=0x18,IER_DMACA_DMAC2I=0x19,IER_DMACA_DMAC3I=0x19, +IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C, +IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C, +IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D, +IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E, +IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F, +IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0x00, +IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02, +IPR_ICU_SWINT=0x03, +IPR_CMT0_CMI0=0x04, +IPR_CMT1_CMI1=0x05, +IPR_CMT2_CMI2=0x06, +IPR_CMT3_CMI3=0x07, +IPR_ETHER_EINT=0x08, +IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E, +IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12, +IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14, +IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15, +IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18, +IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F, +IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F, +IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B, +IPR_RTC_ALM=0x3C, +IPR_WDT_WOVI=0x40, +IPR_AD0_ADI0=0x44, +IPR_AD1_ADI1=0x45, +IPR_S12AD_ADI=0x48, +IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52, +IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54, +IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56, +IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58, +IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A, +IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B, +IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D, +IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F, +IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61, +IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63, +IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65, +IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66, +IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67, +IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68, +IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69, +IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A, +IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B, +IPR_DMACA_DMAC0I=0x70,IPR_DMACA_DMAC1I=0x71,IPR_DMACA_DMAC2I=0x72,IPR_DMACA_DMAC3I=0x73, +IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75, +IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80, +IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81, +IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82, +IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83, +IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85, +IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86, +IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B, +IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F, +IPR_BSC_=0x00, +IPR_CMT0_=0x04, +IPR_CMT1_=0x05, +IPR_CMT2_=0x06, +IPR_CMT3_=0x07, +IPR_ETHER_=0x08, +IPR_RSPI0_=0x14, +IPR_RSPI1_=0x15, +IPR_CAN0_=0x18, +IPR_WDT_=0x40, +IPR_AD0_=0x44, +IPR_AD1_=0x45, +IPR_S12AD_=0x48, +IPR_MTU1_TGI=0x53, +IPR_MTU1_TCI=0x54, +IPR_MTU2_TGI=0x55, +IPR_MTU2_TCI=0x56, +IPR_MTU3_TGI=0x57, +IPR_MTU4_TGI=0x59, +IPR_MTU5_=0x5B, +IPR_MTU5_TGI=0x5B, +IPR_MTU7_TGI=0x5E, +IPR_MTU7_TCI=0x5F, +IPR_MTU8_TGI=0x60, +IPR_MTU8_TCI=0x61, +IPR_MTU9_TGI=0x62, +IPR_MTU10_TGI=0x64, +IPR_MTU11_=0x66, +IPR_MTU11_TGI=0x66, +IPR_POE_=0x67, +IPR_POE_OEI=0x67, +IPR_TMR0_=0x68, +IPR_TMR1_=0x69, +IPR_TMR2_=0x6A, +IPR_TMR3_=0x6B, +IPR_SCI0_=0x80, +IPR_SCI1_=0x81, +IPR_SCI2_=0x82, +IPR_SCI3_=0x83, +IPR_SCI5_=0x85, +IPR_SCI6_=0x86 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_ETHER_EINT IEN0 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_USB1_D0FIFO1 IEN0 +#define IEN_USB1_D1FIFO1 IEN1 +#define IEN_USB1_USBI1 IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSPI1_SPEI1 IEN0 +#define IEN_RSPI1_SPRI1 IEN1 +#define IEN_RSPI1_SPTI1 IEN2 +#define IEN_RSPI1_SPII1 IEN3 +#define IEN_CAN0_ERS0 IEN0 +#define IEN_CAN0_RXF0 IEN1 +#define IEN_CAN0_TXF0 IEN2 +#define IEN_CAN0_RXM0 IEN3 +#define IEN_CAN0_TXM0 IEN4 +#define IEN_RTC_PRD IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_USB_USBR0 IEN2 +#define IEN_USB_USBR1 IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_WDT_WOVI IEN0 +#define IEN_AD0_ADI0 IEN2 +#define IEN_AD1_ADI1 IEN3 +#define IEN_S12AD_ADI IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN7 +#define IEN_MTU6_TGIA6 IEN6 +#define IEN_MTU6_TGIB6 IEN7 +#define IEN_MTU6_TGIC6 IEN0 +#define IEN_MTU6_TGID6 IEN1 +#define IEN_MTU6_TCIV6 IEN2 +#define IEN_MTU6_TGIE6 IEN3 +#define IEN_MTU6_TGIF6 IEN4 +#define IEN_MTU7_TGIA7 IEN5 +#define IEN_MTU7_TGIB7 IEN6 +#define IEN_MTU7_TCIV7 IEN7 +#define IEN_MTU7_TCIU7 IEN0 +#define IEN_MTU8_TGIA8 IEN1 +#define IEN_MTU8_TGIB8 IEN2 +#define IEN_MTU8_TCIV8 IEN3 +#define IEN_MTU8_TCIU8 IEN4 +#define IEN_MTU9_TGIA9 IEN5 +#define IEN_MTU9_TGIB9 IEN6 +#define IEN_MTU9_TGIC9 IEN7 +#define IEN_MTU9_TGID9 IEN0 +#define IEN_MTU9_TCIV9 IEN1 +#define IEN_MTU10_TGIA10 IEN2 +#define IEN_MTU10_TGIB10 IEN3 +#define IEN_MTU10_TGIC10 IEN4 +#define IEN_MTU10_TGID10 IEN5 +#define IEN_MTU10_TCIV10 IEN6 +#define IEN_MTU11_TGIU11 IEN7 +#define IEN_MTU11_TGIV11 IEN0 +#define IEN_MTU11_TGIW11 IEN1 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_POE_OEI3 IEN4 +#define IEN_POE_OEI4 IEN5 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMACA_DMAC0I IEN6 +#define IEN_DMACA_DMAC1I IEN7 +#define IEN_DMACA_DMAC2I IEN0 +#define IEN_DMACA_DMAC3I IEN1 +#define IEN_EXDMAC_EXDMAC0I IEN2 +#define IEN_EXDMAC_EXDMAC1I IEN3 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI2_ERI2 IEN6 +#define IEN_SCI2_RXI2 IEN7 +#define IEN_SCI2_TXI2 IEN0 +#define IEN_SCI2_TEI2 IEN1 +#define IEN_SCI3_ERI3 IEN2 +#define IEN_SCI3_RXI3 IEN3 +#define IEN_SCI3_TXI3 IEN4 +#define IEN_SCI3_TEI3 IEN5 +#define IEN_SCI5_ERI5 IEN2 +#define IEN_SCI5_RXI5 IEN3 +#define IEN_SCI5_TXI5 IEN4 +#define IEN_SCI5_TEI5 IEN5 +#define IEN_SCI6_ERI6 IEN6 +#define IEN_SCI6_RXI6 IEN7 +#define IEN_SCI6_TXI6 IEN0 +#define IEN_SCI6_TEI6 IEN1 +#define IEN_RIIC0_ICEEI0 IEN6 +#define IEN_RIIC0_ICRXI0 IEN7 +#define IEN_RIIC0_ICTXI0 IEN0 +#define IEN_RIIC0_ICTEI0 IEN1 +#define IEN_RIIC1_ICEEI1 IEN2 +#define IEN_RIIC1_ICRXI1 IEN3 +#define IEN_RIIC1_ICTXI1 IEN4 +#define IEN_RIIC1_ICTEI1 IEN5 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_ETHER_EINT 32 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_USB1_D0FIFO1 40 +#define VECT_USB1_D1FIFO1 41 +#define VECT_USB1_USBI1 42 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSPI1_SPEI1 48 +#define VECT_RSPI1_SPRI1 49 +#define VECT_RSPI1_SPTI1 50 +#define VECT_RSPI1_SPII1 51 +#define VECT_CAN0_ERS0 56 +#define VECT_CAN0_RXF0 57 +#define VECT_CAN0_TXF0 58 +#define VECT_CAN0_RXM0 59 +#define VECT_CAN0_TXM0 60 +#define VECT_RTC_PRD 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_USB_USBR0 90 +#define VECT_USB_USBR1 91 +#define VECT_RTC_ALM 92 +#define VECT_WDT_WOVI 96 +#define VECT_AD0_ADI0 98 +#define VECT_AD1_ADI1 99 +#define VECT_S12AD_ADI 102 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_MTU6_TGIA6 142 +#define VECT_MTU6_TGIB6 143 +#define VECT_MTU6_TGIC6 144 +#define VECT_MTU6_TGID6 145 +#define VECT_MTU6_TCIV6 146 +#define VECT_MTU6_TGIE6 147 +#define VECT_MTU6_TGIF6 148 +#define VECT_MTU7_TGIA7 149 +#define VECT_MTU7_TGIB7 150 +#define VECT_MTU7_TCIV7 151 +#define VECT_MTU7_TCIU7 152 +#define VECT_MTU8_TGIA8 153 +#define VECT_MTU8_TGIB8 154 +#define VECT_MTU8_TCIV8 155 +#define VECT_MTU8_TCIU8 156 +#define VECT_MTU9_TGIA9 157 +#define VECT_MTU9_TGIB9 158 +#define VECT_MTU9_TGIC9 159 +#define VECT_MTU9_TGID9 160 +#define VECT_MTU9_TCIV9 161 +#define VECT_MTU10_TGIA10 162 +#define VECT_MTU10_TGIB10 163 +#define VECT_MTU10_TGIC10 164 +#define VECT_MTU10_TGID10 165 +#define VECT_MTU10_TCIV10 166 +#define VECT_MTU11_TGIU11 167 +#define VECT_MTU11_TGIV11 168 +#define VECT_MTU11_TGIW11 169 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_POE_OEI3 172 +#define VECT_POE_OEI4 173 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMACA_DMAC0I 198 +#define VECT_DMACA_DMAC1I 199 +#define VECT_DMACA_DMAC2I 200 +#define VECT_DMACA_DMAC3I 201 +#define VECT_EXDMAC_EXDMAC0I 202 +#define VECT_EXDMAC_EXDMAC1I 203 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI2_ERI2 222 +#define VECT_SCI2_RXI2 223 +#define VECT_SCI2_TXI2 224 +#define VECT_SCI2_TEI2 225 +#define VECT_SCI3_ERI3 226 +#define VECT_SCI3_RXI3 227 +#define VECT_SCI3_TXI3 228 +#define VECT_SCI3_TEI3 229 +#define VECT_SCI5_ERI5 234 +#define VECT_SCI5_RXI5 235 +#define VECT_SCI5_TXI5 236 +#define VECT_SCI5_TEI5 237 +#define VECT_SCI6_ERI6 238 +#define VECT_SCI6_RXI6 239 +#define VECT_SCI6_TXI6 240 +#define VECT_SCI6_TEI6 241 +#define VECT_RIIC0_ICEEI0 246 +#define VECT_RIIC0_ICRXI0 247 +#define VECT_RIIC0_ICTXI0 248 +#define VECT_RIIC0_ICTEI0 249 +#define VECT_RIIC1_ICEEI1 250 +#define VECT_RIIC1_ICRXI1 251 +#define VECT_RIIC1_ICTXI1 252 +#define VECT_RIIC1_ICTEI1 253 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMACA SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_AD0 SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_AD1 SYSTEM.MSTPCRA.BIT.MSTPA22 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTUA SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTUB SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU10 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU11 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_USB1 SYSTEM.MSTPCRB.BIT.MSTPB18 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC1 +#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define EXDMAC0 (*(volatile struct st_exdmac0 __evenaccess *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac0 __evenaccess *)0x82840) +#define EXDMAC (*(volatile struct st_exdmac __evenaccess *)0x82A00) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define WDT (*(volatile union un_wdt __evenaccess *)0x88028) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define AD0 (*(volatile struct st_ad __evenaccess *)0x88040) +#define AD1 (*(volatile struct st_ad __evenaccess *)0x88060) +#define DA (*(volatile struct st_da __evenaccess *)0x880C0) +#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define SCI0 (*(volatile struct st_sci __evenaccess *)0x88240) +#define SCI1 (*(volatile struct st_sci __evenaccess *)0x88248) +#define SCI2 (*(volatile struct st_sci __evenaccess *)0x88250) +#define SCI3 (*(volatile struct st_sci __evenaccess *)0x88258) +#define SCI5 (*(volatile struct st_sci __evenaccess *)0x88268) +#define SCI6 (*(volatile struct st_sci __evenaccess *)0x88270) +#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x88240) +#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x88248) +#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x88250) +#define SMCI3 (*(volatile struct st_smci __evenaccess *)0x88258) +#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x88268) +#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x88270) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RIIC1 (*(volatile struct st_riic __evenaccess *)0x88320) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380) +#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0x883A0) +#define MTUA (*(volatile struct st_mtu __evenaccess *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88700) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88780) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88800) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88880) +#define POE (*(volatile struct st_poe __evenaccess *)0x88900) +#define MTUB (*(volatile struct st_mtu __evenaccess *)0x88A0A) +#define MTU6 (*(volatile struct st_mtu0 __evenaccess *)0x88B00) +#define MTU7 (*(volatile struct st_mtu1 __evenaccess *)0x88B80) +#define MTU8 (*(volatile struct st_mtu2 __evenaccess *)0x88C00) +#define MTU9 (*(volatile struct st_mtu3 __evenaccess *)0x88A00) +#define MTU10 (*(volatile struct st_mtu4 __evenaccess *)0x88A00) +#define MTU11 (*(volatile struct st_mtu5 __evenaccess *)0x88C80) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006) +#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007) +#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008) +#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F) +#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010) +#define IOPORT (*(volatile struct st_ioport __evenaccess *)0x8C100) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x8C288) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define USB1 (*(volatile struct st_usb0 __evenaccess *)0xA0200) +#define USB (*(volatile struct st_usb __evenaccess *)0xA0400) +#define EDMAC (*(volatile struct st_edmac __evenaccess *)0xC0000) +#define ETHERC (*(volatile struct st_etherc __evenaccess *)0xC0100) +#pragma bit_order +#pragma packoption +#endif \ No newline at end of file diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/lowsrc.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/lowsrc.h new file mode 100644 index 000000000..4d2aabfc7 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/lowsrc.h @@ -0,0 +1,13 @@ +/***********************************************************************/ +/* */ +/* FILE :lowsrc.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Header file of I/O Stream file */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ +/*Number of I/O Stream*/ +#define IOSTREAM 20 diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/stacksct.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/stacksct.h new file mode 100644 index 000000000..1d5db830d --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/stacksct.h @@ -0,0 +1,13 @@ +/***********************************************************************/ +/* */ +/* FILE :stacksct.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Setting of Stack area */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ +#pragma stacksize su=0x300 +#pragma stacksize si=0x100 diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/typedefine.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/typedefine.h new file mode 100644 index 000000000..d3ad67fec --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/typedefine.h @@ -0,0 +1,41 @@ +/***********************************************************************/ +/* */ +/* FILE :typedefine.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Aliases of Integer Type */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX +* +* File Name : typedefine.h +* +* Abstract : Aliases of Integer Type. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/vect.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/vect.h new file mode 100644 index 000000000..a6a48946b --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/vect.h @@ -0,0 +1,60 @@ +/***********************************************************************/ +/* */ +/* FILE :vect.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Definition of Vector */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : vect.h +* +* Abstract : Definition of Vector. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +// Exception(Supervisor Instruction) +#pragma interrupt (Excep_SuperVisorInst) +void Excep_SuperVisorInst(void); + +// Exception(Undefined Instruction) +#pragma interrupt (Excep_UndefinedInst) +void Excep_UndefinedInst(void); + +// Exception(Floating Point) +#pragma interrupt (Excep_FloatingPoint) +void Excep_FloatingPoint(void); + +// NMI +#pragma interrupt (NonMaskableInterrupt) +void NonMaskableInterrupt(void); + +// Dummy +#pragma interrupt (Dummy) +void Dummy(void); + +// BRK +#pragma interrupt (Excep_BRK(vect=0)) +void Excep_BRK(void); + +//;<> +//;Power On Reset PC +extern void PowerON_Reset_PC(void); +//;<> + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/yrdkrx62ndef.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/yrdkrx62ndef.h new file mode 100644 index 000000000..f9109943a --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/include/yrdkrx62ndef.h @@ -0,0 +1,89 @@ + +/****************************************************************************** +* DISCLAIMER +* Please refer to http://www.renesas.com/disclaimer +****************************************************************************** + Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : rsksh7216.h +* Version : 1.00 +* Description : RSK 7216 board specific settings +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.10.2009 1.00 First Release +******************************************************************************/ + +#ifndef RSKRX62N_H +#define RSKRX62N_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/* System Clock Settings */ +#define XTAL_FREQUENCY (12000000L) +#define ICLK_MUL (8) +#define PCLK_MUL (4) +#define BCLK_MUL (4) +#define ICLK_FREQUENCY (XTAL_FREQUENCY * ICLK_MUL) +#define PCLK_FREQUENCY (XTAL_FREQUENCY * PCLK_MUL) +#define BCLK_FREQUENCY (XTAL_FREQUENCY * BCLK_MUL) + +#define CMT0_CLK_SELECT (512) + +/* General Values */ +#define LED_ON (1) +#define LED_OFF (0) + +/* LEDs */ +/* Define LEDs to Port Numbers */ +#define LED0 PORTD.DR.BIT.B0 +#define LED1 PORTD.DR.BIT.B1 +#define LED2 PORTD.DR.BIT.B2 +#define LED3 PORTD.DR.BIT.B3 +#define LED4 PORTD.DR.BIT.B4 +#define LED5 PORTD.DR.BIT.B5 +#define LED6 PORTD.DR.BIT.B6 +#define LED7 PORTD.DR.BIT.B7 +#define LED8 PORTE.DR.BIT.B0 +#define LED9 PORTE.DR.BIT.B1 +#define LED10 PORTE.DR.BIT.B2 +#define LED11 PORTE.DR.BIT.B3 + +#define LED0_DDR PORTD.DDR.BIT.B0 +#define LED1_DDR PORTD.DDR.BIT.B1 +#define LED2_DDR PORTD.DDR.BIT.B2 +#define LED3_DDR PORTD.DDR.BIT.B3 +#define LED4_DDR PORTD.DDR.BIT.B4 +#define LED5_DDR PORTD.DDR.BIT.B5 +#define LED6_DDR PORTD.DDR.BIT.B6 +#define LED7_DDR PORTD.DDR.BIT.B7 +#define LED8_DDR PORTE.DDR.BIT.B0 +#define LED9_DDR PORTE.DDR.BIT.B1 +#define LED10_DDR PORTE.DDR.BIT.B2 +#define LED11_DDR PORTE.DDR.BIT.B3 + + + + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + + + +/* RSKRX62N_H */ +#endif + diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-blinky.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-blinky.c new file mode 100644 index 000000000..8fea457d2 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-blinky.c @@ -0,0 +1,217 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This is a very simple demo that creates two tasks and one queue. One task + * (the queue receive task) blocks on the queue to wait for data to arrive, + * toggling an LED each time '100' is received. The other task (the queue send + * task) repeatedly blocks for a fixed period before sending '100' to the queue + * (causing the first task to toggle the LED). + * + * For a much more complete and complex example select either the Debug or + * Debug_with_optimisation build configurations within the HEW IDE. +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Priorities at which the tasks are created. */ +#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which data is sent to the queue, specified in milliseconds. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 500 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added so the send task should always find the +queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* + * The tasks as defined at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + } + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +portTickType xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block state is specified in ticks, the constant used converts ticks + to ms. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to flash its LED. 0 + is used so the send does not block - it shouldn't need to as the queue + should always be empty here. */ + xQueueSend( xQueue, &ulValueToSend, 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + for( ;; ) + { + /* Wait until something arives in the queue - this will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have arrived, but is it the expected + value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( 0 ); + } + } +} +/*-----------------------------------------------------------*/ + +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ +} +/*-----------------------------------------------------------*/ diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-full.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-full.c new file mode 100644 index 000000000..7e0f49c70 --- /dev/null +++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/main-full.c @@ -0,0 +1,641 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This project includes a lot of tasks and tests and is therefore complex. + * If you would prefer a much simpler project to get started with then select + * the 'Blinky' build configuration within the HEW IDE. + * + * Creates all the demo application tasks, then starts the scheduler. The web + * documentation provides more details of the standard demo application tasks, + * which provide no particular functionality but do provide a good example of + * how to use the FreeRTOS API. The tasks defined in flop.c are included in the + * set of standard demo tasks to ensure the floating point unit gets some + * exercise. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill the registers with known values, then check + * that each register still contains its expected value. Each task uses + * different values. The tasks run with very low priority so get preempted + * very frequently. A check variable is incremented on each iteration of the + * test loop. A register containing an unexpected value is indicative of an + * error in the context switching mechanism and will result in a branch to a + * null loop - which in turn will prevent the check variable from incrementing + * any further and allow the check task (described below) to determine that an + * error has occurred. The nature of the reg test tasks necessitates that they + * are written in assembly code. + * + * "Check" task - This only executes every five seconds but has a high priority + * to ensure it gets processor time. Its main function is to check that all the + * standard demo tasks are still operational. While no errors have been + * discovered the check task will toggle LED 5 every 5 seconds - the toggle + * rate increasing to 200ms being a visual indication that at least one task has + * reported unexpected behaviour. + * + * "High frequency timer test" - A high frequency periodic interrupt is + * generated using a timer - the interrupt is assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY so should not be effected by anything + * the kernel is doing. The interrupt service routine measures the number of + * counts a separate timer performs between each interrupt to determine the + * jitter in the interrupt timing. + * + * *NOTE 1* If LED5 is toggling every 5 seconds then all the demo application + * tasks are executing as expected and no errors have been reported in any + * tasks. The toggle rate increasing to 200ms indicates that at least one task + * has reported unexpected behaviour. + * + * *NOTE 2* vApplicationSetupTimerInterrupt() is called by the kernel to let + * the application set up a timer to generate the tick interrupt. In this + * example a compare match timer is used for this purpose. + * + * *NOTE 3* The CPU must be in Supervisor mode when the scheduler is started. + * The PowerON_Reset_PC() supplied in resetprg.c with this demo has + * Change_PSW_PM_to_UserMode() commented out to ensure this is the case. + * + * *NOTE 4* The IntQueue common demo tasks test interrupt nesting and make use + * of all the 8bit timers (as two cascaded 16bit units). +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "flash.h" +#include "IntQueue.h" +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "semtest.h" +#include "PollQ.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "flop.h" + +/* Values that are passed into the reg test tasks using the task parameter. The +tasks check that the values are passed in correctly. */ +#define mainREG_TEST_1_PARAMETER ( 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( 0x12345678UL ) + +/* Priorities at which the tasks are created. */ +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainuIP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The LED toggled by the check task. */ +#define mainCHECK_LED ( 5 ) + +/* The rate at which mainCHECK_LED will toggle when all the tasks are running +without error. Controlled by the check task as described at the top of this +file. */ +#define mainNO_ERROR_CYCLE_TIME ( 5000 / portTICK_RATE_MS ) + +/* The rate at which mainCHECK_LED will toggle when an error has been reported +by at least one task. Controlled by the check task as described at the top of +this file. */ +#define mainERROR_CYCLE_TIME ( 200 / portTICK_RATE_MS ) + +/* The period of the peripheral clock in nano seconds. This is used to calculate +the jitter time in nano seconds as part of the high frequency timer test. The +clock driving the timer is divided by 8. */ +#define mainNS_PER_CLOCK ( ( unsigned long ) ( ( 1.0 / ( ( double ) configPERIPHERAL_CLOCK_HZ ) / 8.0 ) * 1000000000.0 ) ) + +/* + * vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will execute if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue or + * semaphore is created. It is also called by various parts of the demo + * application. + */ +void vApplicationMallocFailedHook( void ); + +/* + * vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set to 1 + * in FreeRTOSConfig.h. It is a hook function that is called on each iteration + * of the idle task. It is essential that code added to this hook function + * never attempts to block in any way (for example, call xQueueReceive() with + * a block time specified). If the application makes use of the vTaskDelete() + * API function (as this demo application does) then it is also important that + * vApplicationIdleHook() is permitted to return to its calling function because + * it is the responsibility of the idle task to clean up memory allocated by the + * kernel to any task that has since been deleted. + */ +void vApplicationIdleHook( void ); + +/* + * vApplicationStackOverflowHook() will only be called if + * configCHECK_FOR_STACK_OVERFLOW is set to a non-zero value. The handle and + * name of the offending task should be passed in the function parameters, but + * it is possible that the stack overflow will have corrupted these - in which + * case pxCurrentTCB can be inspected to find the same information. + */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); + +/* + * The reg test tasks as described at the top of this file. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); + +/* + * The actual implementation of the reg test functionality, which, because of + * the direct register access, have to be in assembly. + */ +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * The check task as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* Variables that are incremented on each iteration of the reg test tasks - +provided the tasks have not reported any errors. The check task inspects these +variables to ensure they are still incrementing as expected. If a variable +stops incrementing then it is likely that its associate task has stalled. */ +unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL; + +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Start the reg test tasks which test the context switching mechanism. */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Start the check task as described at the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartInterruptQueueTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL; +portTickType xNextWakeTime, xCycleFrequency = mainNO_ERROR_CYCLE_TIME; +extern void vSetupHighFrequencyTimer( void ); +extern volatile unsigned short usMaxJitter; +volatile unsigned long ulActualJitter = 0; +static char cErrorText[ 100 ]; + + /* If this is being executed then the kernel has been started. Start the high + frequency timer test as described at the top of this file. This is only + included in the optimised build configuration - otherwise it takes up too much + CPU time. */ + #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST + vSetupHighFrequencyTimer(); + #endif + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); + + /* Check the standard demo tasks are running without error. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + /* Increase the rate at which this task cycles, which will increase the + rate at which mainCHECK_LED flashes to give visual feedback that an error + has occurred. */ + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: GenQueue" ); + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: QueuePeek" ); + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: BlockQueue" ); + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: BlockTime" ); + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: SemTest" ); + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: PollQueue" ); + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: Death" ); + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: IntMath" ); + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: RecMutex" ); + } + else if( xAreIntQueueTasksStillRunning() != pdPASS ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: IntQueue" ); + } + else if( xAreMathsTaskStillRunning() != pdPASS ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: Flop" ); + } + + /* Check the reg test tasks are still cycling. They will stop incrementing + their loop counters if they encounter an error. */ + if( ulRegTest1CycleCount == ulLastRegTest1CycleCount ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: RegTest1" ); + } + + if( ulRegTest2CycleCount == ulLastRegTest2CycleCount ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + strcpy( cErrorText, "Error: RegTest2" ); + } + + ulLastRegTest1CycleCount = ulRegTest1CycleCount; + ulLastRegTest2CycleCount = ulRegTest2CycleCount; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every 5 seconds then everything is ok. A faster toggle + indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Calculate the maximum jitter experienced by the high frequency timer + test and print it out. It is ok to use printf without worrying about + mutual exclusion as it is not used anywhere else in this demo. */ + //sprintf( cTempBuf, "%s [%fns]\n", "Max Jitter = ", ( ( float ) usMaxJitter ) * mainNS_PER_CLOCK ); + ulActualJitter = ( ( unsigned long ) usMaxJitter ) * mainNS_PER_CLOCK; + } +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} + + + + + -- 2.39.5