From dbe7bb0d21f632b9dbe7527aa758b347de7427d7 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 12 Jan 2015 22:47:25 +0100 Subject: [PATCH] ppc4xx: remove PCI405 board Signed-off-by: Matthias Fuchs --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/pci405/Kconfig | 12 - board/esd/pci405/MAINTAINERS | 6 - board/esd/pci405/Makefile | 9 - board/esd/pci405/cmd_pci405.c | 97 -- board/esd/pci405/flash.c | 85 -- board/esd/pci405/fpgadata.c | 1492 ------------------------------- board/esd/pci405/pci405.c | 366 -------- board/esd/pci405/pci405.h | 16 - board/esd/pci405/writeibm.S | 205 ----- configs/PCI405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/PCI405.h | 294 ------ 13 files changed, 1 insertion(+), 2589 deletions(-) delete mode 100644 board/esd/pci405/Kconfig delete mode 100644 board/esd/pci405/MAINTAINERS delete mode 100644 board/esd/pci405/Makefile delete mode 100644 board/esd/pci405/cmd_pci405.c delete mode 100644 board/esd/pci405/flash.c delete mode 100644 board/esd/pci405/fpgadata.c delete mode 100644 board/esd/pci405/pci405.c delete mode 100644 board/esd/pci405/pci405.h delete mode 100644 board/esd/pci405/writeibm.S delete mode 100644 configs/PCI405_defconfig delete mode 100644 include/configs/PCI405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index ea4227e58f..0e8cbf3bc4 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_PCI405 - bool "Support PCI405" - config TARGET_PLU405 bool "Support PLU405" @@ -226,7 +223,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/pci405/Kconfig" source "board/esd/plu405/Kconfig" source "board/esd/pmc405/Kconfig" source "board/esd/pmc405de/Kconfig" diff --git a/board/esd/pci405/Kconfig b/board/esd/pci405/Kconfig deleted file mode 100644 index 0a6524d073..0000000000 --- a/board/esd/pci405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PCI405 - -config SYS_BOARD - default "pci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PCI405" - -endif diff --git a/board/esd/pci405/MAINTAINERS b/board/esd/pci405/MAINTAINERS deleted file mode 100644 index cf9c1c9496..0000000000 --- a/board/esd/pci405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PCI405 BOARD -M: Matthias Fuchs -S: Maintained -F: board/esd/pci405/ -F: include/configs/PCI405.h -F: configs/PCI405_defconfig diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile deleted file mode 100644 index 9e659c796c..0000000000 --- a/board/esd/pci405/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o -obj-y += writeibm.o diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c deleted file mode 100644 index 29c688a787..0000000000 --- a/board/esd/pci405/cmd_pci405.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pci405.h" - -#if defined(CONFIG_CMD_BSP) - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int *ptr; - int count = 0; - int count2 = 0; - int i; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - /* cppcheck-suppress nullPointer */ - *ptr = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - /* cppcheck-suppress nullPointer */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - if (*ptr == PCI_RECONFIG_MAGIC) { - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - } else { - sprintf(addr, "%08x", *ptr); - - /* - * Boot image via bootm - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - do_bootm (cmdtp, 0, 1, local_args); - } - - return 0; -} -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "Wait for pci-image and boot it", - "" -); -#endif diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c deleted file mode 100644 index 113111d3a6..0000000000 --- a/board/esd/pci405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include -#include -#include - -#include "pci405.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Prototypes */ -unsigned long fpga_done_state(void); -unsigned long fpga_init_state(void); - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here */ -#define FPGA_DONE_STATE (fpga_done_state()) -#define FPGA_INIT_STATE (fpga_init_state()) - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE) -#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12) - -#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT) -#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12) - - -int board_revision(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Get version of PCI405 board from GPIO's - */ - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x00100200: - /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ - return 1; - case 0x00000200: - /* CS2==0 && IRQ5==1 -> version 1.2 */ - return 2; - case 0x00000000: - /* CS2==0 && IRQ5==0 -> version 1.3 */ - return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && IRQ5==0 -> version 1.4 */ - return 4; -#endif - default: - /* should not be reached! */ - return 0; - } -} - - -unsigned long fpga_done_state(void) -{ - if (gd->board_type < 2) { - return FPGA_DONE_STATE_V11; - } else { - return FPGA_DONE_STATE_V12; - } -} - - -unsigned long fpga_init_state(void) -{ - if (gd->board_type < 2) { - return FPGA_INIT_STATE_V11; - } else { - return FPGA_INIT_STATE_V12; - } -} - - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) - */ - out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out_be32((void*)GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * Setup GPIO pins (IRQ4/GPIO21 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned int *ptr; - unsigned int *magic; - - /* - * On PCI-405 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Check if magic for pci reconfig is written - */ - magic = (unsigned int *)0x00000004; - if (*magic == PCI_RECONFIG_MAGIC) { - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - *magic = 0; /* clear pci reconfig magic again */ - } - - /* - * Decrease PLB latency timeout and reduce priority of the PCI bridge master - */ -#define PCI0_BRDGOPT1 0x4a - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); - - /* - * Enable fairness and high bus utilization - */ - mtdcr(PLB0_ACR, 0x98000000); - - free(dst); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PCI405"); - } else { - puts (str); - } - - gd->board_type = board_revision(); - printf(" (Rev 1.%ld", gd->board_type); - - if (gd->board_type >= 2) { - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Setup GPIO pins (Trace/GPIO1 to GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */ - if (value) { - puts(", 33 MHz PCI"); - } else { - puts(", 66 MHz PCI"); - } - } - - puts(")\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#define UART1_MCR 0xef600404 -int wpeeprom(int wp) -{ - int wp_state = wp; - - if (wp == 1) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02); - } else if (wp == 0) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02); - } else { - if (in_8((void *)UART1_MCR) & 0x02) { - wp_state = 0; - } else { - wp_state = 1; - } - } - return wp_state; -} - -int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int wp = -1; - if (argc >= 2) { - if (argv[1][0] == '1') { - wp = 1; - } else if (argv[1][0] == '0') { - wp = 0; - } - } - - wp = wpeeprom(wp); - printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); - return 0; -} - -U_BOOT_CMD( - wpeeprom, 2, 1, do_wpeeprom, - "Check/Enable/Disable I2C EEPROM write protection", - "wpeeprom\n" - " - check I2C EEPROM write protection state\n" - "wpeeprom 1\n" - " - enable I2C EEPROM write protection\n" - "wpeeprom 0\n" - " - disable I2C EEPROM write protection" -); diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h deleted file mode 100644 index a62c9c2b0f..0000000000 --- a/board/esd/pci405/pci405.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PCI405_H_ -#define _PCI405_H_ - -#define PCI_REGS_LEN 0x100 -#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) - -#define PCI_RECONFIG_MAGIC 0x07081967 - -#endif /* _PCI405_H_ */ diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S deleted file mode 100644 index 03eaf97b78..0000000000 --- a/board/esd/pci405/writeibm.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include - -#include -#include - -#include -#include - - - .globl write_without_sync -write_without_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start1: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - - b start1 - - blr /* never reached !!!! */ - - .globl write_with_sync -write_with_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start2 - - blr /* never reached !!!! */ - - .globl write_with_less_sync -write_with_less_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2b: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 -/* sync */ - - b start2b - - blr /* never reached !!!! */ - - .globl write_with_more_sync -write_with_more_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start3: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - sync - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - sync - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id (PCIC0_SBSYSVID)*/ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start3 - - blr /* never reached !!!! */ diff --git a/configs/PCI405_defconfig b/configs/PCI405_defconfig deleted file mode 100644 index 48f19fe7ba..0000000000 --- a/configs/PCI405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_PCI405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0b449d1875..a41d9424b7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +PCI405 ppc4xx 405gp - - Matthias Fuchs OCRTC ppc4xx 405gpr - - Matthias Fuchs HUB405 ppc4xx 405ep - - Matthias Fuchs HH405 ppc4xx 405ep - - Matthias Fuchs diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h deleted file mode 100644 index 0989407fc7..0000000000 --- a/include/configs/PCI405.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * (C) Copyright 2001-2004 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PCI405 1 /* ...on a PCI405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mem_linux=14336k\0" \ - "optargs=panic=0\0" \ - "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ - -#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -/*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ -#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ -- 2.39.5