From de2dc5b5b0e4d2bae8b9a7dca98a0e65c7f3a0d1 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Mon, 30 May 2011 15:56:32 +0000 Subject: [PATCH] Start MicroBlaze project for the Spartan-6. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1427 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.bsb | 1 + Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.make | 216 + Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.mhs | 326 ++ Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp | 30 + .../RTOSDemo_incl.make | 111 + .../__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl | 180 + .../__xps/.dswkshop/MdtSvgDiag_Colors.xsl | 150 + .../__xps/.dswkshop/MdtSvgDiag_Globals.xsl | 168 + .../__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl | 584 ++ .../MdtTinySvgBLKD_BusLaneSpaces.xsl | 2758 ++++++++++ .../__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl | 546 ++ .../.dswkshop/MdtTinySvgBLKD_Functions.xsl | 1112 ++++ .../.dswkshop/MdtTinySvgBLKD_Globals.xsl | 115 + .../.dswkshop/MdtTinySvgBLKD_IOPorts.xsl | 495 ++ .../__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl | 1566 ++++++ .../.dswkshop/MdtTinySvgBLKD_Peripherals.xsl | 1582 ++++++ .../.dswkshop/MdtTinySvgBLKD_Processors.xsl | 465 ++ .../.dswkshop/MdtTinySvgDiag_BifShapes.xsl | 271 + .../__xps/bitinit.opt | 1 + .../__xps/edw2xtl_sav_globals.xsl | 263 + .../__xps/edw2xtl_sav_view.xsl | 245 + .../__xps/edw2xtl_sav_view_addr.xsl | 894 ++++ .../__xps/edw2xtl_sav_view_busif.xsl | 631 +++ .../__xps/edw2xtl_sav_view_groups.xsl | 1447 +++++ .../__xps/edw2xtl_sav_view_port.xsl | 771 +++ .../__xps/gensav_cmd.xml | 2 + .../__xps/ise/RTOSDemo.xreport | 218 + .../__xps/ise/xmsgprops.lst | 3 + .../__xps/platgen.opt | 2 + .../__xps/simgen.opt | 1 + .../__xps/system.xml | 4732 +++++++++++++++++ .../__xps/xplorer.opt | 1 + .../__xps/xpsxflow.opt | 1 + .../data/RTOSDemo.ucf | 41 + .../etc/RTOSDemo.filters | 159 + .../etc/RTOSDemo.gui | 220 + Demo/MicroBlaze_Spartan-6_SP605/etc/bitgen.ut | 3 + .../etc/download.cmd | 6 + .../etc/fast_runtime.opt | 84 + .../implementation/RTOSDemo_summary.html | 62 + 40 files changed, 20463 insertions(+) create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.bsb create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.make create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.mhs create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo_incl.make create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtSvgDiag_Colors.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtSvgDiag_Globals.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Functions.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Globals.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/bitinit.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_globals.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_view.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_view_addr.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_view_busif.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_view_groups.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/edw2xtl_sav_view_port.xsl create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/gensav_cmd.xml create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/ise/RTOSDemo.xreport create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/ise/xmsgprops.lst create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/platgen.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/simgen.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/system.xml create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/xplorer.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/__xps/xpsxflow.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/data/RTOSDemo.ucf create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.filters create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.gui create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/etc/bitgen.ut create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/etc/download.cmd create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/etc/fast_runtime.opt create mode 100644 Demo/MicroBlaze_Spartan-6_SP605/implementation/RTOSDemo_summary.html diff --git a/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.bsb b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.bsb new file mode 100644 index 000000000..3e61fc53e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.bsb @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.make b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.make new file mode 100644 index 000000000..5d96a9b8d --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.make @@ -0,0 +1,216 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\RTOSDemo.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\RTOSDemo.mhs + +include RTOSDemo_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: exporttosdk + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttosdk: Export files to SDK" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " simclean : Deletes simulation dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +exporttosdk: $(SYSTEM_HW_HANDOFF_DEP) + +netlist: $(POSTSYN_NETLIST) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral & \ + RTOSDemo_fuse.cmd + cd simulation/behavioral & \ + start /B $(SIM_CMD) -gui -tclbatch RTOSDemo_setup.tcl + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +clean: hwclean simclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + rm -f __xps/ise/_xmsgs/bitinit.xmsgs + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f __xps/ise/_xmsgs/platgen.xmsgs + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + rm -f implementation/download.bit + rm -f __xps/$(SYSTEM)_routed + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + rm -f __xps/ise/_xmsgs/simgen.xmsgs + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + +$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP_LE) + IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)" + cp -f $(MICROBLAZE_BOOTLOOP_LE) $(MICROBLAZE_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + cd synthesis & synthesis.cmd + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @cp -f etc/fast_runtime.opt implementation/xflow.opt + xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE) + xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd .. + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): + @echo "In order to generate ace file, you must have:-" + @echo "- exactly one processor." + @echo "- opb_mdm, if using microblaze." + +################################################################# +# EXPORT_TO_SDK FLOW +################################################################# + +$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt + IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)" + psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT) + xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local + +$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT) + @rm -rf $(SYSTEM_HW_HANDOFF_BIT) + @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR) + +$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm + @rm -rf $(SYSTEM_HW_HANDOFF_BMM) + @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed + +$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.mhs b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.mhs new file mode 100644 index 000000000..c38ca16ff --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.mhs @@ -0,0 +1,326 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d +# Mon May 30 16:46:06 2011 +# Target Board: xilinx.com sp605 Rev C +# Family: spartan6 +# Device: xc6slx45t +# Package: fgg484 +# Speed Grade: -3 +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 + PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 + PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 + PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O + PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I + PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [0:3] + PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [0:3] + PORT Ethernet_Lite_MDIO = Ethernet_Lite_MDIO, DIR = IO + PORT Ethernet_Lite_MDC = Ethernet_Lite_MDC, DIR = O + PORT Ethernet_Lite_TXD = Ethernet_Lite_TXD, DIR = O, VEC = [3:0] + PORT Ethernet_Lite_TX_EN = Ethernet_Lite_TX_EN, DIR = O + PORT Ethernet_Lite_TX_CLK = Ethernet_Lite_TX_CLK, DIR = I + PORT Ethernet_Lite_COL = Ethernet_Lite_COL, DIR = I + PORT Ethernet_Lite_RXD = Ethernet_Lite_RXD, DIR = I, VEC = [3:0] + PORT Ethernet_Lite_RX_ER = Ethernet_Lite_RX_ER, DIR = I + PORT Ethernet_Lite_RX_CLK = Ethernet_Lite_RX_CLK, DIR = I + PORT Ethernet_Lite_CRS = Ethernet_Lite_CRS, DIR = I + PORT Ethernet_Lite_RX_DV = Ethernet_Lite_RX_DV, DIR = I + PORT Ethernet_Lite_PHY_RST_N = Ethernet_Lite_PHY_RST_N, DIR = O + + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4_0 + PARAMETER HW_VER = 1.02.a + PORT interconnect_aclk = clk_100_0000MHzPLL0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4lite_0 + PARAMETER HW_VER = 1.02.a + PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn + PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 8.10.a + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_BARREL = 1 + PARAMETER C_USE_FPU = 1 + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_ICACHE_BASEADDR = 0xc0000000 + PARAMETER C_ICACHE_HIGHADDR = 0xcfffffff + PARAMETER C_USE_ICACHE = 1 + PARAMETER C_ICACHE_ALWAYS_USED = 1 + PARAMETER C_DCACHE_BASEADDR = 0xc0000000 + PARAMETER C_DCACHE_HIGHADDR = 0xcfffffff + PARAMETER C_USE_DCACHE = 1 + PARAMETER C_DCACHE_ALWAYS_USED = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1 + BUS_INTERFACE ILMB = microblaze_0_ilmb + BUS_INTERFACE DLMB = microblaze_0_dlmb + BUS_INTERFACE M_AXI_DP = axi4lite_0 + BUS_INTERFACE M_AXI_DC = axi4_0 + BUS_INTERFACE M_AXI_IC = axi4_0 + BUS_INTERFACE DEBUG = microblaze_0_debug + PORT MB_RESET = proc_sys_reset_0_MB_Reset + PORT CLK = clk_100_0000MHzPLL0 + PORT INTERRUPT = microblaze_0_interrupt +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_ilmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_dlmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_i_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_ilmb + BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_d_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_dlmb + BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN bram_block + PARAMETER INSTANCE = microblaze_0_bram_block + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block + BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PORT Ext_Reset_In = RESET + PORT MB_Reset = proc_sys_reset_0_MB_Reset + PORT Slowest_sync_clk = clk_50_0000MHzPLL0 + PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn + PORT Dcm_locked = proc_sys_reset_0_Dcm_locked + PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER HW_VER = 4.01.a + PARAMETER C_CLKIN_FREQ = 200000000 + PARAMETER C_CLKOUT0_FREQ = 600000000 + PARAMETER C_CLKOUT0_GROUP = PLL0 + PARAMETER C_CLKOUT0_BUF = FALSE + PARAMETER C_CLKOUT1_FREQ = 600000000 + PARAMETER C_CLKOUT1_PHASE = 180 + PARAMETER C_CLKOUT1_GROUP = PLL0 + PARAMETER C_CLKOUT1_BUF = FALSE + PARAMETER C_CLKOUT2_FREQ = 100000000 + PARAMETER C_CLKOUT2_GROUP = PLL0 + PARAMETER C_CLKOUT3_FREQ = 50000000 + PARAMETER C_CLKOUT3_GROUP = PLL0 + PORT RST = RESET + PORT CLKIN = CLK + PORT CLKOUT2 = clk_100_0000MHzPLL0 + PORT CLKOUT3 = clk_50_0000MHzPLL0 + PORT LOCKED = proc_sys_reset_0_Dcm_locked +END + +BEGIN mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.b + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_UART = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x74800000 + PARAMETER C_HIGHADDR = 0x7480ffff + BUS_INTERFACE S_AXI = axi4lite_0 + BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst +END + +BEGIN axi_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BAUDRATE = 115200 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT TX = RS232_Uart_1_sout + PORT RX = RS232_Uart_1_sin + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = RS232_Uart_1_Interrupt +END + +BEGIN axi_gpio + PARAMETER INSTANCE = LEDs_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_O = LEDs_4Bits_TRI_O + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN axi_gpio + PARAMETER INSTANCE = Push_Buttons_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt +END + +BEGIN axi_ethernetlite + PARAMETER INSTANCE = Ethernet_Lite + PARAMETER HW_VER = 1.00.a + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40e00000 + PARAMETER C_HIGHADDR = 0x40e0ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT PHY_MDIO = Ethernet_Lite_MDIO + PORT PHY_MDC = Ethernet_Lite_MDC + PORT PHY_tx_data = Ethernet_Lite_TXD + PORT PHY_tx_en = Ethernet_Lite_TX_EN + PORT PHY_tx_clk = Ethernet_Lite_TX_CLK + PORT PHY_col = Ethernet_Lite_COL + PORT PHY_rx_data = Ethernet_Lite_RXD + PORT PHY_rx_er = Ethernet_Lite_RX_ER + PORT PHY_rx_clk = Ethernet_Lite_RX_CLK + PORT PHY_crs = Ethernet_Lite_CRS + PORT PHY_dv = Ethernet_Lite_RX_DV + PORT PHY_rst_n = Ethernet_Lite_PHY_RST_N + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT IP2INTC_Irpt = Ethernet_Lite_IP2INTC_Irpt +END + +BEGIN axi_timer + PARAMETER INSTANCE = axi_timer_0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_COUNT_WIDTH = 32 + PARAMETER C_ONE_TIMER_ONLY = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = axi_timer_0_Interrupt +END + +BEGIN axi_bram_ctrl + PARAMETER INSTANCE = axi_bram_ctrl_0 + PARAMETER HW_VER = 1.02.a + PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_S_AXI_BASEADDR = 0xC4000000 + PARAMETER C_S_AXI_HIGHADDR = 0xC407FFFF + BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta + BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb + BUS_INTERFACE S_AXI = axi4_0 + PORT S_AXI_ACLK = clk_100_0000MHzPLL0 +END + +BEGIN bram_block + PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta + BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb +END + +BEGIN axi_intc + PARAMETER INSTANCE = microblaze_0_intc + PARAMETER HW_VER = 1.01.a + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT IRQ = microblaze_0_interrupt + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT INTR = RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt +END + diff --git a/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp new file mode 100644 index 000000000..9abde6152 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp @@ -0,0 +1,30 @@ +#Please do not modify this file by hand +XmpVersion: 13.1 +VerMgmt: 13.1 +IntStyle: default +MHS File: RTOSDemo.mhs +Architecture: spartan6 +Device: xc6slx45t +Package: fgg484 +SpeedGrade: -3 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +SimModel: BEHAVIORAL +UcfFile: data/RTOSDemo.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +ICacheAddr: axi_bram_ctrl_0,C_S_AXI_BASEADDR +ICacheAddr: axi_bram_ctrl_0,C_S_AXI_CTRL_BASEADDR +DCacheAddr: axi_bram_ctrl_0,C_S_AXI_BASEADDR +DCacheAddr: axi_bram_ctrl_0,C_S_AXI_CTRL_BASEADDR +Processor: microblaze_0 +ElfImp: +ElfSim: diff --git a/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo_incl.make b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo_incl.make new file mode 100644 index 000000000..092e2805c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo_incl.make @@ -0,0 +1,111 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\RTOSDemo.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +SHELL = CMD + +XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK + +SYSTEM = RTOSDemo + +MHSFILE = RTOSDemo.mhs + +FPGA_ARCH = spartan6 + +DEVICE = xc6slx45tfgg484-3 + +LANGUAGE = vhdl +GLOBAL_SEARCHPATHOPT = +PROJECT_SEARCHPATHOPT = + +SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst + +OBSERVE_PAR_OPTIONS = -error yes + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf + +BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +SIM_CMD = isim_RTOSDemo + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim + + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \ +implementation/axi4lite_0_wrapper.ngc \ +implementation/microblaze_0_wrapper.ngc \ +implementation/microblaze_0_ilmb_wrapper.ngc \ +implementation/microblaze_0_dlmb_wrapper.ngc \ +implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_bram_block_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/debug_module_wrapper.ngc \ +implementation/rs232_uart_1_wrapper.ngc \ +implementation/leds_4bits_wrapper.ngc \ +implementation/push_buttons_4bits_wrapper.ngc \ +implementation/ethernet_lite_wrapper.ngc \ +implementation/axi_timer_0_wrapper.ngc \ +implementation/axi_bram_ctrl_0_wrapper.ngc \ +implementation/axi_bram_ctrl_0_bram_block_wrapper.ngc \ +implementation/microblaze_0_intc_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/RTOSDemo.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Block RAM (BRAM) Block + The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interrupt Controller + intc core attached to the AXI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Interrupt Request Output + + + + + + + + + + Interrupt Inputs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_SP605/__xps/xplorer.opt b/Demo/MicroBlaze_Spartan-6_SP605/__xps/xplorer.opt new file mode 100644 index 000000000..f6181b718 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/__xps/xplorer.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/RTOSDemo.ucf 7 0 diff --git a/Demo/MicroBlaze_Spartan-6_SP605/__xps/xpsxflow.opt b/Demo/MicroBlaze_Spartan-6_SP605/__xps/xpsxflow.opt new file mode 100644 index 000000000..5cd677422 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/__xps/xpsxflow.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/RTOSDemo.ucf 0 diff --git a/Demo/MicroBlaze_Spartan-6_SP605/data/RTOSDemo.ucf b/Demo/MicroBlaze_Spartan-6_SP605/data/RTOSDemo.ucf new file mode 100644 index 000000000..681ad6274 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/data/RTOSDemo.ucf @@ -0,0 +1,41 @@ +# +# pin constraints +# +NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET Ethernet_Lite_COL LOC = "M16" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_CRS LOC = "N15" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG; +NET Ethernet_Lite_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25"; +NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG; +NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25"; +NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25"; +# +# additional constraints +# + +NET "CLK" TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; + diff --git a/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.filters b/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.filters new file mode 100644 index 000000000..79ac1a59b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.filters @@ -0,0 +1,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.gui b/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.gui new file mode 100644 index 000000000..2b3010426 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/etc/RTOSDemo.gui @@ -0,0 +1,220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_SP605/etc/bitgen.ut b/Demo/MicroBlaze_Spartan-6_SP605/etc/bitgen.ut new file mode 100644 index 000000000..bca21c81b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/etc/bitgen.ut @@ -0,0 +1,3 @@ +-g TdoPin:PULLNONE +-g StartUpClk:JTAGCLK +#add other options here. diff --git a/Demo/MicroBlaze_Spartan-6_SP605/etc/download.cmd b/Demo/MicroBlaze_Spartan-6_SP605/etc/download.cmd new file mode 100644 index 000000000..da4d7717e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 2 -file implementation/download.bit +program -p 2 +quit diff --git a/Demo/MicroBlaze_Spartan-6_SP605/etc/fast_runtime.opt b/Demo/MicroBlaze_Spartan-6_SP605/etc/fast_runtime.opt new file mode 100644 index 000000000..994a6d2f8 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/etc/fast_runtime.opt @@ -0,0 +1,84 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +-detail; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/MicroBlaze_Spartan-6_SP605/implementation/RTOSDemo_summary.html b/Demo/MicroBlaze_Spartan-6_SP605/implementation/RTOSDemo_summary.html new file mode 100644 index 000000000..0ffeadcbb --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_SP605/implementation/RTOSDemo_summary.html @@ -0,0 +1,62 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + +
RTOSDemo Project Status
Project File:RTOSDemo.xmpImplementation State:New
Module Name:RTOSDemo
  • Errors:
 
Product Version:EDK 13.1
  • Warnings:
 
+ + + + 
+ + + + + + + + +
XPS Reports [-]
Report NameGeneratedErrorsWarningsInfos
Platgen Log File    
Libgen Log File    
Simgen Log File    
BitInit Log File    
System Log FileMon 30. May 16:47:01 2011   
+ + + + + + + + + 
+ + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Translation Report     
Map Report     
Place and Route Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 05/30/2011 - 16:47:01
+ \ No newline at end of file -- 2.39.2