From e1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 30 Jan 2008 15:35:50 +0100 Subject: [PATCH] ppc4xx: Fix GPIO configuration for pcs440ep The SRD0_PFC0 register was not configured correctly to enable the GPIO's 49-63 for GPIO. They have been configured as trace signals. This patch fixes this by clearing the corresponding bit. Signed-off-by: Stefan Roese --- board/pcs440ep/pcs440ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 90e99d3dca..96adbc915d 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -175,7 +175,7 @@ int board_early_init_f(void) *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ + mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; -- 2.39.5