From e2b6f347c72b1291c34cf23057d04edde6841670 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 24 Aug 2018 13:01:49 -0700 Subject: [PATCH] Clarify what exactly the RISC-V code supports. Change-Id: I8da657426cc52c738ab41bfb0164cbc6721c0aef Signed-off-by: Tim Newsome Reviewed-on: http://openocd.zylin.com/4655 Tested-by: jenkins Reviewed-by: Philipp Guehring Reviewed-by: Liviu Ionescu Reviewed-by: Tomas Vanek --- doc/openocd.texi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index e87d8c29..bbe6cffd 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9022,8 +9022,11 @@ Display all registers in @emph{group}. @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug -Specification. +debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32 +harts. (It's possible to increase this limit to 1024 by changing +RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V +Debug Specification, but there is also support for legacy targets that +implement version 0.11. @subsection RISC-V Terminology -- 2.39.5