From e3a27ff5c06308cac98d4906a77f6eacfef803b0 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Mon, 17 Sep 2007 09:51:42 +0000 Subject: [PATCH] Remove separate LM3Sxxxx directories. These have been replaced by consolidated directories in the V4.5.0 version. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@108 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/CORTEX_LM3S2965_GCC/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../CORTEX_LM3S2965_GCC/LuminaryDrivers/adc.h | 130 -- .../CORTEX_LM3S2965_GCC/LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../CORTEX_LM3S2965_GCC/LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../CORTEX_LM3S2965_GCC/LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/libdriver.a | Bin 88936 -> 0 bytes .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../CORTEX_LM3S2965_GCC/LuminaryDrivers/pwm.h | 161 -- .../CORTEX_LM3S2965_GCC/LuminaryDrivers/qei.h | 104 - .../CORTEX_LM3S2965_GCC/LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/ustdlib.c | 418 ---- .../LuminaryDrivers/ustdlib.h | 46 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S2965_GCC/Makefile | 85 - Demo/CORTEX_LM3S2965_GCC/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S2965_GCC/bitmap.h | 171 -- Demo/CORTEX_LM3S2965_GCC/lcd_message.h | 9 - Demo/CORTEX_LM3S2965_GCC/main.c | 313 --- Demo/CORTEX_LM3S2965_GCC/makedefs | 208 -- Demo/CORTEX_LM3S2965_GCC/standalone.ld | 60 - Demo/CORTEX_LM3S2965_GCC/startup.c | 234 --- Demo/CORTEX_LM3S2965_GCC/timertest.c | 133 -- Demo/CORTEX_LM3S2965_IAR/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../CORTEX_LM3S2965_IAR/LuminaryDrivers/adc.h | 130 -- .../CORTEX_LM3S2965_IAR/LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../CORTEX_LM3S2965_IAR/LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/driverlib.r79 | Bin 192492 -> 0 bytes .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../CORTEX_LM3S2965_IAR/LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../CORTEX_LM3S2965_IAR/LuminaryDrivers/pwm.h | 161 -- .../CORTEX_LM3S2965_IAR/LuminaryDrivers/qei.h | 104 - .../CORTEX_LM3S2965_IAR/LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S2965_IAR/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S2965_IAR/RTOSDemo.dep | 856 -------- Demo/CORTEX_LM3S2965_IAR/RTOSDemo.ewd | 1133 ----------- Demo/CORTEX_LM3S2965_IAR/RTOSDemo.ewp | 1728 ---------------- Demo/CORTEX_LM3S2965_IAR/RTOSDemo.eww | 10 - Demo/CORTEX_LM3S2965_IAR/RTOSDemo.xcl | 56 - Demo/CORTEX_LM3S2965_IAR/bitmap.h | 171 -- Demo/CORTEX_LM3S2965_IAR/lcd_message.h | 9 - Demo/CORTEX_LM3S2965_IAR/main.c | 307 --- Demo/CORTEX_LM3S2965_IAR/startup_ewarm.c | 265 --- Demo/CORTEX_LM3S2965_IAR/timertest.c | 133 -- Demo/CORTEX_LM3S2965_KEIL/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/DriverLib.lib | Bin 1019382 -> 0 bytes .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../LuminaryDrivers/adc.h | 130 -- .../LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../LuminaryDrivers/pwm.h | 161 -- .../LuminaryDrivers/qei.h | 104 - .../LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S2965_KEIL/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Opt | 55 - Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Uv2 | 118 -- Demo/CORTEX_LM3S2965_KEIL/bitmap.h | 171 -- Demo/CORTEX_LM3S2965_KEIL/lcd_message.h | 9 - Demo/CORTEX_LM3S2965_KEIL/main.c | 313 --- Demo/CORTEX_LM3S2965_KEIL/startup_rvmdk.S | 247 --- Demo/CORTEX_LM3S2965_KEIL/timertest.c | 133 -- Demo/CORTEX_LM3S6965_GCC/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../CORTEX_LM3S6965_GCC/LuminaryDrivers/adc.h | 130 -- .../CORTEX_LM3S6965_GCC/LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../CORTEX_LM3S6965_GCC/LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../CORTEX_LM3S6965_GCC/LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/libdriver.a | Bin 88936 -> 0 bytes .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../CORTEX_LM3S6965_GCC/LuminaryDrivers/pwm.h | 161 -- .../CORTEX_LM3S6965_GCC/LuminaryDrivers/qei.h | 104 - .../CORTEX_LM3S6965_GCC/LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/ustdlib.c | 670 ------- .../LuminaryDrivers/ustdlib.h | 48 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S6965_GCC/Makefile | 101 - Demo/CORTEX_LM3S6965_GCC/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S6965_GCC/bitmap.h | 171 -- Demo/CORTEX_LM3S6965_GCC/lcd_message.h | 9 - Demo/CORTEX_LM3S6965_GCC/main.c | 331 ---- Demo/CORTEX_LM3S6965_GCC/makedefs | 208 -- Demo/CORTEX_LM3S6965_GCC/standalone.ld | 60 - Demo/CORTEX_LM3S6965_GCC/startup.c | 248 --- Demo/CORTEX_LM3S6965_GCC/timertest.c | 133 -- .../webserver/Makefile.webserver | 1 - .../webserver/clock-arch.h | 42 - Demo/CORTEX_LM3S6965_GCC/webserver/emac.c | 281 --- Demo/CORTEX_LM3S6965_GCC/webserver/emac.h | 322 --- .../webserver/http-strings | 35 - .../webserver/http-strings.c | 102 - .../webserver/http-strings.h | 34 - .../CORTEX_LM3S6965_GCC/webserver/httpd-cgi.c | 269 --- .../CORTEX_LM3S6965_GCC/webserver/httpd-cgi.h | 84 - Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.c | 132 -- Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.h | 57 - .../webserver/httpd-fs/404.html | 8 - .../webserver/httpd-fs/index.html | 13 - .../webserver/httpd-fs/index.shtml | 20 - .../webserver/httpd-fs/io.shtml | 28 - .../webserver/httpd-fs/stats.shtml | 41 - .../webserver/httpd-fs/tcp.shtml | 21 - .../webserver/httpd-fsdata.c | 470 ----- .../webserver/httpd-fsdata.h | 64 - Demo/CORTEX_LM3S6965_GCC/webserver/httpd.c | 346 ---- Demo/CORTEX_LM3S6965_GCC/webserver/httpd.h | 62 - Demo/CORTEX_LM3S6965_GCC/webserver/makefsdata | 78 - .../CORTEX_LM3S6965_GCC/webserver/makestrings | 40 - Demo/CORTEX_LM3S6965_GCC/webserver/uIP_Task.c | 300 --- Demo/CORTEX_LM3S6965_GCC/webserver/uip-conf.h | 159 -- .../CORTEX_LM3S6965_GCC/webserver/webserver.h | 49 - Demo/CORTEX_LM3S6965_IAR/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../CORTEX_LM3S6965_IAR/LuminaryDrivers/adc.h | 130 -- .../CORTEX_LM3S6965_IAR/LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../CORTEX_LM3S6965_IAR/LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/driverlib.r79 | Bin 192492 -> 0 bytes .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../CORTEX_LM3S6965_IAR/LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../CORTEX_LM3S6965_IAR/LuminaryDrivers/pwm.h | 161 -- .../CORTEX_LM3S6965_IAR/LuminaryDrivers/qei.h | 104 - .../CORTEX_LM3S6965_IAR/LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S6965_IAR/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S6965_IAR/RTOSDemo.dep | 856 -------- Demo/CORTEX_LM3S6965_IAR/RTOSDemo.ewd | 1133 ----------- Demo/CORTEX_LM3S6965_IAR/RTOSDemo.ewp | 1761 ----------------- Demo/CORTEX_LM3S6965_IAR/RTOSDemo.eww | 10 - Demo/CORTEX_LM3S6965_IAR/RTOSDemo.xcl | 56 - Demo/CORTEX_LM3S6965_IAR/bitmap.h | 171 -- Demo/CORTEX_LM3S6965_IAR/lcd_message.h | 9 - Demo/CORTEX_LM3S6965_IAR/main.c | 325 --- Demo/CORTEX_LM3S6965_IAR/startup_ewarm.c | 265 --- Demo/CORTEX_LM3S6965_IAR/timertest.c | 133 -- .../webserver/Makefile.webserver | 1 - .../webserver/clock-arch.h | 42 - Demo/CORTEX_LM3S6965_IAR/webserver/emac.c | 281 --- Demo/CORTEX_LM3S6965_IAR/webserver/emac.h | 322 --- .../webserver/http-strings | 35 - .../webserver/http-strings.c | 102 - .../webserver/http-strings.h | 34 - .../CORTEX_LM3S6965_IAR/webserver/httpd-cgi.c | 269 --- .../CORTEX_LM3S6965_IAR/webserver/httpd-cgi.h | 84 - Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.c | 132 -- Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.h | 57 - .../webserver/httpd-fs/404.html | 8 - .../webserver/httpd-fs/index.html | 13 - .../webserver/httpd-fs/index.shtml | 20 - .../webserver/httpd-fs/io.shtml | 28 - .../webserver/httpd-fs/stats.shtml | 41 - .../webserver/httpd-fs/tcp.shtml | 21 - .../webserver/httpd-fsdata.c | 470 ----- .../webserver/httpd-fsdata.h | 64 - Demo/CORTEX_LM3S6965_IAR/webserver/httpd.c | 346 ---- Demo/CORTEX_LM3S6965_IAR/webserver/httpd.h | 62 - Demo/CORTEX_LM3S6965_IAR/webserver/makefsdata | 78 - .../CORTEX_LM3S6965_IAR/webserver/makestrings | 40 - Demo/CORTEX_LM3S6965_IAR/webserver/uIP_Task.c | 300 --- Demo/CORTEX_LM3S6965_IAR/webserver/uip-conf.h | 159 -- .../CORTEX_LM3S6965_IAR/webserver/webserver.h | 49 - Demo/CORTEX_LM3S6965_KEIL/FreeRTOSConfig.h | 80 - .../LuminaryDrivers/DriverLib.lib | Bin 1019382 -> 0 bytes .../LuminaryDrivers/LM3Sxxx.h | 64 - .../LuminaryDrivers/LM3Sxxxx.h | 70 - .../LuminaryDrivers/_flash.h | 78 - .../LuminaryDrivers/_timer.h | 137 -- .../LuminaryDrivers/adc.h | 130 -- .../LuminaryDrivers/can.h | 441 ----- .../LuminaryDrivers/comp.h | 122 -- .../LuminaryDrivers/cpu.h | 40 - .../LuminaryDrivers/debug.h | 56 - .../LuminaryDrivers/ethernet.h | 254 --- .../LuminaryDrivers/gpio.h | 138 -- .../LuminaryDrivers/hibernate.h | 107 - .../LuminaryDrivers/hw_adc.h | 343 ---- .../LuminaryDrivers/hw_can.h | 379 ---- .../LuminaryDrivers/hw_comp.h | 118 -- .../LuminaryDrivers/hw_ethernet.h | 205 -- .../LuminaryDrivers/hw_flash.h | 147 -- .../LuminaryDrivers/hw_gpio.h | 115 -- .../LuminaryDrivers/hw_hibernate.h | 145 -- .../LuminaryDrivers/hw_i2c.h | 197 -- .../LuminaryDrivers/hw_ints.h | 113 -- .../LuminaryDrivers/hw_memmap.h | 80 - .../LuminaryDrivers/hw_nvic.h | 1050 ---------- .../LuminaryDrivers/hw_pwm.h | 260 --- .../LuminaryDrivers/hw_qei.h | 176 -- .../LuminaryDrivers/hw_ssi.h | 120 -- .../LuminaryDrivers/hw_sysctl.h | 659 ------ .../LuminaryDrivers/hw_timer.h | 235 --- .../LuminaryDrivers/hw_types.h | 129 -- .../LuminaryDrivers/hw_uart.h | 241 --- .../LuminaryDrivers/hw_watchdog.h | 116 -- .../LuminaryDrivers/i2c.h | 137 -- .../LuminaryDrivers/interrupt.h | 57 - .../LuminaryDrivers/lmi_flash.h | 78 - .../LuminaryDrivers/lmi_timer.h | 137 -- .../LuminaryDrivers/osram128x64x4.c | 933 --------- .../LuminaryDrivers/osram128x64x4.h | 63 - .../LuminaryDrivers/pwm.h | 161 -- .../LuminaryDrivers/qei.h | 104 - .../LuminaryDrivers/ssi.h | 89 - .../LuminaryDrivers/sysctl.h | 301 --- .../LuminaryDrivers/systick.h | 55 - .../LuminaryDrivers/uart.h | 104 - .../LuminaryDrivers/watchdog.h | 63 - Demo/CORTEX_LM3S6965_KEIL/ParTest/ParTest.c | 83 - Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Opt | 70 - Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Uv2 | 129 -- Demo/CORTEX_LM3S6965_KEIL/bitmap.h | 171 -- Demo/CORTEX_LM3S6965_KEIL/lcd_message.h | 9 - Demo/CORTEX_LM3S6965_KEIL/main.c | 331 ---- Demo/CORTEX_LM3S6965_KEIL/startup_rvmdk.S | 248 --- Demo/CORTEX_LM3S6965_KEIL/timertest.c | 133 -- .../webserver/Makefile.webserver | 1 - .../webserver/clock-arch.h | 42 - Demo/CORTEX_LM3S6965_KEIL/webserver/emac.c | 281 --- Demo/CORTEX_LM3S6965_KEIL/webserver/emac.h | 322 --- .../webserver/http-strings | 35 - .../webserver/http-strings.c | 102 - .../webserver/http-strings.h | 34 - .../webserver/httpd-cgi.c | 269 --- .../webserver/httpd-cgi.h | 84 - .../CORTEX_LM3S6965_KEIL/webserver/httpd-fs.c | 132 -- .../CORTEX_LM3S6965_KEIL/webserver/httpd-fs.h | 57 - .../webserver/httpd-fs/404.html | 8 - .../webserver/httpd-fs/index.html | 13 - .../webserver/httpd-fs/index.shtml | 20 - .../webserver/httpd-fs/io.shtml | 28 - .../webserver/httpd-fs/stats.shtml | 41 - .../webserver/httpd-fs/tcp.shtml | 21 - .../webserver/httpd-fsdata.c | 470 ----- .../webserver/httpd-fsdata.h | 64 - Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.c | 346 ---- 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100644 index b97aac5b8..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxx.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxx.h deleted file mode 100644 index 11952d416..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxx.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXX_H__ -#define __LM3SXXX_H__ - -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXX_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxxx.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxxx.h deleted file mode 100644 index bafb07cda..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/LM3Sxxxx.h +++ /dev/null @@ -1,70 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXXX_H__ -#define __LM3SXXXX_H__ - -#include "hw_adc.h" -#include "hw_can.h" -#include "hw_comp.h" -#include "hw_ethernet.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_hibernate.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "can.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "ethernet.h" -#include "flash.h" -#include "gpio.h" -#include "hibernate.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXXX_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_flash.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_timer.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/adc.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/adc.h deleted file mode 100644 index 7533ccfd8..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/adc.h +++ /dev/null @@ -1,130 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceOverflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceUnderflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/can.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/can.h deleted file mode 100644 index bdd623304..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/can.h +++ /dev/null @@ -1,441 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CAN_H__ -#define __CAN_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -//! These are the flags used by the tCANMsgObject variable when calling the -//! the CANMessageSet() and CANMessageGet() APIs. -// -//***************************************************************************** -typedef enum -{ - // - //! This indicates that transmit interrupts should be enabled, or are - //! enabled. - // - MSG_OBJ_TX_INT_ENABLE = 0x00000001, - - // - //! This indicates that receive interrupts should be enabled or are - //! enabled. - // - MSG_OBJ_RX_INT_ENABLE = 0x00000002, - - // - //! This indicates that a message object will use or is using an extended - //! identifier. - // - MSG_OBJ_EXTENDED_ID = 0x00000004, - - // - //! This indicates that a message object will use or is using filtering - //! based on the object's message Identifier. - // - MSG_OBJ_USE_ID_FILTER = 0x00000008, - - // - //! This indicates that new data was available in the message object. - // - MSG_OBJ_NEW_DATA = 0x00000080, - - // - //! This indicates that data was lost since this message object was last - //! read. - // - MSG_OBJ_DATA_LOST = 0x00000100, - - // - //! This indicates that a message object will use or is using filtering - //! based on the direction of the transfer. If the direction filtering is - //! used then ID filtering must also be enabled. - // - MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object will use or is using message - //! identifier filtering based of the the extended identifier. - //! If the extended identifier filtering is used then ID filtering must - //! also be enabled. - // - MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object is a remote frame. - // - MSG_OBJ_REMOTE_FRAME = 0x00000040, - - // - //! This indicates that a message object has no flags set. - // - MSG_OBJ_NO_FLAGS = 0x00000000 -} -tCANObjFlags; - -//***************************************************************************** -// -//! This define is used with the #tCANObjFlags enumerated values to allow -//! checking only status flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! This structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - unsigned long ulMsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - unsigned long ulMsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - unsigned long ulFlags; - - // - //! This value is the number of bytes of data in the message object. - // - unsigned long ulMsgLen; - - // - //! This is a pointer to the message object's data. - // - unsigned char *pucMsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - unsigned int uSyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - unsigned int uPhase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - unsigned int uSJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - unsigned int uQuantumPrescaler; - -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the a CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of the several status registers -//! to read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32 bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32 bit mask of message objects with a new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32 bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -//! These definitions are used to specify interrupt sources to CANIntEnable() -//! and CANIntDisable(). -// -//***************************************************************************** -typedef enum -{ - // - //! This flag is used to allow a CAN controller to generate error - //! interrupts. - // - CAN_INT_ERROR = 0x00000008, - - // - //! This flag is used to allow a CAN controller to generate status - //! interrupts. - // - CAN_INT_STATUS = 0x00000004, - - // - //! This flag is used to allow a CAN controller to generate any CAN - //! interrupts. If this is not set then no interrupts will be generated by - //! the CAN controller. - // - CAN_INT_MASTER = 0x00000002 -} -tCANIntFlags; - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that will -//! be set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -//! The following enumeration contains all error or status indicators that -//! can be returned when calling the CANStatusGet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! CAN controller has entered a Bus Off state. - // - CAN_STATUS_BUS_OFF = 0x00000080, - - // - //! CAN controller error level has reached warning level. - // - CAN_STATUS_EWARN = 0x00000040, - - // - //! CAN controller error level has reached error passive level. - // - CAN_STATUS_EPASS = 0x00000020, - - // - //! A message was received successfully since the last read of this status. - // - CAN_STATUS_RXOK = 0x00000010, - - // - //! A message was transmitted successfully since the last read of this - //! status. - // - CAN_STATUS_TXOK = 0x00000008, - - // - //! This is the mask for the last error code field. - // - CAN_STATUS_LEC_MSK = 0x00000007, - - // - //! There was no error. - // - CAN_STATUS_LEC_NONE = 0x00000000, - - // - //! A bit stuffing error has occurred. - // - CAN_STATUS_LEC_STUFF = 0x00000001, - - // - //! A formatting error has occurred. - // - CAN_STATUS_LEC_FORM = 0x00000002, - - // - //! An acknowledge error has occurred. - // - CAN_STATUS_LEC_ACK = 0x00000003, - - // - //! The bus remained a bit level of 1 for longer than is allowed. - // - CAN_STATUS_LEC_BIT1 = 0x00000004, - - // - //! The bus remained a bit level of 0 for longer than is allowed. - // - CAN_STATUS_LEC_BIT0 = 0x00000005, - - // - //! A CRC error has occurred. - // - CAN_STATUS_LEC_CRC = 0x00000006, - - // - //! This is the mask for the CAN Last Error Code (LEC). - // - CAN_STATUS_LEC_MASK = 0x00000007 -} -tCANStatusCtrl; - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANInit(unsigned long ulBase); -extern void CANEnable(unsigned long ulBase); -extern void CANDisable(unsigned long ulBase); -extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern unsigned long CANReadReg(unsigned long ulRegAddress); -extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); -extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tMsgObjType eMsgType); -extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); -extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); -extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); -extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); -extern unsigned long CANIntStatus(unsigned long ulBase, - tCANIntStsReg eIntStsReg); -extern tBoolean CANRetryGet(unsigned long ulBase); -extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); -extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, - unsigned long *pulTxCount); -extern long CANGetIntNumber(unsigned long ulBase); -extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); -extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#ifdef __cplusplus -} -#endif - -#endif // __CAN_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/comp.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/comp.h deleted file mode 100644 index 60fa1e04e..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/comp.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#ifndef DEPRECATED -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#endif -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/cpu.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/cpu.h deleted file mode 100644 index f21f82221..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/debug.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/debug.h deleted file mode 100644 index c64b8fc2d..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ethernet.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ethernet.h deleted file mode 100644 index 127763f2c..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ethernet.h +++ /dev/null @@ -1,254 +0,0 @@ -//***************************************************************************** -// -// ethernet.h - Defines and Macros for the ethernet module. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ETHERNET_H__ -#define __ETHERNET_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EthernetConfigSet as the ulConfig value, and -// returned from EthernetConfigGet. -// -//***************************************************************************** -#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets -#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous -#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast -#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode -#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation -#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding - -//***************************************************************************** -// -// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and -// EthernetIntClear as the ulIntFlags parameter, and returned from -// EthernetIntStatus. -// -//***************************************************************************** -#define ETH_INT_PHY 0x040 // PHY Event/Interrupt -#define ETH_INT_MDIO 0x020 // Management Transaction -#define ETH_INT_RXER 0x010 // RX Error -#define ETH_INT_RXOF 0x008 // RX FIFO Overrun -#define ETH_INT_TX 0x004 // TX Complete -#define ETH_INT_TXER 0x002 // TX Error -#define ETH_INT_RX 0x001 // RX Complete - -//***************************************************************************** -// -// The following define values that can be passed as register addresses to -// EthernetPHYRead and EthernetPHYWrite. -// -//***************************************************************************** -#define PHY_MR0 0 // Control -#define PHY_MR1 1 // Status -#define PHY_MR2 2 // PHY Identifier 1 -#define PHY_MR3 3 // PHY Identifier 2 -#define PHY_MR4 4 // Auto-Neg. Advertisement -#define PHY_MR5 5 // Auto-Neg. Link Partner Ability -#define PHY_MR6 6 // Auto-Neg. Expansion - // 7-15 Reserved/Not Implemented -#define PHY_MR16 16 // Vendor Specific -#define PHY_MR17 17 // Interrupt Control/Status -#define PHY_MR18 18 // Diagnostic Register -#define PHY_MR19 19 // Transceiver Control - // 20-22 Reserved -#define PHY_MR23 23 // LED Configuration Register -#define PHY_MR24 24 // MDI/MDIX Control Register - // 25-31 Reserved/Not Implemented - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR0 register -// -//***************************************************************************** -#define PHY_MR0_RESET 0x8000 // Reset the PHY -#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback -#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection -#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T -#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T -#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable -#define PHY_MR0_PWRDN 0x0800 // Power Down -#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation -#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex -#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode -#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR1 register -// -//***************************************************************************** -#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete -#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected -#define PHY_MR1_LINK 0x0004 // Link Established -#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR17 register -// -//***************************************************************************** -#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt -#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int. -#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int. -#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt -#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt -#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int. - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR18 register -// -//***************************************************************************** -#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed -#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated -#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated -#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated -#define PHY_MR18_RATE 0x0400 // Rate Negotiated -#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T -#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR23 register -// -//***************************************************************************** -#define PHY_MR23_LED1 0x00f0 // LED1 Configuration -#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status -#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity -#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity -#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity -#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity -#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity -#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity -#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity -#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity -#define PHY_MR23_LED0 0x000f // LED0 Configuration -#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status -#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity -#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity -#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity -#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity -#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity -#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity -#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity -#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR24 register -// -//***************************************************************************** -#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration -#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough -#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - big endian/little endian byte swapping macros for -// 32-bit (long) values -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - big endian/little endian byte swapping macros for -// 16-bit (short) values -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/libdriver.a b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/libdriver.a deleted file mode 100644 index b5de5a193bc316196a75daed3f28ddb1a0d16b1a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 88936 zcmeFa4Pafxc_uvP-YZ#_t}R&-ARA#{OESpVxWYEXfRkM7+Sfla*s)DQTG~j+0ttkr zNHRZ38e~jb5@?pi?3TnyOB=SEHfbvZ-lc7*RZMsJ653Br(v~D7aZ-Y)p!;1BK@>y7 zKF`d&=gb*h#ZGDa(VvmdJ@dZrGw=MKIWzB>GiT}gj)BhZca{HKChji2cwNh7>)vtc zrI%$gEn4LMW-{+seX(I=+RK#+-m6sozJJ+wdj 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-//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.c b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.c deleted file mode 100644 index 472f9deeb..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.c +++ /dev/null @@ -1,418 +0,0 @@ -//***************************************************************************** -// -// ustdlib.c - Simple standard library functions. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -#include -#include -#include "debug.h" - -//***************************************************************************** -// -//! \addtogroup utilities_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A mapping from an integer between 0 and 15 to its ASCII character -// equivalent. -// -//***************************************************************************** -static const char * const g_pcHex = "0123456789abcdef"; - -//***************************************************************************** -// -//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. -//! -//! \param pcBuf is the buffer where the converted string is stored. -//! \param pcString is the format string. -//! \param ... are the optional arguments, which depend on the contents of the -//! format string. -//! -//! This function is very similar to the C library sprintf() function. -//! Only the following formatting characters are supported: -//! -//! - \%c to print a character -//! - \%d to print a decimal value -//! - \%s to print a string -//! - \%u to print an unsigned decimal value -//! - \%x to print a hexadecimal value using lower case letters -//! - \%X to print a hexadecimal value using lower case letters (not upper case -//! letters as would typically be used) -//! - \%\% to print out a \% character -//! -//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% -//! and the format character, which specifies the minimum number of characters -//! to use for that value; if preceeded by a 0 then the extra characters will -//! be filled with zeros instead of spaces. For example, ``\%8d'' will use -//! eight characters to print the decimal value with spaces added to reach -//! eight; ``\%08d'' will use eight characters as well but will add zeros -//! instead of spaces. -//! -//! The type of the arguments after \b pcString must match the requirements of -//! the format string. For example, if an integer was passed where a string -//! was expected, an error of some kind will most likely occur. -//! -//! The caller must ensure that the buffer pcBuf is large enough to hold the -//! entire converted string, including the null termination character. -//! -//! \return None. -// -//***************************************************************************** -void -usprintf(char *pcBuf, const char *pcString, ...) -{ - unsigned long ulIdx, ulValue, ulPos, ulCount, ulBase; - char *pcStr, cFill; - va_list vaArgP; - - // - // Check the arguments. - // - ASSERT(pcString != 0); - ASSERT(pcBuf != 0); - - // - // Start the varargs processing. - // - va_start(vaArgP, pcString); - - // - // Loop while there are more characters in the string. - // - while(*pcString) - { - // - // Find the first non-% character, or the end of the string. - // - for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0'); - ulIdx++) - { - } - - // - // Write this portion of the string. - // - strncpy(pcBuf, pcString, ulIdx); - - // - // Skip the portion of the string that was written. - // - pcString += ulIdx; - pcBuf += ulIdx; - - // - // See if the next character is a %. - // - if(*pcString == '%') - { - // - // Skip the %. - // - pcString++; - - // - // Set the digit count to zero, and the fill character to space - // (i.e. to the defaults). - // - ulCount = 0; - cFill = ' '; - - // - // It may be necessary to get back here to process more characters. - // Goto's aren't pretty, but effective. I feel extremely dirty for - // using not one but two of the beasts. - // -again: - - // - // Determine how to handle the next character. - // - switch(*pcString++) - { - // - // Handle the digit characters. - // - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - // - // If this is a zero, and it is the first digit, then the - // fill character is a zero instead of a space. - // - if((pcString[-1] == '0') && (ulCount == 0)) - { - cFill = '0'; - } - - // - // Update the digit count. - // - ulCount *= 10; - ulCount += pcString[-1] - '0'; - - // - // Get the next character. - // - goto again; - } - - // - // Handle the %c command. - // - case 'c': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Print out the character. - // - *pcBuf++ = (char)ulValue; - - // - // This command has been handled. - // - break; - } - - // - // Handle the %d command. - // - case 'd': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Reset the buffer position. - // - ulPos = 0; - - // - // If the value is negative, make it positive and stick a - // minus sign in the beginning of the buffer. - // - if((long)ulValue < 0) - { - *pcBuf++ = '-'; - ulPos++; - ulValue = -(long)ulValue; - } - - // - // Set the base to 10. - // - ulBase = 10; - - // - // Convert the value to ASCII. - // - goto convert; - } - - // - // Handle the %s command. - // - case 's': - { - // - // Get the string pointer from the varargs. - // - pcStr = va_arg(vaArgP, char *); - - // - // Determine the length of the string. - // - for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) - { - } - - // - // Write the string. - // - strncpy(pcBuf, pcStr, ulIdx); - pcBuf += ulIdx; - - // - // This command has been handled. - // - break; - } - - // - // Handle the %u command. - // - case 'u': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Reset the buffer position. - // - ulPos = 0; - - // - // Set the base to 10. - // - ulBase = 10; - - // - // Convert the value to ASCII. - // - goto convert; - } - - // - // Handle the %x and %X commands. Note that they are treated - // identically; i.e. %X will use lower case letters for a-f - // instead of the upper case letters is should use. - // - case 'x': - case 'X': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Reset the buffer position. - // - ulPos = 0; - - // - // Set the base to 16. - // - ulBase = 16; - - // - // Determine the number of digits in the string version of - // the value. - // -convert: - for(ulIdx = 1; - (((ulIdx * ulBase) <= ulValue) && - (((ulIdx * ulBase) / ulBase) == ulIdx)); - ulIdx *= ulBase, ulCount--) - { - } - - // - // Provide additional padding at the beginning of the - // string conversion if needed. - // - if((ulCount > 1) && (ulCount < 16)) - { - for(ulCount--; ulCount; ulCount--) - { - *pcBuf++ = cFill; - ulPos++; - } - } - - // - // Convert the value into a string. - // - for(; ulIdx; ulIdx /= ulBase) - { - *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase]; - ulPos++; - } - - // - // This command has been handled. - // - break; - } - - // - // Handle the %% command. - // - case '%': - { - // - // Simply write a single %. - // - *pcBuf++ = pcString[-1]; - - // - // This command has been handled. - // - break; - } - - // - // Handle all other commands. - // - default: - { - // - // Indicate an error. - // - strncpy(pcBuf, "ERROR", 5); - pcBuf += 5; - - // - // This command has been handled. - // - break; - } - } - } - } - - // - // End the varargs processing. - // - va_end(vaArgP); - - // - // Null terminate the string in the buffer. - // - *pcBuf = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.h deleted file mode 100644 index f950d8173..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/ustdlib.h +++ /dev/null @@ -1,46 +0,0 @@ -//***************************************************************************** -// -// uartstdlib.h - Prototypes for simple standard library functions. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// -//***************************************************************************** - -#ifndef __UARTSTDLIB_H__ -#define __UARTSTDLIB_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void usprintf(char *, const char *pcString, ...); - -#ifdef __cplusplus -} -#endif - -#endif // __UARTSTDLIB_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_GCC/Makefile b/Demo/CORTEX_LM3S2965_GCC/Makefile deleted file mode 100644 index e9bb5f2b9..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/Makefile +++ /dev/null @@ -1,85 +0,0 @@ -#****************************************************************************** -# -# Makefile - Rules for building the driver library and examples. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -include makedefs - -RTOS_SOURCE_DIR=../../Source -DEMO_SOURCE_DIR=../Common/Minimal - -CFLAGS+=-I LuminaryDrivers -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= -D sprintf=usprintf - -VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:LuminaryDrivers:ParTest - -OBJS=${COMPILER}/main.o \ - ${COMPILER}/list.o \ - ${COMPILER}/queue.o \ - ${COMPILER}/tasks.o \ - ${COMPILER}/port.o \ - ${COMPILER}/heap_2.o \ - ${COMPILER}/BlockQ.o \ - ${COMPILER}/PollQ.o \ - ${COMPILER}/integer.o \ - ${COMPILER}/semtest.o \ - ${COMPILER}/osram128x64x4.o \ - ${COMPILER}/blocktim.o \ - ${COMPILER}/death.o \ - ${COMPILER}/ParTest.o \ - ${COMPILER}/timertest.o \ - ${COMPILER}/ustdlib.o - -INIT_OBJS= ${COMPILER}/startup.o - -LIBS= LuminaryDrivers/libdriver.a - - -# -# The default rule, which causes init to be built. -# -all: ${COMPILER} \ - ${COMPILER}/RTOSDemo.axf \ - -# -# The rule to clean out all the build products -# - -clean: - @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf - -# -# The rule to create the target directory -# -${COMPILER}: - @mkdir ${COMPILER} - -${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} -SCATTER_RTOSDemo=standalone.ld -ENTRY_RTOSDemo=ResetISR - -# -# -# Include the automatically generated dependency files. -# --include ${wildcard ${COMPILER}/*.d} __dummy__ - diff --git a/Demo/CORTEX_LM3S2965_GCC/ParTest/ParTest.c b/Demo/CORTEX_LM3S2965_GCC/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S2965_GCC/bitmap.h b/Demo/CORTEX_LM3S2965_GCC/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, -0x00 }; - -#define bmpBITMAP_HEIGHT 50 -#define bmpBITMAP_WIDTH 128 - -#endif diff --git a/Demo/CORTEX_LM3S2965_GCC/lcd_message.h b/Demo/CORTEX_LM3S2965_GCC/lcd_message.h deleted file mode 100644 index ced7a1dbc..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/lcd_message.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef LCD_MESSAGE_H -#define LCD_MESSAGE_H - -typedef struct -{ - char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S2965_GCC/main.c b/Demo/CORTEX_LM3S2965_GCC/main.c deleted file mode 100644 index 41f5ca569..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/main.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - #ifdef __ICCARM__ - vSetupTimer(); - #endif - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - #ifdef __ICCARM__ - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - #else - sprintf( cPassMessage, "PASS" ); - #endif - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S2965_GCC/makedefs b/Demo/CORTEX_LM3S2965_GCC/makedefs deleted file mode 100644 index efd7530d4..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/makedefs +++ /dev/null @@ -1,208 +0,0 @@ -#****************************************************************************** -# -# makedefs - Definitions common to all makefiles. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -#****************************************************************************** -# -# Get the operating system name. If this is Cygwin, the .d files will be -# munged to convert c: into /cygdrive/c so that "make" will be happy with the -# auto-generated dependencies. -# -#****************************************************************************** -os:=${shell uname -s} - -#****************************************************************************** -# -# The compiler to be used. -# -#****************************************************************************** -ifndef COMPILER -COMPILER=gcc -endif - -#****************************************************************************** -# -# The debugger to be used. -# -#****************************************************************************** -ifndef DEBUGGER -DEBUGGER=gdb -endif - -#****************************************************************************** -# -# Definitions for using GCC. -# -#****************************************************************************** -ifeq (${COMPILER}, gcc) - -# -# The command for calling the compiler. -# -CC=arm-stellaris-eabi-gcc - -# -# The flags passed to the assembler. -# -AFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -MD - -# -# The flags passed to the compiler. -# -CFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -O2 \ - -MD - -# -# The command for calling the library archiver. -# -AR=arm-stellaris-eabi-ar - -# -# The command for calling the linker. -# -LD=arm-stellaris-eabi-ld - -# -# The flags passed to the linker. -# -LDFLAGS= -Map gcc/out.map - -# -# Get the location of libgcc.a from the GCC front-end. -# -LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} - -# -# Get the location of libc.a from the GCC front-end. -# -LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} - -# -# The command for extracting images from the linked executables. -# -OBJCOPY=arm-stellaris-eabi-objcopy - -endif - -#****************************************************************************** -# -# Tell the compiler to include debugging information if the DEBUG environment -# variable is set. -# -#****************************************************************************** -ifdef DEBUG -CFLAGS += -g -endif - -#****************************************************************************** -# -# The rule for building the object file from each C source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.c - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi - @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} -ifeq (${COMPILER}, rvds) - @mv -f ${notdir ${@:.o=.d}} ${COMPILER} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for building the object file from each assembly source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.S - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi -ifeq (${COMPILER}, rvds) - @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} - @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} - @rm ${@:.o=_.S} - @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} - @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} - @rm ${notdir ${<:.S=.d}} -endif -ifeq (${COMPILER}, gcc) - @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for creating an object library. -# -#****************************************************************************** -${COMPILER}/%.a: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " AR ${@}"; \ - else \ - echo ${AR} -cr ${@} ${^}; \ - fi - @${AR} -cr ${@} ${^} - -#****************************************************************************** -# -# The rule for linking the application. -# -#****************************************************************************** -${COMPILER}/%.axf: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " LD ${@}"; \ - fi -ifeq (${COMPILER}, gcc) - @if [ 'x${VERBOSE}' != x ]; \ - then \ - echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}'; \ - fi - @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}' - @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} -endif diff --git a/Demo/CORTEX_LM3S2965_GCC/standalone.ld b/Demo/CORTEX_LM3S2965_GCC/standalone.ld deleted file mode 100644 index 35111445b..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/standalone.ld +++ /dev/null @@ -1,60 +0,0 @@ -/****************************************************************************** - * - * standalone.ld - Linker script for applications using startup.c and - * DriverLib. - * - * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. - * - * Software License Agreement - * - * Luminary Micro, Inc. (LMI) is supplying this software for use solely and - * exclusively on LMI's microcontroller products. - * - * The software is owned by LMI and/or its suppliers, and is protected under - * applicable copyright laws. All rights are reserved. Any use in violation - * of the foregoing restrictions may subject the user to criminal sanctions - * under applicable laws, as well as to civil liability for the breach of the - * terms and conditions of this license. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 1392 of the Stellaris Peripheral Driver Library. - * - *****************************************************************************/ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - *(.rodata*) - _etext = .; - } > FLASH - - .data : AT (ADDR(.text) + SIZEOF(.text)) - { - _data = .; - *(vtable) - *(.data*) - _edata = .; - } > SRAM - - .bss : - { - _bss = .; - *(.bss*) - *(COMMON) - _ebss = .; - } > SRAM -} diff --git a/Demo/CORTEX_LM3S2965_GCC/startup.c b/Demo/CORTEX_LM3S2965_GCC/startup.c deleted file mode 100644 index 7530af16d..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/startup.c +++ /dev/null @@ -1,234 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1392 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void Timer0IntHandler(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - Timer0IntHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // Quadrature Encoder 1 - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - 0, // Reserved - IntDefaultHandler, // Ethernet - IntDefaultHandler // Hibernate -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied main() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_bss; pulDest < &_ebss; ) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S2965_GCC/timertest.c b/Demo/CORTEX_LM3S2965_GCC/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S2965_GCC/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S2965_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S2965_IAR/FreeRTOSConfig.h deleted file mode 100644 index 709dc0d3e..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxx.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxx.h deleted file mode 100644 index 11952d416..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxx.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXX_H__ -#define __LM3SXXX_H__ - -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXX_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxxx.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxxx.h deleted file mode 100644 index bafb07cda..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/LM3Sxxxx.h +++ /dev/null @@ -1,70 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXXX_H__ -#define __LM3SXXXX_H__ - -#include "hw_adc.h" -#include "hw_can.h" -#include "hw_comp.h" -#include "hw_ethernet.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_hibernate.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "can.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "ethernet.h" -#include "flash.h" -#include "gpio.h" -#include "hibernate.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXXX_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_flash.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_timer.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/adc.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/adc.h deleted file mode 100644 index 7533ccfd8..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/adc.h +++ /dev/null @@ -1,130 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceOverflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceUnderflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/can.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/can.h deleted file mode 100644 index bdd623304..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/can.h +++ /dev/null @@ -1,441 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CAN_H__ -#define __CAN_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -//! These are the flags used by the tCANMsgObject variable when calling the -//! the CANMessageSet() and CANMessageGet() APIs. -// -//***************************************************************************** -typedef enum -{ - // - //! This indicates that transmit interrupts should be enabled, or are - //! enabled. - // - MSG_OBJ_TX_INT_ENABLE = 0x00000001, - - // - //! This indicates that receive interrupts should be enabled or are - //! enabled. - // - MSG_OBJ_RX_INT_ENABLE = 0x00000002, - - // - //! This indicates that a message object will use or is using an extended - //! identifier. - // - MSG_OBJ_EXTENDED_ID = 0x00000004, - - // - //! This indicates that a message object will use or is using filtering - //! based on the object's message Identifier. - // - MSG_OBJ_USE_ID_FILTER = 0x00000008, - - // - //! This indicates that new data was available in the message object. - // - MSG_OBJ_NEW_DATA = 0x00000080, - - // - //! This indicates that data was lost since this message object was last - //! read. - // - MSG_OBJ_DATA_LOST = 0x00000100, - - // - //! This indicates that a message object will use or is using filtering - //! based on the direction of the transfer. If the direction filtering is - //! used then ID filtering must also be enabled. - // - MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object will use or is using message - //! identifier filtering based of the the extended identifier. - //! If the extended identifier filtering is used then ID filtering must - //! also be enabled. - // - MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object is a remote frame. - // - MSG_OBJ_REMOTE_FRAME = 0x00000040, - - // - //! This indicates that a message object has no flags set. - // - MSG_OBJ_NO_FLAGS = 0x00000000 -} -tCANObjFlags; - -//***************************************************************************** -// -//! This define is used with the #tCANObjFlags enumerated values to allow -//! checking only status flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! This structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - unsigned long ulMsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - unsigned long ulMsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - unsigned long ulFlags; - - // - //! This value is the number of bytes of data in the message object. - // - unsigned long ulMsgLen; - - // - //! This is a pointer to the message object's data. - // - unsigned char *pucMsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - unsigned int uSyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - unsigned int uPhase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - unsigned int uSJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - unsigned int uQuantumPrescaler; - -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the a CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of the several status registers -//! to read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32 bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32 bit mask of message objects with a new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32 bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -//! These definitions are used to specify interrupt sources to CANIntEnable() -//! and CANIntDisable(). -// -//***************************************************************************** -typedef enum -{ - // - //! This flag is used to allow a CAN controller to generate error - //! interrupts. - // - CAN_INT_ERROR = 0x00000008, - - // - //! This flag is used to allow a CAN controller to generate status - //! interrupts. - // - CAN_INT_STATUS = 0x00000004, - - // - //! This flag is used to allow a CAN controller to generate any CAN - //! interrupts. If this is not set then no interrupts will be generated by - //! the CAN controller. - // - CAN_INT_MASTER = 0x00000002 -} -tCANIntFlags; - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that will -//! be set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -//! The following enumeration contains all error or status indicators that -//! can be returned when calling the CANStatusGet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! CAN controller has entered a Bus Off state. - // - CAN_STATUS_BUS_OFF = 0x00000080, - - // - //! CAN controller error level has reached warning level. - // - CAN_STATUS_EWARN = 0x00000040, - - // - //! CAN controller error level has reached error passive level. - // - CAN_STATUS_EPASS = 0x00000020, - - // - //! A message was received successfully since the last read of this status. - // - CAN_STATUS_RXOK = 0x00000010, - - // - //! A message was transmitted successfully since the last read of this - //! status. - // - CAN_STATUS_TXOK = 0x00000008, - - // - //! This is the mask for the last error code field. - // - CAN_STATUS_LEC_MSK = 0x00000007, - - // - //! There was no error. - // - CAN_STATUS_LEC_NONE = 0x00000000, - - // - //! A bit stuffing error has occurred. - // - CAN_STATUS_LEC_STUFF = 0x00000001, - - // - //! A formatting error has occurred. - // - CAN_STATUS_LEC_FORM = 0x00000002, - - // - //! An acknowledge error has occurred. - // - CAN_STATUS_LEC_ACK = 0x00000003, - - // - //! The bus remained a bit level of 1 for longer than is allowed. - // - CAN_STATUS_LEC_BIT1 = 0x00000004, - - // - //! The bus remained a bit level of 0 for longer than is allowed. - // - CAN_STATUS_LEC_BIT0 = 0x00000005, - - // - //! A CRC error has occurred. - // - CAN_STATUS_LEC_CRC = 0x00000006, - - // - //! This is the mask for the CAN Last Error Code (LEC). - // - CAN_STATUS_LEC_MASK = 0x00000007 -} -tCANStatusCtrl; - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANInit(unsigned long ulBase); -extern void CANEnable(unsigned long ulBase); -extern void CANDisable(unsigned long ulBase); -extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern unsigned long CANReadReg(unsigned long ulRegAddress); -extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); -extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tMsgObjType eMsgType); -extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); -extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); -extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); -extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); -extern unsigned long CANIntStatus(unsigned long ulBase, - tCANIntStsReg eIntStsReg); -extern tBoolean CANRetryGet(unsigned long ulBase); -extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); -extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, - unsigned long *pulTxCount); -extern long CANGetIntNumber(unsigned long ulBase); -extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); -extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#ifdef __cplusplus -} -#endif - -#endif // __CAN_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/comp.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/comp.h deleted file mode 100644 index 60fa1e04e..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/comp.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#ifndef DEPRECATED -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#endif -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/cpu.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/cpu.h deleted file mode 100644 index f21f82221..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/debug.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/debug.h deleted file mode 100644 index c64b8fc2d..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. 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2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ETHERNET_H__ -#define __ETHERNET_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EthernetConfigSet as the ulConfig value, and -// returned from EthernetConfigGet. -// -//***************************************************************************** -#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets -#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous -#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast -#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode -#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation -#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding - -//***************************************************************************** -// -// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and -// EthernetIntClear as the ulIntFlags parameter, and returned from -// EthernetIntStatus. -// -//***************************************************************************** -#define ETH_INT_PHY 0x040 // PHY Event/Interrupt -#define ETH_INT_MDIO 0x020 // Management Transaction -#define ETH_INT_RXER 0x010 // RX Error -#define ETH_INT_RXOF 0x008 // RX FIFO Overrun -#define ETH_INT_TX 0x004 // TX Complete -#define ETH_INT_TXER 0x002 // TX Error -#define ETH_INT_RX 0x001 // RX Complete - -//***************************************************************************** -// -// The following define values that can be passed as register addresses to -// EthernetPHYRead and EthernetPHYWrite. -// -//***************************************************************************** -#define PHY_MR0 0 // Control -#define PHY_MR1 1 // Status -#define PHY_MR2 2 // PHY Identifier 1 -#define PHY_MR3 3 // PHY Identifier 2 -#define PHY_MR4 4 // Auto-Neg. Advertisement -#define PHY_MR5 5 // Auto-Neg. Link Partner Ability -#define PHY_MR6 6 // Auto-Neg. Expansion - // 7-15 Reserved/Not Implemented -#define PHY_MR16 16 // Vendor Specific -#define PHY_MR17 17 // Interrupt Control/Status -#define PHY_MR18 18 // Diagnostic Register -#define PHY_MR19 19 // Transceiver Control - // 20-22 Reserved -#define PHY_MR23 23 // LED Configuration Register -#define PHY_MR24 24 // MDI/MDIX Control Register - // 25-31 Reserved/Not Implemented - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR0 register -// -//***************************************************************************** -#define PHY_MR0_RESET 0x8000 // Reset the PHY -#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback -#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection -#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T -#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T -#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable -#define PHY_MR0_PWRDN 0x0800 // Power Down -#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation -#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex -#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode -#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR1 register -// -//***************************************************************************** -#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete -#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected -#define PHY_MR1_LINK 0x0004 // Link Established -#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR17 register -// -//***************************************************************************** -#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt -#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int. -#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int. -#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt -#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt -#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int. - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR18 register -// -//***************************************************************************** -#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed -#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated -#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated -#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated -#define PHY_MR18_RATE 0x0400 // Rate Negotiated -#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T -#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR23 register -// -//***************************************************************************** -#define PHY_MR23_LED1 0x00f0 // LED1 Configuration -#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status -#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity -#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity -#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity -#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity -#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity -#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity -#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity -#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity -#define PHY_MR23_LED0 0x000f // LED0 Configuration -#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status -#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity -#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity -#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity -#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity -#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity -#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity -#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity -#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR24 register -// -//***************************************************************************** -#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration -#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough -#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - big endian/little endian byte swapping macros for -// 32-bit (long) values -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - big endian/little endian byte swapping macros for -// 16-bit (short) values -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_flash.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_IAR/ParTest/ParTest.c b/Demo/CORTEX_LM3S2965_IAR/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S2965_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S2965_IAR/RTOSDemo.dep deleted file mode 100644 index 9b6787905..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/RTOSDemo.dep +++ /dev/null @@ -1,856 +0,0 @@ - - - - 2 - - Debug - - $TOOLKIT_DIR$\inc\stddef.h - $PROJ_DIR$\Debug\Obj\flash.pbi - $PROJ_DIR$\Debug\Obj\uIP_Task.pbi - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\Debug\Obj\blocktim.r79 - $TOOLKIT_DIR$\inc\stdlib.h - $TOOLKIT_DIR$\lib\dl7mptnnl8n.h - $PROJ_DIR$\..\Common\include\blocktim.h - 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Linker script for EW-ARM. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -// -// Set the CPU type to ARM. -// --carm - -// -// Define the size of flash and SRAM. -// --DROMSTART=00000000 --DROMEND=00040000 --DRAMSTART=20000000 --DRAMEND=20010000 - - - -// -// Define the sections to place into flash, and the order to place them. -// --Z(CODE)INTVEC=ROMSTART-ROMEND --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)CODE=ROMSTART-ROMEND --Z(CONST)CODE_ID=ROMSTART-ROMEND --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -// -// Define the sections to place into SRAM, and the order to place them. -// --Z(DATA)VTABLE=RAMSTART-RAMEND --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND --Z(DATA)CODE_I=RAMSTART-RAMEND diff --git a/Demo/CORTEX_LM3S2965_IAR/bitmap.h b/Demo/CORTEX_LM3S2965_IAR/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, -0x00 }; - -#define bmpBITMAP_HEIGHT 50 -#define bmpBITMAP_WIDTH 128 - -#endif diff --git a/Demo/CORTEX_LM3S2965_IAR/lcd_message.h b/Demo/CORTEX_LM3S2965_IAR/lcd_message.h deleted file mode 100644 index adfc18b8a..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/lcd_message.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef LCD_MESSAGE_H -#define LCD_MESSAGE_H - -typedef struct -{ - signed char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S2965_IAR/main.c b/Demo/CORTEX_LM3S2965_IAR/main.c deleted file mode 100644 index 68530c29b..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/main.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - vSetupTimer(); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S2965_IAR/startup_ewarm.c b/Demo/CORTEX_LM3S2965_IAR/startup_ewarm.c deleted file mode 100644 index fe6effc46..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/startup_ewarm.c +++ /dev/null @@ -1,265 +0,0 @@ -//***************************************************************************** -// -// startup_ewarm.c - Boot code for Stellaris. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 100 of the Stellaris Ethernet -// Applications Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// External declaration for the interrupt handler used by the application. -// -//***************************************************************************** - - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vEMAC_ISR( void ); -extern Timer0IntHandler( void ); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = -{ - { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - Timer0IntHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // Quadrature Encoder 1 - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // CAN2 - IntDefaultHandler, // Ethernet - IntDefaultHandler // Power Island -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S2965_IAR/timertest.c b/Demo/CORTEX_LM3S2965_IAR/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S2965_IAR/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S2965_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S2965_KEIL/FreeRTOSConfig.h deleted file mode 100644 index b97aac5b8..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/DriverLib.lib b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/DriverLib.lib deleted file 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ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_flash.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S2965_KEIL/ParTest/ParTest.c b/Demo/CORTEX_LM3S2965_KEIL/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Opt b/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Opt deleted file mode 100644 index 3fc7df23e..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Opt +++ /dev/null @@ -1,55 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' -GRPOPT 1,(Demo_Source),0,0,0 -GRPOPT 2,(Libraries),0,0,0 -GRPOPT 3,(RTOS_Source),0,0,0 - -OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> -OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c> -OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c> -OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c> -OPTFFF 1,5,1,0,0,0,0,0,<.\main.c> -OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c> -OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> -OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> -OPTFFF 1,9,2,570425344,0,0,0,0,<.\startup_rvmdk.S> -OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c> -OPTFFF 1,11,5,0,0,0,0,0,<.\FreeRTOSConfig.h> -OPTFFF 2,12,4,0,0,0,0,0,<.\LuminaryDrivers\driverlib.lib> -OPTFFF 2,13,1,0,0,0,0,0,<.\LuminaryDrivers\osram128x64x4.c> -OPTFFF 3,14,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 3,15,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 3,16,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 3,17,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> -OPTFFF 3,18,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> - - -TARGOPT 1, (FreeRTOS_Demo) - ADSCLK=6000000 - OPTTT 1,1,1,0 - OPTHX 1,65535,0,0,0 - OPTLX 79,66,8,<.\rvmdk\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTAX 255 - OPTBL 0,(Data Sheet) - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S2965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S2965) - OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - OPTDF 0x0 - OPTLE <> - OPTLC <> -EndOpt - diff --git a/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Uv2 b/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Uv2 deleted file mode 100644 index 745475b8e..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/RTOSDemo.Uv2 +++ /dev/null @@ -1,118 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' - -Group (Demo_Source) -Group (Libraries) -Group (RTOS_Source) - -File 1,1,<..\Common\Minimal\BlockQ.c> 0x46520544 -File 1,1,<..\Common\Minimal\blocktim.c> 0x46520544 -File 1,1,<..\Common\Minimal\death.c> 0x46520544 -File 1,1,<..\Common\Minimal\integer.c> 0x46520544 -File 1,1,<.\main.c> 0x4664B508 -File 1,1,<.\ParTest\ParTest.c> 0x46520580 -File 1,1,<..\Common\Minimal\PollQ.c> 0x46520544 -File 1,1,<..\Common\Minimal\semtest.c> 0x46520544 -File 1,2,<.\startup_rvmdk.S> 0x4664BAF8 -File 1,1,<.\timertest.c> 0x46520544 -File 1,5,<.\FreeRTOSConfig.h> 0x46638356 -File 2,4,<.\LuminaryDrivers\driverlib.lib> 0x46647F6C -File 2,1,<.\LuminaryDrivers\osram128x64x4.c> 0x46649D66 -File 3,1,<..\..\Source\tasks.c> 0x46520544 -File 3,1,<..\..\Source\list.c> 0x46520544 -File 3,1,<..\..\Source\queue.c> 0x46520544 -File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x44FB69B0 -File 3,1,<..\..\Source\portable\MemMang\heap_2.c> 0x46520580 - - -Options 1,0,0 // Target 'FreeRTOS_Demo' - Device (LM3S2965) - Vendor (Luminary Micro) - Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) - FlashUt () - StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) - FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) - DevID (4322) - Rgf (LM3Sxxxx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin () - EnvInc () - EnvLib () - EnvReg (ÿLuminary\) - OrgReg (ÿLuminary\) - TgStat=16 - OutDir (.\rvmdk\) - OutName (RTOSDemo) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=1 - LstDir (.\rvmdk\) - HexSel=1 - MG32K=0 - TGMORE=0 - RunUsr 0 1 - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - CrunUsr 0 0 <> - CrunUsr 1 0 <> - SVCSID <> - GLFLAGS=1790 - ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ACPUTYP ("Cortex-M3") - ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } - OCMADSIROM { 1,0,0,0,0,0,0,4,0 } - OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } - OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } - RV_STAVEC () - ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSCMISC () - ADSCDEFN (RVDS_ARMCM3_LM3S102) - ADSCUDEF () - ADSCINCD (.;.\LuminaryDrivers;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include) - ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSAMISC () - ADSADEFN () - ADSAUDEF () - ADSAINCD () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSLDTA (0x00000000) - ADSLDDA (0x20000000) - ADSLDSC () - ADSLDIB () - ADSLDIC () - ADSLDMC (--entry Reset_Handler) - ADSLDIF () - ADSLDDW () - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S2965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S2965) - OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\lmidk-agdi.dll) - FLASH3 ("" ()) - FLASH4 () -EndOpt - diff --git a/Demo/CORTEX_LM3S2965_KEIL/bitmap.h b/Demo/CORTEX_LM3S2965_KEIL/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, -0x00 }; - -#define bmpBITMAP_HEIGHT 50 -#define bmpBITMAP_WIDTH 128 - -#endif diff --git a/Demo/CORTEX_LM3S2965_KEIL/lcd_message.h b/Demo/CORTEX_LM3S2965_KEIL/lcd_message.h deleted file mode 100644 index ced7a1dbc..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/lcd_message.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef LCD_MESSAGE_H -#define LCD_MESSAGE_H - -typedef struct -{ - char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S2965_KEIL/main.c b/Demo/CORTEX_LM3S2965_KEIL/main.c deleted file mode 100644 index 41f5ca569..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/main.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - #ifdef __ICCARM__ - vSetupTimer(); - #endif - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - #ifdef __ICCARM__ - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - #else - sprintf( cPassMessage, "PASS" ); - #endif - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S2965_KEIL/startup_rvmdk.S b/Demo/CORTEX_LM3S2965_KEIL/startup_rvmdk.S deleted file mode 100644 index 1682047b9..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/startup_rvmdk.S +++ /dev/null @@ -1,247 +0,0 @@ -; <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** -; -; startup_rvmdk.S - Startup code for use with Keil's uVision. -; -; Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -; -; Software License Agreement -; -; Luminary Micro, Inc. (LMI) is supplying this software for use solely and -; exclusively on LMI's microcontroller products. -; -; The software is owned by LMI and/or its suppliers, and is protected under -; applicable copyright laws. All rights are reserved. Any use in violation -; of the foregoing restrictions may subject the user to criminal sanctions -; under applicable laws, as well as to civil liability for the breach of the -; terms and conditions of this license. -; -; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 1408 of the Stellaris Peripheral Driver Library. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Stack EQU 0x00000800 - -;****************************************************************************** -; -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack -__initial_sp - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -HeapMem - SPACE Heap -__heap_limit - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** - EXPORT __Vectors -__Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD FaultISR ; Hard Fault Handler - DCD IntDefaultHandler ; MPU Fault Handler - DCD IntDefaultHandler ; Bus Fault Handler - DCD IntDefaultHandler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; SVCall Handler - DCD IntDefaultHandler ; Debug Monitor Handler - DCD 0 ; Reserved - EXTERN xPortPendSVHandler - DCD xPortPendSVHandler ; PendSV Handler - EXTERN xPortSysTickHandler - DCD xPortSysTickHandler ; SysTick Handler - DCD IntDefaultHandler ; GPIO Port A - DCD IntDefaultHandler ; GPIO Port B - DCD IntDefaultHandler ; GPIO Port C - DCD IntDefaultHandler ; GPIO Port D - DCD IntDefaultHandler ; GPIO Port E - DCD IntDefaultHandler ; UART0 - DCD IntDefaultHandler ; UART1 - DCD IntDefaultHandler ; SSI - DCD IntDefaultHandler ; I2C - DCD IntDefaultHandler ; PWM Fault - DCD IntDefaultHandler ; PWM Generator 0 - DCD IntDefaultHandler ; PWM Generator 1 - DCD IntDefaultHandler ; PWM Generator 2 - DCD IntDefaultHandler ; Quadrature Encoder - DCD IntDefaultHandler ; ADC Sequence 0 - DCD IntDefaultHandler ; ADC Sequence 1 - DCD IntDefaultHandler ; ADC Sequence 2 - DCD IntDefaultHandler ; ADC Sequence 3 - DCD IntDefaultHandler ; Watchdog - EXTERN Timer0IntHandler - DCD Timer0IntHandler ; Timer 0A - DCD IntDefaultHandler ; Timer 0B - DCD IntDefaultHandler ; Timer 1A - DCD IntDefaultHandler ; Timer 1B - DCD IntDefaultHandler ; Timer 2A - DCD IntDefaultHandler ; Timer 2B - DCD IntDefaultHandler ; Comp 0 - DCD IntDefaultHandler ; Comp 1 - DCD IntDefaultHandler ; Comp 2 - DCD IntDefaultHandler ; System Control - DCD IntDefaultHandler ; Flash Control - DCD IntDefaultHandler ; GPIO Port F - DCD IntDefaultHandler ; GPIO Port G - DCD IntDefaultHandler ; GPIO Port H - DCD IntDefaultHandler ; UART2 Rx and Tx - DCD IntDefaultHandler ; SSI1 Rx and Tx - DCD IntDefaultHandler ; Timer 3 subtimer A - DCD IntDefaultHandler ; Timer 3 subtimer B - DCD IntDefaultHandler ; I2C1 Master and Slave - DCD IntDefaultHandler ; Quadrature Encoder 1 - DCD IntDefaultHandler ; CAN0 - DCD IntDefaultHandler ; CAN1 - DCD 0 ; Reserved - DCD IntDefaultHandler ; Ethernet - DCD IntDefaultHandler ; Hibernate - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** - EXPORT Reset_Handler -Reset_Handler - ; - ; Call the C library enty point that handles startup. This will copy - ; the .data section initializers from flash to SRAM and zero fill the - ; .bss section. It will then call __rt_entry, which will be either the - ; C library version or the one supplied here depending on the - ; configured startup type. - ; - IMPORT __main - B __main - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a NMI. This -; simply enters an infinite loop, preserving the system state for examination -; by a debugger. -; -;****************************************************************************** -NmiSR - B NmiSR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a fault -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -FaultISR - B FaultISR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives an unexpected -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -IntDefaultHandler - B IntDefaultHandler - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Some code in the normal code section for initializing the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; The function expected of the C library startup code for defining the stack -; and heap memory locations. For the C library version of the startup code, -; provide this function so that the C library initialization code can find out -; the location of the stack and heap. -; -;****************************************************************************** - IF :DEF: __MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - ENDIF - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Tell the assembler that we're done. -; -;****************************************************************************** - END diff --git a/Demo/CORTEX_LM3S2965_KEIL/timertest.c b/Demo/CORTEX_LM3S2965_KEIL/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S2965_KEIL/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/FreeRTOSConfig.h b/Demo/CORTEX_LM3S6965_GCC/FreeRTOSConfig.h deleted file mode 100644 index b97aac5b8..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxx.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxx.h deleted file mode 100644 index 11952d416..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxx.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXX_H__ -#define __LM3SXXX_H__ - -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXX_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxxx.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxxx.h deleted file mode 100644 index bafb07cda..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/LM3Sxxxx.h +++ /dev/null @@ -1,70 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXXX_H__ -#define __LM3SXXXX_H__ - -#include "hw_adc.h" -#include "hw_can.h" -#include "hw_comp.h" -#include "hw_ethernet.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_hibernate.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "can.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "ethernet.h" -#include "flash.h" -#include "gpio.h" -#include "hibernate.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXXX_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_flash.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_timer.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/adc.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/adc.h deleted file mode 100644 index 7533ccfd8..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/adc.h +++ /dev/null @@ -1,130 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceOverflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceUnderflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/can.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/can.h deleted file mode 100644 index bdd623304..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/can.h +++ /dev/null @@ -1,441 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CAN_H__ -#define __CAN_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -//! These are the flags used by the tCANMsgObject variable when calling the -//! the CANMessageSet() and CANMessageGet() APIs. -// -//***************************************************************************** -typedef enum -{ - // - //! This indicates that transmit interrupts should be enabled, or are - //! enabled. - // - MSG_OBJ_TX_INT_ENABLE = 0x00000001, - - // - //! This indicates that receive interrupts should be enabled or are - //! enabled. - // - MSG_OBJ_RX_INT_ENABLE = 0x00000002, - - // - //! This indicates that a message object will use or is using an extended - //! identifier. - // - MSG_OBJ_EXTENDED_ID = 0x00000004, - - // - //! This indicates that a message object will use or is using filtering - //! based on the object's message Identifier. - // - MSG_OBJ_USE_ID_FILTER = 0x00000008, - - // - //! This indicates that new data was available in the message object. - // - MSG_OBJ_NEW_DATA = 0x00000080, - - // - //! This indicates that data was lost since this message object was last - //! read. - // - MSG_OBJ_DATA_LOST = 0x00000100, - - // - //! This indicates that a message object will use or is using filtering - //! based on the direction of the transfer. If the direction filtering is - //! used then ID filtering must also be enabled. - // - MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object will use or is using message - //! identifier filtering based of the the extended identifier. - //! If the extended identifier filtering is used then ID filtering must - //! also be enabled. - // - MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object is a remote frame. - // - MSG_OBJ_REMOTE_FRAME = 0x00000040, - - // - //! This indicates that a message object has no flags set. - // - MSG_OBJ_NO_FLAGS = 0x00000000 -} -tCANObjFlags; - -//***************************************************************************** -// -//! This define is used with the #tCANObjFlags enumerated values to allow -//! checking only status flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! This structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - unsigned long ulMsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - unsigned long ulMsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - unsigned long ulFlags; - - // - //! This value is the number of bytes of data in the message object. - // - unsigned long ulMsgLen; - - // - //! This is a pointer to the message object's data. - // - unsigned char *pucMsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - unsigned int uSyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - unsigned int uPhase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - unsigned int uSJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - unsigned int uQuantumPrescaler; - -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the a CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of the several status registers -//! to read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32 bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32 bit mask of message objects with a new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32 bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -//! These definitions are used to specify interrupt sources to CANIntEnable() -//! and CANIntDisable(). -// -//***************************************************************************** -typedef enum -{ - // - //! This flag is used to allow a CAN controller to generate error - //! interrupts. - // - CAN_INT_ERROR = 0x00000008, - - // - //! This flag is used to allow a CAN controller to generate status - //! interrupts. - // - CAN_INT_STATUS = 0x00000004, - - // - //! This flag is used to allow a CAN controller to generate any CAN - //! interrupts. If this is not set then no interrupts will be generated by - //! the CAN controller. - // - CAN_INT_MASTER = 0x00000002 -} -tCANIntFlags; - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that will -//! be set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -//! The following enumeration contains all error or status indicators that -//! can be returned when calling the CANStatusGet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! CAN controller has entered a Bus Off state. - // - CAN_STATUS_BUS_OFF = 0x00000080, - - // - //! CAN controller error level has reached warning level. - // - CAN_STATUS_EWARN = 0x00000040, - - // - //! CAN controller error level has reached error passive level. - // - CAN_STATUS_EPASS = 0x00000020, - - // - //! A message was received successfully since the last read of this status. - // - CAN_STATUS_RXOK = 0x00000010, - - // - //! A message was transmitted successfully since the last read of this - //! status. - // - CAN_STATUS_TXOK = 0x00000008, - - // - //! This is the mask for the last error code field. - // - CAN_STATUS_LEC_MSK = 0x00000007, - - // - //! There was no error. - // - CAN_STATUS_LEC_NONE = 0x00000000, - - // - //! A bit stuffing error has occurred. - // - CAN_STATUS_LEC_STUFF = 0x00000001, - - // - //! A formatting error has occurred. - // - CAN_STATUS_LEC_FORM = 0x00000002, - - // - //! An acknowledge error has occurred. - // - CAN_STATUS_LEC_ACK = 0x00000003, - - // - //! The bus remained a bit level of 1 for longer than is allowed. - // - CAN_STATUS_LEC_BIT1 = 0x00000004, - - // - //! The bus remained a bit level of 0 for longer than is allowed. - // - CAN_STATUS_LEC_BIT0 = 0x00000005, - - // - //! A CRC error has occurred. - // - CAN_STATUS_LEC_CRC = 0x00000006, - - // - //! This is the mask for the CAN Last Error Code (LEC). - // - CAN_STATUS_LEC_MASK = 0x00000007 -} -tCANStatusCtrl; - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANInit(unsigned long ulBase); -extern void CANEnable(unsigned long ulBase); -extern void CANDisable(unsigned long ulBase); -extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern unsigned long CANReadReg(unsigned long ulRegAddress); -extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); -extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tMsgObjType eMsgType); -extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); -extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); -extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); -extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); -extern unsigned long CANIntStatus(unsigned long ulBase, - tCANIntStsReg eIntStsReg); -extern tBoolean CANRetryGet(unsigned long ulBase); -extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); -extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, - unsigned long *pulTxCount); -extern long CANGetIntNumber(unsigned long ulBase); -extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); -extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#ifdef __cplusplus -} -#endif - -#endif // __CAN_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/comp.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/comp.h deleted file mode 100644 index 60fa1e04e..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/comp.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#ifndef DEPRECATED -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#endif -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/cpu.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/cpu.h deleted file mode 100644 index f21f82221..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/debug.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/debug.h deleted file mode 100644 index c64b8fc2d..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ethernet.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ethernet.h deleted file mode 100644 index 127763f2c..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ethernet.h +++ /dev/null @@ -1,254 +0,0 @@ -//***************************************************************************** -// -// ethernet.h - Defines and Macros for the ethernet module. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ETHERNET_H__ -#define __ETHERNET_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EthernetConfigSet as the ulConfig value, and -// returned from EthernetConfigGet. -// -//***************************************************************************** -#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets -#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous -#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast -#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode -#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation -#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding - -//***************************************************************************** -// -// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and -// EthernetIntClear as the ulIntFlags parameter, and returned from -// EthernetIntStatus. -// -//***************************************************************************** -#define ETH_INT_PHY 0x040 // PHY Event/Interrupt -#define ETH_INT_MDIO 0x020 // Management Transaction -#define ETH_INT_RXER 0x010 // RX Error -#define ETH_INT_RXOF 0x008 // RX FIFO Overrun -#define ETH_INT_TX 0x004 // TX Complete -#define ETH_INT_TXER 0x002 // TX Error -#define ETH_INT_RX 0x001 // RX Complete - -//***************************************************************************** -// -// The following define values that can be passed as register addresses to -// EthernetPHYRead and EthernetPHYWrite. -// -//***************************************************************************** -#define PHY_MR0 0 // Control -#define PHY_MR1 1 // Status -#define PHY_MR2 2 // PHY Identifier 1 -#define PHY_MR3 3 // PHY Identifier 2 -#define PHY_MR4 4 // Auto-Neg. Advertisement -#define PHY_MR5 5 // Auto-Neg. Link Partner Ability -#define PHY_MR6 6 // Auto-Neg. Expansion - // 7-15 Reserved/Not Implemented -#define PHY_MR16 16 // Vendor Specific -#define PHY_MR17 17 // Interrupt Control/Status -#define PHY_MR18 18 // Diagnostic Register -#define PHY_MR19 19 // Transceiver Control - // 20-22 Reserved -#define PHY_MR23 23 // LED Configuration Register -#define PHY_MR24 24 // MDI/MDIX Control Register - // 25-31 Reserved/Not Implemented - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR0 register -// -//***************************************************************************** -#define PHY_MR0_RESET 0x8000 // Reset the PHY -#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback -#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection -#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T -#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T -#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable -#define PHY_MR0_PWRDN 0x0800 // Power Down -#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation -#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex -#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode -#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR1 register -// -//***************************************************************************** -#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete -#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected -#define PHY_MR1_LINK 0x0004 // Link Established -#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR17 register -// -//***************************************************************************** -#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt -#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int. -#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int. -#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt -#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt -#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int. - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR18 register -// -//***************************************************************************** -#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed -#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated -#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated -#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated -#define PHY_MR18_RATE 0x0400 // Rate Negotiated -#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T -#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR23 register -// -//***************************************************************************** -#define PHY_MR23_LED1 0x00f0 // LED1 Configuration -#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status -#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity -#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity -#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity -#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity -#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity -#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity -#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity -#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity -#define PHY_MR23_LED0 0x000f // LED0 Configuration -#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status -#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity -#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity -#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity -#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity -#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity -#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity -#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity -#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR24 register -// -//***************************************************************************** -#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration -#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough -#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - big endian/little endian byte swapping macros for -// 32-bit (long) values -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - big endian/little endian byte swapping macros for -// 16-bit (short) values -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/libdriver.a b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/libdriver.a deleted file mode 100644 index b5de5a193bc316196a75daed3f28ddb1a0d16b1a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 88936 zcmeFa4Pafxc_uvP-YZ#_t}R&-ARA#{OESpVxWYEXfRkM7+Sfla*s)DQTG~j+0ttkr zNHRZ38e~jb5@?pi?3TnyOB=SEHfbvZ-lc7*RZMsJ653Br(v~D7aZ-Y)p!;1BK@>y7 zKF`d&=gb*h#ZGDa(VvmdJ@dZrGw=MKIWzB>GiT}gj)BhZca{HKChji2cwNh7>)vtc zrI%$gEn4LMW-{+seX(I=+RK#+-m6sozJJ+wdj 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-//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.c b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.c deleted file mode 100644 index e68b143fa..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.c +++ /dev/null @@ -1,670 +0,0 @@ -//***************************************************************************** -// -// ustdlib.c - Simple standard library functions. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -#include -#include -#include "debug.h" - -//***************************************************************************** -// -//! \addtogroup utilities_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A mapping from an integer between 0 and 15 to its ASCII character -// equivalent. -// -//***************************************************************************** -static const char * const g_pcHex = "0123456789abcdef"; - -//***************************************************************************** -// -//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. -//! -//! \param pcBuf points to the buffer where the converted string is stored. -//! \param ulSize is the size of the buffer. -//! \param pcString is the format string. -//! \param vaArgP is the list of optional arguments, which depend on the -//! contents of the format string. -//! -//! This function is very similar to the C library vsnprintf() -//! function. Only the following formatting characters are supported: -//! -//! - \%c to print a character -//! - \%d to print a decimal value -//! - \%s to print a string -//! - \%u to print an unsigned decimal value -//! - \%x to print a hexadecimal value using lower case letters -//! - \%X to print a hexadecimal value using lower case letters (not upper case -//! letters as would typically be used) -//! - \%\% to print out a \% character -//! -//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% -//! and the format character, which specifies the minimum number of characters -//! to use for that value; if preceeded by a 0 then the extra characters will -//! be filled with zeros instead of spaces. For example, ``\%8d'' will use -//! eight characters to print the decimal value with spaces added to reach -//! eight; ``\%08d'' will use eight characters as well but will add zeros -//! instead of spaces. -//! -//! The type of the arguments after \b pcString must match the requirements of -//! the format string. For example, if an integer was passed where a string -//! was expected, an error of some kind will most likely occur. -//! -//! The \b ulSize parameter limits the number of characters that will be -//! stored in the buffer pointed to by \b pcBuf to prevent the possibility -//! of a buffer overflow. The buffer size should be large enough to hold -//! the expected converted output string, including the null termination -//! character. -//! -//! The function will return the number of characters that would be -//! converted as if there were no limit on the buffer size. Therefore -//! it is possible for the function to return a count that is greater than -//! the specified buffer size. If this happens, it means that the output -//! was truncated. -//! -//! \return the number of characters that were to be stored, not including -//! the NULL termination character, regardless of space in the buffer. -// -//***************************************************************************** -int -uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, - va_list vaArgP) -{ - unsigned long ulIdx, ulValue, ulCount, ulBase; - char *pcStr, cFill; - int iConvertCount = 0; - - // - // Check the arguments. - // - ASSERT(pcString != 0); - ASSERT(pcBuf != 0); - ASSERT(ulSize != 0); - - // - // Adjust buffer size limit to allow one space for null termination. - // - if(ulSize) - { - ulSize--; - } - - // - // Initialize the count of characters converted. - // - iConvertCount = 0; - - // - // Loop while there are more characters in the format string. - // - while(*pcString) - { - // - // Find the first non-% character, or the end of the string. - // - for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0'); - ulIdx++) - { - } - - // - // Write this portion of the string to the output buffer. If - // there are more characters to write than there is space in the - // buffer, then only write as much as will fit in the buffer. - // - if(ulIdx > ulSize) - { - strncpy(pcBuf, pcString, ulSize); - pcBuf += ulSize; - ulSize = 0; - } - else - { - strncpy(pcBuf, pcString, ulIdx); - pcBuf += ulIdx; - ulSize -= ulIdx; - } - - // - // Update the conversion count. This will be the number of - // characters that should have been written, even if there was - // not room in the buffer. - // - iConvertCount += ulIdx; - - // - // Skip the portion of the format string that was written. - // - pcString += ulIdx; - - // - // See if the next character is a %. - // - if(*pcString == '%') - { - // - // Skip the %. - // - pcString++; - - // - // Set the digit count to zero, and the fill character to space - // (i.e. to the defaults). - // - ulCount = 0; - cFill = ' '; - - // - // It may be necessary to get back here to process more characters. - // Goto's aren't pretty, but effective. I feel extremely dirty for - // using not one but two of the beasts. - // -again: - - // - // Determine how to handle the next character. - // - switch(*pcString++) - { - // - // Handle the digit characters. - // - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - // - // If this is a zero, and it is the first digit, then the - // fill character is a zero instead of a space. - // - if((pcString[-1] == '0') && (ulCount == 0)) - { - cFill = '0'; - } - - // - // Update the digit count. - // - ulCount *= 10; - ulCount += pcString[-1] - '0'; - - // - // Get the next character. - // - goto again; - } - - // - // Handle the %c command. - // - case 'c': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Copy the character to the output buffer, if - // there is room. Update the buffer size remaining. - // - if(ulSize != 0) - { - *pcBuf++ = (char)ulValue; - ulSize--; - } - - // - // Update the conversion count. - // - iConvertCount++; - - // - // This command has been handled. - // - break; - } - - // - // Handle the %d command. - // - case 'd': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // If the value is negative, make it positive and stick a - // minus sign in the beginning of the buffer. - // - if((long)ulValue < 0) - { - ulValue = -(long)ulValue; - - if(ulSize != 0) - { - *pcBuf++ = '-'; - ulSize--; - } - - // - // Update the conversion count. - // - iConvertCount++; - } - - // - // Set the base to 10. - // - ulBase = 10; - - // - // Convert the value to ASCII. - // - goto convert; - } - - // - // Handle the %s command. - // - case 's': - { - // - // Get the string pointer from the varargs. - // - pcStr = va_arg(vaArgP, char *); - - // - // Determine the length of the string. - // - for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) - { - } - - // - // Copy the string to the output buffer. Only copy - // as much as will fit in the buffer. Update the - // output buffer pointer and the space remaining. - // - if(ulIdx > ulSize) - { - strncpy(pcBuf, pcStr, ulSize); - pcBuf += ulSize; - ulSize = 0; - } - else - { - strncpy(pcBuf, pcStr, ulIdx); - pcBuf += ulIdx; - ulSize -= ulIdx; - } - - // - // Update the conversion count. This will be the number of - // characters that should have been written, even if there - // was not room in the buffer. - // - iConvertCount += ulIdx; - - // - // - // This command has been handled. - // - break; - } - - // - // Handle the %u command. - // - case 'u': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Set the base to 10. - // - ulBase = 10; - - // - // Convert the value to ASCII. - // - goto convert; - } - - // - // Handle the %x and %X commands. Note that they are treated - // identically; i.e. %X will use lower case letters for a-f - // instead of the upper case letters is should use. - // - case 'x': - case 'X': - { - // - // Get the value from the varargs. - // - ulValue = va_arg(vaArgP, unsigned long); - - // - // Set the base to 16. - // - ulBase = 16; - - // - // Determine the number of digits in the string version of - // the value. - // -convert: - for(ulIdx = 1; - (((ulIdx * ulBase) <= ulValue) && - (((ulIdx * ulBase) / ulBase) == ulIdx)); - ulIdx *= ulBase, ulCount--) - { - } - - // - // Provide additional padding at the beginning of the - // string conversion if needed. - // - if((ulCount > 1) && (ulCount < 16)) - { - for(ulCount--; ulCount; ulCount--) - { - // - // Copy the character to the output buffer if - // there is room. - // - if(ulSize != 0) - { - *pcBuf++ = cFill; - ulSize--; - } - - // - // Update the conversion count. - // - iConvertCount++; - } - } - - // - // Convert the value into a string. - // - for(; ulIdx; ulIdx /= ulBase) - { - // - // Copy the character to the output buffer if - // there is room. - // - if(ulSize != 0) - { - *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase]; - ulSize--; - } - - // - // Update the conversion count. - // - iConvertCount++; - } - - // - // This command has been handled. - // - break; - } - - // - // Handle the %% command. - // - case '%': - { - // - // Simply write a single %. - // - if(ulSize != 0) - { - *pcBuf++ = pcString[-1]; - ulSize--; - } - - // - // Update the conversion count. - // - iConvertCount++; - - // - // This command has been handled. - // - break; - } - - // - // Handle all other commands. - // - default: - { - // - // Indicate an error. - // - if(ulSize >= 5) - { - strncpy(pcBuf, "ERROR", 5); - pcBuf += 5; - ulSize -= 5; - } - else - { - strncpy(pcBuf, "ERROR", ulSize); - pcBuf += ulSize; - ulSize = 0; - } - - // - // Update the conversion count. - // - iConvertCount += 5; - - // - // This command has been handled. - // - break; - } - } - } - } - - // - // Null terminate the string in the buffer. - // - *pcBuf = 0; - return(iConvertCount); -} - -//***************************************************************************** -// -//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. -//! -//! \param pcBuf is the buffer where the converted string is stored. -//! \param pcString is the format string. -//! \param ... are the optional arguments, which depend on the contents of the -//! format string. -//! -//! This function is very similar to the C library sprintf() function. -//! Only the following formatting characters are supported: -//! -//! - \%c to print a character -//! - \%d to print a decimal value -//! - \%s to print a string -//! - \%u to print an unsigned decimal value -//! - \%x to print a hexadecimal value using lower case letters -//! - \%X to print a hexadecimal value using lower case letters (not upper case -//! letters as would typically be used) -//! - \%\% to print out a \% character -//! -//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% -//! and the format character, which specifies the minimum number of characters -//! to use for that value; if preceeded by a 0 then the extra characters will -//! be filled with zeros instead of spaces. For example, ``\%8d'' will use -//! eight characters to print the decimal value with spaces added to reach -//! eight; ``\%08d'' will use eight characters as well but will add zeros -//! instead of spaces. -//! -//! The type of the arguments after \b pcString must match the requirements of -//! the format string. For example, if an integer was passed where a string -//! was expected, an error of some kind will most likely occur. -//! -//! The caller must ensure that the buffer pcBuf is large enough to hold the -//! entire converted string, including the null termination character. -//! -//! \return The count of characters that were written to the output buffer, -//! not including the NULL termination character. -// -//***************************************************************************** -int -usprintf(char *pcBuf, const char *pcString, ...) -{ - va_list vaArgP; - int iRet; - - // - // Start the varargs processing. - // - va_start(vaArgP, pcString); - - // - // Call vsnprintf to perform the conversion. Use a - // large number for the buffer size. - // - iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP); - - // - // End the varargs processing. - // - va_end(vaArgP); - - // - // Return the conversion count. - // - return(iRet); -} - -//***************************************************************************** -// -//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. -//! -//! \param pcBuf is the buffer where the converted string is stored. -//! \param ulSize is the size of the buffer. -//! \param pcString is the format string. -//! \param ... are the optional arguments, which depend on the contents of the -//! format string. -//! -//! This function is very similar to the C library sprintf() function. -//! Only the following formatting characters are supported: -//! -//! - \%c to print a character -//! - \%d to print a decimal value -//! - \%s to print a string -//! - \%u to print an unsigned decimal value -//! - \%x to print a hexadecimal value using lower case letters -//! - \%X to print a hexadecimal value using lower case letters (not upper case -//! letters as would typically be used) -//! - \%\% to print out a \% character -//! -//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% -//! and the format character, which specifies the minimum number of characters -//! to use for that value; if preceeded by a 0 then the extra characters will -//! be filled with zeros instead of spaces. For example, ``\%8d'' will use -//! eight characters to print the decimal value with spaces added to reach -//! eight; ``\%08d'' will use eight characters as well but will add zeros -//! instead of spaces. -//! -//! The type of the arguments after \b pcString must match the requirements of -//! the format string. For example, if an integer was passed where a string -//! was expected, an error of some kind will most likely occur. -//! -//! The function will copy at most \b ulSize - 1 characters into the -//! buffer \b pcBuf. One space is reserved in the buffer for the null -//! termination character. -//! -//! The function will return the number of characters that would be -//! converted as if there were no limit on the buffer size. Therefore -//! it is possible for the function to return a count that is greater than -//! the specified buffer size. If this happens, it means that the output -//! was truncated. -//! -//! \return the number of characters that were to be stored, not including -//! the NULL termination character, regardless of space in the buffer. -// -//***************************************************************************** -int -usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...) -{ -int iRet; - - va_list vaArgP; - - // - // Start the varargs processing. - // - va_start(vaArgP, pcString); - - // - // Call vsnprintf to perform the conversion. - // - iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP); - - // - // End the varargs processing. - // - va_end(vaArgP); - - // - // Return the conversion count. - // - return(iRet); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.h deleted file mode 100644 index 811170cdc..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/ustdlib.h +++ /dev/null @@ -1,48 +0,0 @@ -//***************************************************************************** -// -// uartstdlib.h - Prototypes for simple standard library functions. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// -//***************************************************************************** - -#ifndef __UARTSTDLIB_H__ -#define __UARTSTDLIB_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern int usprintf(char *, const char *pcString, ...); -extern int usnprintf(char *pcBuf, unsigned long ulSize, - const char *pcString, ...); - -#ifdef __cplusplus -} -#endif - -#endif // __UARTSTDLIB_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_GCC/Makefile b/Demo/CORTEX_LM3S6965_GCC/Makefile deleted file mode 100644 index e2460af75..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/Makefile +++ /dev/null @@ -1,101 +0,0 @@ -#****************************************************************************** -# -# Makefile - Rules for building the driver library and examples. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -include makedefs - -RTOS_SOURCE_DIR=../../Source -DEMO_SOURCE_DIR=../Common/Minimal -UIP_SOURCE_DIR=../Common/ethernet/uIP/uip-1.0/uip - -CFLAGS+=-I LuminaryDrivers -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ${UIP_SOURCE_DIR} -I webserver -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= -D PACK_STRUCT_END=__attribute\(\(packed\)\) -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -D sprintf=usprintf -D snprintf=usnprintf -D printf=uipprintf - -VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:${UIP_SOURCE_DIR}:init:LuminaryDrivers:ParTest:webserver - -OBJS=${COMPILER}/main.o \ - ${COMPILER}/list.o \ - ${COMPILER}/queue.o \ - ${COMPILER}/tasks.o \ - ${COMPILER}/port.o \ - ${COMPILER}/heap_2.o \ - ${COMPILER}/BlockQ.o \ - ${COMPILER}/PollQ.o \ - ${COMPILER}/integer.o \ - ${COMPILER}/semtest.o \ - ${COMPILER}/osram128x64x4.o \ - ${COMPILER}/ustdlib.o \ - ${COMPILER}/blocktim.o \ - ${COMPILER}/death.o \ - ${COMPILER}/ParTest.o \ - ${COMPILER}/timertest.o \ - ${COMPILER}/emac.o \ - ${COMPILER}/http-strings.o \ - ${COMPILER}/httpd-cgi.o \ - ${COMPILER}/httpd-fs.o \ - ${COMPILER}/httpd.o \ - ${COMPILER}/psock.o \ - ${COMPILER}/timer.o \ - ${COMPILER}/uip.o \ - ${COMPILER}/uip_arp.o \ - ${COMPILER}/uIP_Task.o - -INIT_OBJS= ${COMPILER}/startup.o - -LIBS= LuminaryDrivers/libdriver.a - - -# -# The default rule, which causes init to be built. -# -all: ${COMPILER} \ - ${COMPILER}/RTOSDemo.axf \ - -# -# The rule to clean out all the build products -# - -clean: - @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf - -# -# The rule to create the target directory -# -${COMPILER}: - @mkdir ${COMPILER} - -${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} -SCATTER_RTOSDemo=standalone.ld -ENTRY_RTOSDemo=ResetISR - -# -# -# Include the automatically generated dependency files. -# --include ${wildcard ${COMPILER}/*.d} __dummy__ - - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/ParTest/ParTest.c b/Demo/CORTEX_LM3S6965_GCC/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S6965_GCC/bitmap.h b/Demo/CORTEX_LM3S6965_GCC/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, -0x00 }; - -#define bmpBITMAP_HEIGHT 50 -#define bmpBITMAP_WIDTH 128 - -#endif diff --git a/Demo/CORTEX_LM3S6965_GCC/lcd_message.h b/Demo/CORTEX_LM3S6965_GCC/lcd_message.h deleted file mode 100644 index ced7a1dbc..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/lcd_message.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef LCD_MESSAGE_H -#define LCD_MESSAGE_H - -typedef struct -{ - char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S6965_GCC/main.c b/Demo/CORTEX_LM3S6965_GCC/main.c deleted file mode 100644 index 3645a81f1..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/main.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - * "uIP" task - This is the task that handles the uIP stack. All TCP/IP - * processing is performed in this task. - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* Size of the stack allocated to the uIP task. */ -#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that handles the uIP stack. All TCP/IP processing is performed in - * this task. - */ -extern void vuIP_Task( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Create the uIP task. */ - xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - #ifdef __ICCARM__ - vSetupTimer(); - #endif - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable/Reset the Ethernet Controller */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); - SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - #ifdef __ICCARM__ - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - #else - sprintf( cPassMessage, "PASS" ); - #endif - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S6965_GCC/makedefs b/Demo/CORTEX_LM3S6965_GCC/makedefs deleted file mode 100644 index efd7530d4..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/makedefs +++ /dev/null @@ -1,208 +0,0 @@ -#****************************************************************************** -# -# makedefs - Definitions common to all makefiles. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -#****************************************************************************** -# -# Get the operating system name. If this is Cygwin, the .d files will be -# munged to convert c: into /cygdrive/c so that "make" will be happy with the -# auto-generated dependencies. -# -#****************************************************************************** -os:=${shell uname -s} - -#****************************************************************************** -# -# The compiler to be used. -# -#****************************************************************************** -ifndef COMPILER -COMPILER=gcc -endif - -#****************************************************************************** -# -# The debugger to be used. -# -#****************************************************************************** -ifndef DEBUGGER -DEBUGGER=gdb -endif - -#****************************************************************************** -# -# Definitions for using GCC. -# -#****************************************************************************** -ifeq (${COMPILER}, gcc) - -# -# The command for calling the compiler. -# -CC=arm-stellaris-eabi-gcc - -# -# The flags passed to the assembler. -# -AFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -MD - -# -# The flags passed to the compiler. -# -CFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -O2 \ - -MD - -# -# The command for calling the library archiver. -# -AR=arm-stellaris-eabi-ar - -# -# The command for calling the linker. -# -LD=arm-stellaris-eabi-ld - -# -# The flags passed to the linker. -# -LDFLAGS= -Map gcc/out.map - -# -# Get the location of libgcc.a from the GCC front-end. -# -LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} - -# -# Get the location of libc.a from the GCC front-end. -# -LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} - -# -# The command for extracting images from the linked executables. -# -OBJCOPY=arm-stellaris-eabi-objcopy - -endif - -#****************************************************************************** -# -# Tell the compiler to include debugging information if the DEBUG environment -# variable is set. -# -#****************************************************************************** -ifdef DEBUG -CFLAGS += -g -endif - -#****************************************************************************** -# -# The rule for building the object file from each C source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.c - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi - @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} -ifeq (${COMPILER}, rvds) - @mv -f ${notdir ${@:.o=.d}} ${COMPILER} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for building the object file from each assembly source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.S - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi -ifeq (${COMPILER}, rvds) - @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} - @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} - @rm ${@:.o=_.S} - @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} - @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} - @rm ${notdir ${<:.S=.d}} -endif -ifeq (${COMPILER}, gcc) - @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for creating an object library. -# -#****************************************************************************** -${COMPILER}/%.a: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " AR ${@}"; \ - else \ - echo ${AR} -cr ${@} ${^}; \ - fi - @${AR} -cr ${@} ${^} - -#****************************************************************************** -# -# The rule for linking the application. -# -#****************************************************************************** -${COMPILER}/%.axf: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " LD ${@}"; \ - fi -ifeq (${COMPILER}, gcc) - @if [ 'x${VERBOSE}' != x ]; \ - then \ - echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}'; \ - fi - @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}' - @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} -endif diff --git a/Demo/CORTEX_LM3S6965_GCC/standalone.ld b/Demo/CORTEX_LM3S6965_GCC/standalone.ld deleted file mode 100644 index 35111445b..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/standalone.ld +++ /dev/null @@ -1,60 +0,0 @@ -/****************************************************************************** - * - * standalone.ld - Linker script for applications using startup.c and - * DriverLib. - * - * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. - * - * Software License Agreement - * - * Luminary Micro, Inc. (LMI) is supplying this software for use solely and - * exclusively on LMI's microcontroller products. - * - * The software is owned by LMI and/or its suppliers, and is protected under - * applicable copyright laws. All rights are reserved. Any use in violation - * of the foregoing restrictions may subject the user to criminal sanctions - * under applicable laws, as well as to civil liability for the breach of the - * terms and conditions of this license. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 1392 of the Stellaris Peripheral Driver Library. - * - *****************************************************************************/ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - *(.rodata*) - _etext = .; - } > FLASH - - .data : AT (ADDR(.text) + SIZEOF(.text)) - { - _data = .; - *(vtable) - *(.data*) - _edata = .; - } > SRAM - - .bss : - { - _bss = .; - *(.bss*) - *(COMMON) - _ebss = .; - } > SRAM -} diff --git a/Demo/CORTEX_LM3S6965_GCC/startup.c b/Demo/CORTEX_LM3S6965_GCC/startup.c deleted file mode 100644 index 6fec1cf34..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/startup.c +++ /dev/null @@ -1,248 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1392 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vEMAC_ISR(void); -extern void Timer0IntHandler(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - Timer0IntHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // Quadrature Encoder 1 - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - 0, // Reserved - vEMAC_ISR, // Ethernet - IntDefaultHandler // Hibernate -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied main() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_bss; pulDest < &_ebss; ) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// A dummy printf function to satisfy the calls to printf from uip. This -// avoids pulling in the run-time library. -// -//***************************************************************************** -int -uipprintf(const char *fmt, ...) -{ - return(0); -} - diff --git a/Demo/CORTEX_LM3S6965_GCC/timertest.c b/Demo/CORTEX_LM3S6965_GCC/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/Makefile.webserver b/Demo/CORTEX_LM3S6965_GCC/webserver/Makefile.webserver deleted file mode 100644 index f38c47a72..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/Makefile.webserver +++ /dev/null @@ -1 +0,0 @@ -APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/clock-arch.h b/Demo/CORTEX_LM3S6965_GCC/webserver/clock-arch.h deleted file mode 100644 index cde657b62..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include "FreeRTOS.h" - -typedef unsigned long clock_time_t; -#define CLOCK_CONF_SECOND configTICK_RATE_HZ - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/emac.c b/Demo/CORTEX_LM3S6965_GCC/webserver/emac.c deleted file mode 100644 index b5f394442..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/emac.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "Semphr.h" -#include "task.h" - -/* Demo includes. */ -#include "EMAC.h" - -/* uIP includes. */ -#include "uip.h" - -/* Hardware library includes. */ -#include "hw_types.h" -#include "hw_memmap.h" -#include "hw_ints.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "interrupt.h" - -#define emacNUM_RX_BUFFERS 5 -#define emacFRAM_SIZE_BYTES 2 -#define macNEGOTIATE_DELAY 2000 -#define macWAIT_SEND_TIME ( 10 ) - -/* The task that handles the MAC peripheral. This is created at a high -priority and is effectively a deferred interrupt handler. The peripheral -handling is deferred to a task to prevent the entire FIFO having to be read -from within an ISR. */ -void vMACHandleTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used to wake the uIP task when data arrives. */ -xSemaphoreHandle xEMACSemaphore = NULL; - -/* The semaphore used to wake the interrupt handler task. The peripheral -is processed at the task level to prevent the need to read the entire FIFO from -within the ISR itself. */ -xSemaphoreHandle xMACInterruptSemaphore = NULL; - -/* The buffer used by the uIP stack. In this case the pointer is used to -point to one of the Rx buffers. */ -unsigned portCHAR *uip_buf; - -/* Buffers into which Rx data is placed. */ -static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; - -/* The length of the data within each of the Rx buffers. */ -static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; - -/* Used to keep a track of the number of bytes to transmit. */ -static unsigned portLONG ulNextTxSpace; - -/*-----------------------------------------------------------*/ - -portBASE_TYPE vInitEMAC( void ) -{ -unsigned long ulTemp; -portBASE_TYPE xReturn; - - /* Ensure all interrupts are disabled. */ - EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); - - /* Clear any interrupts that were already pending. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Initialise the MAC and connect. */ - EthernetInit( ETH_BASE ); - EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); - EthernetEnable( ETH_BASE ); - - /* Mark each Rx buffer as empty. */ - for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) - { - ulRxLength[ ulTemp ] = 0; - } - - /* Create the queue and task used to defer the MAC processing to the - task level. */ - vSemaphoreCreateBinary( xMACInterruptSemaphore ); - xSemaphoreTake( xMACInterruptSemaphore, 0 ); - xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - vTaskDelay( macNEGOTIATE_DELAY ); - - /* We are only interested in Rx interrupts. */ - IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_ETH ); - EthernetIntEnable(ETH_BASE, ETH_INT_RX); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) -{ -static unsigned long ulNextRxBuffer = 0; -unsigned int iLen; - - iLen = ulRxLength[ ulNextRxBuffer ]; - - if( iLen != 0 ) - { - /* Leave room for the size at the start of the buffer. */ - uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - - ulRxLength[ ulNextRxBuffer ] = 0; - - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - } - - return iLen; -} -/*-----------------------------------------------------------*/ - -void vInitialiseSend( void ) -{ - /* Set the index to the first byte to send - skipping over the size - bytes. */ - ulNextTxSpace = 2; -} -/*-----------------------------------------------------------*/ - -void vIncrementTxLength( unsigned portLONG ulLength ) -{ - ulNextTxSpace += ulLength; -} -/*-----------------------------------------------------------*/ - -void vSendBufferToMAC( void ) -{ -unsigned long *pulSource; -unsigned portSHORT * pus; -unsigned portLONG ulNextWord; - - /* Locate the data to be send. */ - pus = ( unsigned portSHORT * ) uip_buf; - - /* Add in the size of the data. */ - pus--; - *pus = ulNextTxSpace; - - /* Wait for data to be sent if there is no space immediately. */ - while( !EthernetSpaceAvail( ETH_BASE ) ) - { - vTaskDelay( macWAIT_SEND_TIME ); - } - - pulSource = ( unsigned portLONG * ) pus; - - for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) - { - HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; - pulSource++; - } - - /* Go. */ - HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; -} -/*-----------------------------------------------------------*/ - -void vEMAC_ISR( void ) -{ -portBASE_TYPE xSwitchRequired = pdFALSE; -unsigned portLONG ulTemp; - - /* Clear the interrupt. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Was it an Rx interrupt? */ - if( ulTemp & ETH_INT_RX ) - { - xSwitchRequired = pdTRUE; - xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE ); - EthernetIntDisable( ETH_BASE, ETH_INT_RX ); - } - - /* Switch to the uIP task. */ - portEND_SWITCHING_ISR( xSwitchRequired ); -} -/*-----------------------------------------------------------*/ - -void vMACHandleTask( void *pvParameters ) -{ -unsigned long ulLen = 0, i; -unsigned portLONG ulLength, ulInt; -unsigned long *pulBuffer; -static unsigned portLONG ulNextRxBuffer = 0; -portBASE_TYPE xSwitchRequired = pdFALSE; - - for( ;; ) - { - /* Wait for something to do. */ - xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); - - while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) - { - ulLength = HWREG( ETH_BASE + MAC_O_DATA ); - - /* Leave room at the start of the buffer for the size. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - *pulBuffer = ( ulLength >> 16 ); - - /* Get the size of the data. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); - ulLength &= 0xFFFF; - - if( ulLength > 4 ) - { - ulLength -= 4; - - if( ulLength >= UIP_BUFSIZE ) - { - /* The data won't fit in our buffer. Ensure we don't - try to write into the buffer. */ - ulLength = 0; - } - - /* Read out the data into our buffer. */ - for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) - { - *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); - pulBuffer++; - } - - /* Store the length of the data into the separate array. */ - ulRxLength[ ulNextRxBuffer ] = ulLength; - - /* Use the next buffer the next time through. */ - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - - /* Ensure the uIP task is not blocked as data has arrived. */ - xSemaphoreGive( xEMACSemaphore ); - } - } - - EthernetIntEnable( ETH_BASE, ETH_INT_RX ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/emac.h b/Demo/CORTEX_LM3S6965_GCC/webserver/emac.h deleted file mode 100644 index a49b59828..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/emac.h +++ /dev/null @@ -1,322 +0,0 @@ -/*---------------------------------------------------------------------------- - * LPC2378 Ethernet Definitions - *---------------------------------------------------------------------------- - * Name: EMAC.H - * Purpose: Philips LPC2378 EMAC hardware definitions - *---------------------------------------------------------------------------- - * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#ifndef __EMAC_H -#define __EMAC_H - -/* MAC address definition. The MAC address must be unique on the network. */ -#define emacETHADDR0 0 -#define emacETHADDR1 0xbd -#define emacETHADDR2 0x33 -#define emacETHADDR3 0x02 -#define emacETHADDR4 0x64 -#define emacETHADDR5 0x24 - - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ -#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ - -/* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE 0x7FE00000 -#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) -#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) -#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) -#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) -#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) - -/* RX and TX descriptor and status definitions. */ -#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) -#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) -#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) -#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) -#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) -#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) -#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) -#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) -#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* MAC Configuration Register 1 */ -#define MAC1_REC_EN 0x00000001 /* Receive Enable */ -#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ -#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ -#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ -#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ -#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ -#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ -#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ -#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ -#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ -#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ -#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ -#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ -#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ -#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ -#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ -#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ -#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ -#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ -#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ -#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ -#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ -#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ -#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ - -/* Non Back-to-Back Inter-Packet-Gap Register */ -#define IPGR_DEF 0x00000012 /* Recommended value */ - -/* Collision Window/Retry Register */ -#define CLRT_DEF 0x0000370F /* Default value */ - -/* PHY Support Register */ -#undef SUPP_SPEED /* Remove compiler warning. */ -#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ -#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ - -/* Test Register */ -#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ -#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ -#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ - -/* MII Management Configuration Register */ -#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ -#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ -#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ -#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ - -/* MII Management Command Register */ -#undef MCMD_READ /* Remove compiler warning. */ -#define MCMD_READ 0x00000001 /* MII Read */ -#undef MCMD_SCAN /* Remove compiler warning. */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#undef MIND_BUSY /* Remove compiler warning. */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* Command Register */ -#define CR_RX_EN 0x00000001 /* Enable Receive */ -#define CR_TX_EN 0x00000002 /* Enable Transmit */ -#define CR_REG_RES 0x00000008 /* Reset Host Registers */ -#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ -#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ -#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ -#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ -#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ -#define CR_RMII 0x00000200 /* Reduced MII Interface */ -#define CR_FULL_DUP 0x00000400 /* Full Duplex */ - -/* Status Register */ -#define SR_RX_EN 0x00000001 /* Enable Receive */ -#define SR_TX_EN 0x00000002 /* Enable Transmit */ - -/* Transmit Status Vector 0 Register */ -#define TSV0_CRC_ERR 0x00000001 /* CRC error */ -#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ -#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ -#define TSV0_MCAST 0x00000010 /* Multicast Destination */ -#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ -#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ -#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ -#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ -#define TSV0_GIANT 0x00000400 /* Giant Frame */ -#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ -#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ -#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ -#define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ -#define TSV0_VLAN 0x80000000 /* VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ -#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ -#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ -#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ -#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ -#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ -#define RSV_CRC_ERR 0x00100000 /* CRC Error */ -#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ -#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ -#define RSV_REC_OK 0x00800000 /* Frame Received OK */ -#define RSV_MCAST 0x01000000 /* Multicast Frame */ -#define RSV_BCAST 0x02000000 /* Broadcast Frame */ -#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ -#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ -#define RSV_PAUSE 0x10000000 /* Pause Frame */ -#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ -#define RSV_VLAN 0x40000000 /* VLAN Frame */ - -/* Flow Control Counter Register */ -#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ -#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ - -/* Flow Control Status Register */ -#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ - -/* Receive Filter Control Register */ -#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ -#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ -#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ -#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ -#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ -#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ -#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ -#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ -#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ -#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ -#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ -#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ -#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ -#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ -#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ - -/* Interrupt Status/Enable/Clear/Set Registers */ -#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ -#define INT_RX_ERR 0x00000002 /* Receive Error */ -#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ -#define INT_RX_DONE 0x00000008 /* Receive Done */ -#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ -#define INT_TX_ERR 0x00000020 /* Transmit Error */ -#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ -#define INT_TX_DONE 0x00000080 /* Transmit Done */ -#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ -#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ - -/* Power Down Register */ -#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ - -/* RX Descriptor Control Word */ -#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ -#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ -#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define RINFO_SIZE 0x000007FF /* Data size in bytes */ -#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ -#define RINFO_VLAN 0x00080000 /* VLAN Frame */ -#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ -#define RINFO_MCAST 0x00200000 /* Multicast Frame */ -#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ -#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ -#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ -#define RINFO_LEN_ERR 0x02000000 /* Length Error */ -#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ -#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ -#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ -#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ -#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ - RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) - -/* TX Descriptor Control Word */ -#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ -#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ -#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ -#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ -#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ -#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ -#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ -#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ -#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ -#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ -#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ -#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier */ - -// prototypes -portBASE_TYPE vInitEMAC(void); -unsigned short ReadFrameBE_EMAC(void); -void vIncrementTxLength(unsigned long ulLength); -void CopyFromFrame_EMAC(void *Dest, unsigned short Size); -void DummyReadFrame_EMAC(unsigned short Size); -unsigned short StartReadFrame(void); -void EndReadFrame(void); -unsigned int CheckFrameReceived(void); -void vInitialiseSend(void); -unsigned int Rdy4Tx(void); -void vSendBufferToMAC(void); -void vEMACWaitForInput( void ); -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); - - -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings b/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings deleted file mode 100644 index 0d3c30cdd..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings +++ /dev/null @@ -1,35 +0,0 @@ -http_http "http://" -http_200 "200 " -http_301 "301 " -http_302 "302 " -http_get "GET " -http_10 "HTTP/1.0" -http_11 "HTTP/1.1" -http_content_type "content-type: " -http_texthtml "text/html" -http_location "location: " -http_host "host: " -http_crnl "\r\n" -http_index_html "/index.html" -http_404_html "/404.html" -http_referer "Referer:" -http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_content_type_plain "Content-type: text/plain\r\n\r\n" -http_content_type_html "Content-type: text/html\r\n\r\n" -http_content_type_css "Content-type: text/css\r\n\r\n" -http_content_type_text "Content-type: text/text\r\n\r\n" -http_content_type_png "Content-type: image/png\r\n\r\n" -http_content_type_gif "Content-type: image/gif\r\n\r\n" -http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" -http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" -http_html ".html" -http_shtml ".shtml" -http_htm ".htm" -http_css ".css" -http_png ".png" -http_gif ".gif" -http_jpg ".jpg" -http_text ".txt" -http_txt ".txt" - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.c b/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.c deleted file mode 100644 index ef7a41c7d..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.c +++ /dev/null @@ -1,102 +0,0 @@ -const char http_http[8] = -/* "http://" */ -{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; -const char http_200[5] = -/* "200 " */ -{0x32, 0x30, 0x30, 0x20, }; -const char http_301[5] = -/* "301 " */ -{0x33, 0x30, 0x31, 0x20, }; -const char http_302[5] = -/* "302 " */ -{0x33, 0x30, 0x32, 0x20, }; -const char http_get[5] = -/* "GET " */ -{0x47, 0x45, 0x54, 0x20, }; -const char http_10[9] = -/* "HTTP/1.0" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; -const char http_11[9] = -/* "HTTP/1.1" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; -const char http_content_type[15] = -/* "content-type: " */ -{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; -const char http_texthtml[10] = -/* "text/html" */ -{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_location[11] = -/* "location: " */ -{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; -const char http_host[7] = -/* "host: " */ -{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; -const char http_crnl[3] = -/* "\r\n" */ -{0xd, 0xa, }; -const char http_index_html[12] = -/* "/index.html" */ -{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_404_html[10] = -/* "/404.html" */ -{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_referer[9] = -/* "Referer:" */ -{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; -const char http_header_200[84] = -/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_header_404[91] = -/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_content_type_plain[29] = -/* "Content-type: text/plain\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_html[28] = -/* "Content-type: text/html\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_css [27] = -/* "Content-type: text/css\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_text[28] = -/* "Content-type: text/text\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_png [28] = -/* "Content-type: image/png\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_gif [28] = -/* "Content-type: image/gif\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_jpg [29] = -/* "Content-type: image/jpeg\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_binary[43] = -/* "Content-type: application/octet-stream\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; -const char http_html[6] = -/* ".html" */ -{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_shtml[7] = -/* ".shtml" */ -{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_htm[5] = -/* ".htm" */ -{0x2e, 0x68, 0x74, 0x6d, }; -const char http_css[5] = -/* ".css" */ -{0x2e, 0x63, 0x73, 0x73, }; -const char http_png[5] = -/* ".png" */ -{0x2e, 0x70, 0x6e, 0x67, }; -const char http_gif[5] = -/* ".gif" */ -{0x2e, 0x67, 0x69, 0x66, }; -const char http_jpg[5] = -/* ".jpg" */ -{0x2e, 0x6a, 0x70, 0x67, }; -const char http_text[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; -const char http_txt[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.h b/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.h deleted file mode 100644 index acbe7e17f..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/http-strings.h +++ /dev/null @@ -1,34 +0,0 @@ -extern const char http_http[8]; -extern const char http_200[5]; -extern const char http_301[5]; -extern const char http_302[5]; -extern const char http_get[5]; -extern const char http_10[9]; -extern const char http_11[9]; -extern const char http_content_type[15]; -extern const char http_texthtml[10]; -extern const char http_location[11]; -extern const char http_host[7]; -extern const char http_crnl[3]; -extern const char http_index_html[12]; -extern const char http_404_html[10]; -extern const char http_referer[9]; -extern const char http_header_200[84]; -extern const char http_header_404[91]; -extern const char http_content_type_plain[29]; -extern const char http_content_type_html[28]; -extern const char http_content_type_css [27]; -extern const char http_content_type_text[28]; -extern const char http_content_type_png [28]; -extern const char http_content_type_gif [28]; -extern const char http_content_type_jpg [29]; -extern const char http_content_type_binary[43]; -extern const char http_html[6]; -extern const char http_shtml[7]; -extern const char http_htm[5]; -extern const char http_css[5]; -extern const char http_png[5]; -extern const char http_gif[5]; -extern const char http_jpg[5]; -extern const char http_text[5]; -extern const char http_txt[5]; diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.c b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.c deleted file mode 100644 index 803b771e6..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2006, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ - * - */ - -#include "uip.h" -#include "psock.h" -#include "httpd.h" -#include "httpd-cgi.h" -#include "httpd-fs.h" - -#include -#include - -HTTPD_CGI_CALL(file, "file-stats", file_stats); -HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); -HTTPD_CGI_CALL(net, "net-stats", net_stats); -HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); -HTTPD_CGI_CALL(io, "led-io", led_io ); - - -static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; - -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -httpd_cgifunction -httpd_cgi(char *name) -{ - const struct httpd_cgi_call **f; - - /* Find the matching name in the table, return the function. */ - for(f = calls; *f != NULL; ++f) { - if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { - return (*f)->function; - } - } - return nullfunction; -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_file_stats(void *arg) -{ - char *f = (char *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -static unsigned short -generate_tcp_stats(void *arg) -{ - struct uip_conn *conn; - struct httpd_state *s = (struct httpd_state *)arg; - - conn = &uip_conns[s->count]; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", - htons(conn->lport), - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & UIP_TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' '); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) -{ - - PSOCK_BEGIN(&s->sout); - - for(s->count = 0; s->count < UIP_CONNS; ++s->count) { - if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { - PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); - } - } - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_net_stats(void *arg) -{ - struct httpd_state *s = (struct httpd_state *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); -} - -static -PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - -#if UIP_STATISTICS - - for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); - ++s->count) { - PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); - } - -#endif /* UIP_STATISTICS */ - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -extern void vTaskList( signed char *pcWriteBuffer ); -static char cCountBuf[ 32 ]; -long lRefreshCount = 0; -static unsigned short -generate_rtos_stats(void *arg) -{ - lRefreshCount++; - sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); - vTaskList( uip_appdata ); - strcat( uip_appdata, cCountBuf ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - - -static -PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -char *pcStatus; -extern unsigned long uxParTestGetLED( unsigned long uxLED ); - -static unsigned short generate_io_state( void *arg ) -{ - if( uxParTestGetLED( 0 ) ) - { - pcStatus = "checked"; - } - else - { - pcStatus = ""; - } - - sprintf( uip_appdata, - "LED"\ - "

"\ - "", - pcStatus ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - -static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); - PSOCK_END(&s->sout); -} - -/** @} */ - - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.h b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.h deleted file mode 100644 index 7ae928321..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-cgi.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface header file - * \author - * Adam Dunkels - * - */ - - - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_CGI_H__ -#define __HTTPD_CGI_H__ - -#include "psock.h" -#include "httpd.h" - -typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); - -httpd_cgifunction httpd_cgi(char *name); - -struct httpd_cgi_call { - const char *name; - const httpd_cgifunction function; -}; - -/** - * \brief HTTPD CGI function declaration - * \param name The C variable name of the function - * \param str The string name of the function, used in the script file - * \param function A pointer to the function that implements it - * - * This macro is used for declaring a HTTPD CGI - * function. This function is then added to the list of - * HTTPD CGI functions with the httpd_cgi_add() function. - * - * \hideinitializer - */ -#define HTTPD_CGI_CALL(name, str, function) \ -static PT_THREAD(function(struct httpd_state *, char *)); \ -static const struct httpd_cgi_call name = {str, function} - -void httpd_cgi_init(void); -#endif /* __HTTPD_CGI_H__ */ - -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.c b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.c deleted file mode 100644 index dc4aef011..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ - -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-fsdata.h" - -#ifndef NULL -#define NULL 0 -#endif /* NULL */ - -#include "httpd-fsdata.c" - -#if HTTPD_FS_STATISTICS -static u16_t count[HTTPD_FS_NUMFILES]; -#endif /* HTTPD_FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -httpd_fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -httpd_fs_open(const char *name, struct httpd_fs_file *file) -{ -#if HTTPD_FS_STATISTICS - u16_t i = 0; -#endif /* HTTPD_FS_STATISTICS */ - struct httpd_fsdata_file_noconst *f; - - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#if HTTPD_FS_STATISTICS - ++count[i]; -#endif /* HTTPD_FS_STATISTICS */ - return 1; - } -#if HTTPD_FS_STATISTICS - ++i; -#endif /* HTTPD_FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_fs_init(void) -{ -#if HTTPD_FS_STATISTICS - u16_t i; - for(i = 0; i < HTTPD_FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* HTTPD_FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#if HTTPD_FS_STATISTICS -u16_t httpd_fs_count -(char *name) -{ - struct httpd_fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* HTTPD_FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.h b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.h deleted file mode 100644 index b594eea56..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FS_H__ -#define __HTTPD_FS_H__ - -#define HTTPD_FS_STATISTICS 1 - -struct httpd_fs_file { - char *data; - int len; -}; - -/* file must be allocated by caller and will be filled in - by the function. */ -int httpd_fs_open(const char *name, struct httpd_fs_file *file); - -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 -u16_t httpd_fs_count(char *name); -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ - -void httpd_fs_init(void); - -#endif /* __HTTPD_FS_H__ */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/404.html b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/404.html deleted file mode 100644 index 43e7f4cad..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/404.html +++ /dev/null @@ -1,8 +0,0 @@ - - -

-

404 - file not found

-

Go here instead.

-
- - \ No newline at end of file diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.html b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.html deleted file mode 100644 index 1d3bbeee1..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.html +++ /dev/null @@ -1,13 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -Loading index.shtml. Click here if not automatically redirected. - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.shtml b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.shtml deleted file mode 100644 index 1923ea762..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/index.shtml +++ /dev/null @@ -1,20 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Task statistics

-Page will refresh every 2 seconds.

-

Task          State  Priority  Stack	#
************************************************

-%! rtos-stats
-
- - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/io.shtml b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/io.shtml deleted file mode 100644 index 07554bb71..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/io.shtml +++ /dev/null @@ -1,28 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-LED and LCD IO
- -

- -Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". - - -

-

-%! led-io -

- -

-

- - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/stats.shtml b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/stats.shtml deleted file mode 100644 index d762f40d8..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/stats.shtml +++ /dev/null @@ -1,41 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Network statistics

- -
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
%! net-stats
-
- - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/tcp.shtml b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/tcp.shtml deleted file mode 100644 index 654d61f21..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fs/tcp.shtml +++ /dev/null @@ -1,21 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-
-

Network connections

-

- - -%! tcp-connections - - - - - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.c b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.c deleted file mode 100644 index a7fcfab5a..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.c +++ /dev/null @@ -1,470 +0,0 @@ -static const unsigned char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, - 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, - 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, - 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, - 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, - 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, - 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, - 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0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, - 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, - 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, - 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, - 0xa, 0xd, 0xa, 0}; - -const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; - -const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; - -const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; - -const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; - -#define HTTPD_FS_ROOT file_tcp_shtml - -#define HTTPD_FS_NUMFILES 6 diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.h b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.h deleted file mode 100644 index 52d35c265..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd-fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FSDATA_H__ -#define __HTTPD_FSDATA_H__ - -#include "uip.h" - -struct httpd_fsdata_file { - const struct httpd_fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -struct httpd_fsdata_file_noconst { - struct httpd_fsdata_file *next; - char *name; - char *data; - int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -#endif /* __HTTPD_FSDATA_H__ */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.c b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.c deleted file mode 100644 index 644cf16b7..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.c +++ /dev/null @@ -1,346 +0,0 @@ -/** - * \addtogroup apps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - - */ - -/** - * \file - * Web server - * \author - * Adam Dunkels - */ - - -/* - * Copyright (c) 2004, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-cgi.h" -#include "http-strings.h" - -#include - -#define STATE_WAITING 0 -#define STATE_OUTPUT 1 - -#define ISO_nl 0x0a -#define ISO_space 0x20 -#define ISO_bang 0x21 -#define ISO_percent 0x25 -#define ISO_period 0x2e -#define ISO_slash 0x2f -#define ISO_colon 0x3a - - -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_part_of_file(void *state) -{ - struct httpd_state *s = (struct httpd_state *)state; - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - memcpy(uip_appdata, s->file.data, s->len); - - return s->len; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - do { - PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); - s->file.len -= s->len; - s->file.data += s->len; - } while(s->file.len > 0); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_part_of_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND(&s->sout, s->file.data, s->len); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static void -next_scriptstate(struct httpd_state *s) -{ - char *p; - p = strchr(s->scriptptr, ISO_nl) + 1; - s->scriptlen -= (unsigned short)(p - s->scriptptr); - s->scriptptr = p; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_script(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->scriptpt); - - - while(s->file.len > 0) { - - /* Check if we should start executing a script. */ - if(*s->file.data == ISO_percent && - *(s->file.data + 1) == ISO_bang) { - s->scriptptr = s->file.data + 3; - s->scriptlen = s->file.len - 3; - if(*(s->scriptptr - 1) == ISO_colon) { - httpd_fs_open(s->scriptptr + 1, &s->file); - PT_WAIT_THREAD(&s->scriptpt, send_file(s)); - } else { - PT_WAIT_THREAD(&s->scriptpt, - httpd_cgi(s->scriptptr)(s, s->scriptptr)); - } - next_scriptstate(s); - - /* The script is over, so we reset the pointers and continue - sending the rest of the file. */ - s->file.data = s->scriptptr; - s->file.len = s->scriptlen; - } else { - /* See if we find the start of script marker in the block of HTML - to be sent. */ - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - - if(*s->file.data == ISO_percent) { - ptr = strchr(s->file.data + 1, ISO_percent); - } else { - ptr = strchr(s->file.data, ISO_percent); - } - if(ptr != NULL && - ptr != s->file.data) { - s->len = (int)(ptr - s->file.data); - if(s->len >= uip_mss()) { - s->len = uip_mss(); - } - } - PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); - s->file.data += s->len; - s->file.len -= s->len; - - } - } - - PT_END(&s->scriptpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) -{ - char *ptr; - - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND_STR(&s->sout, statushdr); - - ptr = strrchr(s->filename, ISO_period); - if(ptr == NULL) { - PSOCK_SEND_STR(&s->sout, http_content_type_binary); - } else if(strncmp(http_html, ptr, 5) == 0 || - strncmp(http_shtml, ptr, 6) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_html); - } else if(strncmp(http_css, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_css); - } else if(strncmp(http_png, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_png); - } else if(strncmp(http_gif, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_gif); - } else if(strncmp(http_jpg, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_jpg); - } else { - PSOCK_SEND_STR(&s->sout, http_content_type_plain); - } - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_output(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->outputpt); - - if(!httpd_fs_open(s->filename, &s->file)) { - httpd_fs_open(http_404_html, &s->file); - strcpy(s->filename, http_404_html); - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_404)); - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_200)); - ptr = strchr(s->filename, ISO_period); - if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { - PT_INIT(&s->scriptpt); - PT_WAIT_THREAD(&s->outputpt, handle_script(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } - } - PSOCK_CLOSE(&s->sout); - PT_END(&s->outputpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_input(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sin); - - PSOCK_READTO(&s->sin, ISO_space); - - - if(strncmp(s->inputbuf, http_get, 4) != 0) { - PSOCK_CLOSE_EXIT(&s->sin); - } - PSOCK_READTO(&s->sin, ISO_space); - - if(s->inputbuf[0] != ISO_slash) { - PSOCK_CLOSE_EXIT(&s->sin); - } - - if(s->inputbuf[1] == ISO_space) { - strncpy(s->filename, http_index_html, sizeof(s->filename)); - } else { - - s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; - - /* Process any form input being sent to the server. */ - { - extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); - vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); - } - - strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); - } - - /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ - - s->state = STATE_OUTPUT; - - while(1) { - PSOCK_READTO(&s->sin, ISO_nl); - - if(strncmp(s->inputbuf, http_referer, 8) == 0) { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; - /* httpd_log(&s->inputbuf[9]);*/ - } - } - - PSOCK_END(&s->sin); -} -/*---------------------------------------------------------------------------*/ -static void -handle_connection(struct httpd_state *s) -{ - handle_input(s); - if(s->state == STATE_OUTPUT) { - handle_output(s); - } -} -/*---------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); - - if(uip_closed() || uip_aborted() || uip_timedout()) { - } else if(uip_connected()) { - PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); - PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); - PT_INIT(&s->outputpt); - s->state = STATE_WAITING; - /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ - s->timer = 0; - handle_connection(s); - } else if(s != NULL) { - if(uip_poll()) { - ++s->timer; - if(s->timer >= 20) { - uip_abort(); - } - } else { - s->timer = 0; - } - handle_connection(s); - } else { - uip_abort(); - } -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the web server - * - * This function initializes the web server and should be - * called at system boot-up. - */ -void -httpd_init(void) -{ - uip_listen(HTONS(80)); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.h b/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.h deleted file mode 100644 index 7f7a6666e..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/httpd.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2005, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -#include "psock.h" -#include "httpd-fs.h" - -struct httpd_state { - unsigned char timer; - struct psock sin, sout; - struct pt outputpt, scriptpt; - char inputbuf[50]; - char filename[20]; - char state; - struct httpd_fs_file file; - int len; - char *scriptptr; - int scriptlen; - - unsigned short count; -}; - -void httpd_init(void); -void httpd_appcall(void); - -void httpd_log(char *msg); -void httpd_log_file(u16_t *requester, char *file); - -#endif /* __HTTPD_H__ */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/makefsdata b/Demo/CORTEX_LM3S6965_GCC/webserver/makefsdata deleted file mode 100644 index 8d2715a8a..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/makefsdata +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> httpd-fsdata.c"); - -chdir("httpd-fs"); - -opendir(DIR, "."); -@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); -closedir(DIR); - -foreach $file (@files) { - - if(-d $file && $file !~ /^\./) { - print "Processing directory $file\n"; - opendir(DIR, $file); - @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); - closedir(DIR); - printf "Adding files @newfiles\n"; - @files = (@files, map { $_ = "$file/$_" } @newfiles); - next; - } -} - -foreach $file (@files) { - if(-f $file) { - - print "Adding file $file\n"; - - open(FILE, $file) || die "Could not open file $file\n"; - - $file =~ s-^-/-; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - # for AVR, add PROGMEM here - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "0};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@pfiles, $file); - } -} - -for($i = 0; $i < @fvars; $i++) { - $file = $pfiles[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/makestrings b/Demo/CORTEX_LM3S6965_GCC/webserver/makestrings deleted file mode 100644 index 8a13c6d29..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/makestrings +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl - - -sub stringify { - my $name = shift(@_); - open(OUTPUTC, "> $name.c"); - open(OUTPUTH, "> $name.h"); - - open(FILE, "$name"); - - while() { - if(/(.+) "(.+)"/) { - $var = $1; - $data = $2; - - $datan = $data; - $datan =~ s/\\r/\r/g; - $datan =~ s/\\n/\n/g; - $datan =~ s/\\01/\01/g; - $datan =~ s/\\0/\0/g; - - printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); - printf(OUTPUTC "/* \"$data\" */\n"); - printf(OUTPUTC "{"); - for($j = 0; $j < length($datan); $j++) { - printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); - } - printf(OUTPUTC "};\n"); - - printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); - - } - } - close(OUTPUTC); - close(OUTPUTH); -} -stringify("http-strings"); - -exit 0; - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/uIP_Task.c b/Demo/CORTEX_LM3S6965_GCC/webserver/uIP_Task.c deleted file mode 100644 index c6c2f3597..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/uIP_Task.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -#include "lcd_message.h" - -/* uip includes. */ -#include "hw_types.h" - -#include "uip.h" -#include "uip_arp.h" -#include "httpd.h" -#include "timer.h" -#include "clock-arch.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "hw_memmap.h" -#include "lmi_flash.h" - -/* Demo includes. */ -#include "emac.h" -#include "partest.h" - -/*-----------------------------------------------------------*/ - -/* IP address configuration. */ -#define uipIP_ADDR0 172 -#define uipIP_ADDR1 25 -#define uipIP_ADDR2 218 -#define uipIP_ADDR3 9 - -/* How long to wait before attempting to connect the MAC again. */ -#define uipINIT_WAIT 100 - -/* Shortcut to the header within the Rx buffer. */ -#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) - -/* Standard constant. */ -#define uipTOTAL_FRAME_HEADER_SIZE 54 - -/*-----------------------------------------------------------*/ - -/* - * Send the uIP buffer to the MAC. - */ -static void prvENET_Send(void); - -/* - * Setup the MAC address in the MAC itself, and in the uIP stack. - */ -static void prvSetMACAddress( void ); - -/* - * Port functions required by the uIP stack. - */ -void clock_init( void ); -clock_time_t clock_time( void ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used by the ISR to wake the uIP task. */ -extern xSemaphoreHandle xEMACSemaphore; - -/*-----------------------------------------------------------*/ - -void clock_init(void) -{ - /* This is done when the scheduler starts. */ -} -/*-----------------------------------------------------------*/ - -clock_time_t clock_time( void ) -{ - return xTaskGetTickCount(); -} -/*-----------------------------------------------------------*/ - -void vuIP_Task( void *pvParameters ) -{ -portBASE_TYPE i; -uip_ipaddr_t xIPAddr; -struct timer periodic_timer, arp_timer; -extern void ( vEMAC_ISR )( void ); - - /* Create the semaphore used by the ISR to wake this task. */ - vSemaphoreCreateBinary( xEMACSemaphore ); - - /* Initialise the uIP stack. */ - timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); - timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); - uip_init(); - uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); - uip_sethostaddr( xIPAddr ); - httpd_init(); - - while( vInitEMAC() != pdPASS ) - { - vTaskDelay( uipINIT_WAIT ); - } - prvSetMACAddress(); - - - for( ;; ) - { - /* Is there received data ready to be processed? */ - uip_len = uiGetEMACRxData( uip_buf ); - - if( uip_len > 0 ) - { - /* Standard uIP loop taken from the uIP manual. */ - - if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) - { - uip_arp_ipin(); - uip_input(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) - { - uip_arp_arpin(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - prvENET_Send(); - } - } - } - else - { - if( timer_expired( &periodic_timer ) ) - { - timer_reset( &periodic_timer ); - for( i = 0; i < UIP_CONNS; i++ ) - { - uip_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - - /* Call the ARP timer function every 10 seconds. */ - if( timer_expired( &arp_timer ) ) - { - timer_reset( &arp_timer ); - uip_arp_timer(); - } - } - else - { - /* We did not receive a packet, and there was no periodic - processing to perform. Block for a fixed period. If a packet - is received during this period we will be woken by the ISR - giving us the Semaphore. */ - xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvENET_Send(void) -{ - vInitialiseSend(); - vIncrementTxLength( uip_len ); - vSendBufferToMAC(); -} -/*-----------------------------------------------------------*/ - -static void prvSetMACAddress( void ) -{ -unsigned portLONG ulUser0, ulUser1; -unsigned char pucMACArray[8]; -struct uip_eth_addr xAddr; - - /* Get the device MAC address from flash */ - FlashUserGet(&ulUser0, &ulUser1); - - /* Convert the MAC address from flash into sequence of bytes. */ - pucMACArray[0] = ((ulUser0 >> 0) & 0xff); - pucMACArray[1] = ((ulUser0 >> 8) & 0xff); - pucMACArray[2] = ((ulUser0 >> 16) & 0xff); - pucMACArray[3] = ((ulUser1 >> 0) & 0xff); - pucMACArray[4] = ((ulUser1 >> 8) & 0xff); - pucMACArray[5] = ((ulUser1 >> 16) & 0xff); - - /* Program the MAC address. */ - EthernetMACAddrSet(ETH_BASE, pucMACArray); - - xAddr.addr[ 0 ] = pucMACArray[0]; - xAddr.addr[ 1 ] = pucMACArray[1]; - xAddr.addr[ 2 ] = pucMACArray[2]; - xAddr.addr[ 3 ] = pucMACArray[3]; - xAddr.addr[ 4 ] = pucMACArray[4]; - xAddr.addr[ 5 ] = pucMACArray[5]; - uip_setethaddr( xAddr ); -} -/*-----------------------------------------------------------*/ - -void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) -{ -char *c, *pcText; -static portCHAR cMessageForDisplay[ 32 ]; -extern xQueueHandle xOLEDQueue; -xOLEDMessage xOLEDMessage; - - /* Process the form input sent by the IO page of the served HTML. */ - - c = strstr( pcInputString, "?" ); - - if( c ) - { - /* Turn LED's on or off in accordance with the check box status. */ - if( strstr( c, "LED0=1" ) != NULL ) - { - vParTestSetLED( 0, 1 ); - } - else - { - vParTestSetLED( 0, 0 ); - } - - /* Find the start of the text to be displayed on the LCD. */ - pcText = strstr( c, "LCD=" ); - pcText += strlen( "LCD=" ); - - /* Terminate the file name for further processing within uIP. */ - *c = 0x00; - - /* Terminate the LCD string. */ - c = strstr( pcText, " " ); - if( c != NULL ) - { - *c = 0x00; - } - - /* Add required spaces. */ - while( ( c = strstr( pcText, "+" ) ) != NULL ) - { - *c = ' '; - } - - /* Write the message to the LCD. */ - strcpy( cMessageForDisplay, pcText ); - xOLEDMessage.pcMessage = cMessageForDisplay; - xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/uip-conf.h b/Demo/CORTEX_LM3S6965_GCC/webserver/uip-conf.h deleted file mode 100644 index 664077d89..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/uip-conf.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1500 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#define UIP_CONF_EXTERNAL_BUFFER - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_GCC/webserver/webserver.h b/Demo/CORTEX_LM3S6965_GCC/webserver/webserver.h deleted file mode 100644 index 1acb290b8..000000000 --- a/Demo/CORTEX_LM3S6965_GCC/webserver/webserver.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ -#ifndef __WEBSERVER_H__ -#define __WEBSERVER_H__ - -#include "httpd.h" - -typedef struct httpd_state uip_tcp_appstate_t; -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - - -#endif /* __WEBSERVER_H__ */ diff --git a/Demo/CORTEX_LM3S6965_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S6965_IAR/FreeRTOSConfig.h deleted file mode 100644 index 709dc0d3e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxx.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxx.h deleted file mode 100644 index 11952d416..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxx.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXX_H__ -#define __LM3SXXX_H__ - -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXX_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxxx.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxxx.h deleted file mode 100644 index bafb07cda..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/LM3Sxxxx.h +++ /dev/null @@ -1,70 +0,0 @@ -//***************************************************************************** -// -// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __LM3SXXXX_H__ -#define __LM3SXXXX_H__ - -#include "hw_adc.h" -#include "hw_can.h" -#include "hw_comp.h" -#include "hw_ethernet.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_hibernate.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "adc.h" -#include "can.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "ethernet.h" -#include "flash.h" -#include "gpio.h" -#include "hibernate.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif // __LM3SXXXX_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_flash.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_timer.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/adc.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/adc.h deleted file mode 100644 index 7533ccfd8..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/adc.h +++ /dev/null @@ -1,130 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceOverflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceUnderflowClear(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/can.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/can.h deleted file mode 100644 index bdd623304..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/can.h +++ /dev/null @@ -1,441 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CAN_H__ -#define __CAN_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -//! These are the flags used by the tCANMsgObject variable when calling the -//! the CANMessageSet() and CANMessageGet() APIs. -// -//***************************************************************************** -typedef enum -{ - // - //! This indicates that transmit interrupts should be enabled, or are - //! enabled. - // - MSG_OBJ_TX_INT_ENABLE = 0x00000001, - - // - //! This indicates that receive interrupts should be enabled or are - //! enabled. - // - MSG_OBJ_RX_INT_ENABLE = 0x00000002, - - // - //! This indicates that a message object will use or is using an extended - //! identifier. - // - MSG_OBJ_EXTENDED_ID = 0x00000004, - - // - //! This indicates that a message object will use or is using filtering - //! based on the object's message Identifier. - // - MSG_OBJ_USE_ID_FILTER = 0x00000008, - - // - //! This indicates that new data was available in the message object. - // - MSG_OBJ_NEW_DATA = 0x00000080, - - // - //! This indicates that data was lost since this message object was last - //! read. - // - MSG_OBJ_DATA_LOST = 0x00000100, - - // - //! This indicates that a message object will use or is using filtering - //! based on the direction of the transfer. If the direction filtering is - //! used then ID filtering must also be enabled. - // - MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object will use or is using message - //! identifier filtering based of the the extended identifier. - //! If the extended identifier filtering is used then ID filtering must - //! also be enabled. - // - MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), - - // - //! This indicates that a message object is a remote frame. - // - MSG_OBJ_REMOTE_FRAME = 0x00000040, - - // - //! This indicates that a message object has no flags set. - // - MSG_OBJ_NO_FLAGS = 0x00000000 -} -tCANObjFlags; - -//***************************************************************************** -// -//! This define is used with the #tCANObjFlags enumerated values to allow -//! checking only status flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! This structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - unsigned long ulMsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - unsigned long ulMsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - unsigned long ulFlags; - - // - //! This value is the number of bytes of data in the message object. - // - unsigned long ulMsgLen; - - // - //! This is a pointer to the message object's data. - // - unsigned char *pucMsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - unsigned int uSyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - unsigned int uPhase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - unsigned int uSJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - unsigned int uQuantumPrescaler; - -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the a CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of the several status registers -//! to read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32 bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32 bit mask of message objects with a new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32 bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -//! These definitions are used to specify interrupt sources to CANIntEnable() -//! and CANIntDisable(). -// -//***************************************************************************** -typedef enum -{ - // - //! This flag is used to allow a CAN controller to generate error - //! interrupts. - // - CAN_INT_ERROR = 0x00000008, - - // - //! This flag is used to allow a CAN controller to generate status - //! interrupts. - // - CAN_INT_STATUS = 0x00000004, - - // - //! This flag is used to allow a CAN controller to generate any CAN - //! interrupts. If this is not set then no interrupts will be generated by - //! the CAN controller. - // - CAN_INT_MASTER = 0x00000002 -} -tCANIntFlags; - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that will -//! be set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -//! The following enumeration contains all error or status indicators that -//! can be returned when calling the CANStatusGet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! CAN controller has entered a Bus Off state. - // - CAN_STATUS_BUS_OFF = 0x00000080, - - // - //! CAN controller error level has reached warning level. - // - CAN_STATUS_EWARN = 0x00000040, - - // - //! CAN controller error level has reached error passive level. - // - CAN_STATUS_EPASS = 0x00000020, - - // - //! A message was received successfully since the last read of this status. - // - CAN_STATUS_RXOK = 0x00000010, - - // - //! A message was transmitted successfully since the last read of this - //! status. - // - CAN_STATUS_TXOK = 0x00000008, - - // - //! This is the mask for the last error code field. - // - CAN_STATUS_LEC_MSK = 0x00000007, - - // - //! There was no error. - // - CAN_STATUS_LEC_NONE = 0x00000000, - - // - //! A bit stuffing error has occurred. - // - CAN_STATUS_LEC_STUFF = 0x00000001, - - // - //! A formatting error has occurred. - // - CAN_STATUS_LEC_FORM = 0x00000002, - - // - //! An acknowledge error has occurred. - // - CAN_STATUS_LEC_ACK = 0x00000003, - - // - //! The bus remained a bit level of 1 for longer than is allowed. - // - CAN_STATUS_LEC_BIT1 = 0x00000004, - - // - //! The bus remained a bit level of 0 for longer than is allowed. - // - CAN_STATUS_LEC_BIT0 = 0x00000005, - - // - //! A CRC error has occurred. - // - CAN_STATUS_LEC_CRC = 0x00000006, - - // - //! This is the mask for the CAN Last Error Code (LEC). - // - CAN_STATUS_LEC_MASK = 0x00000007 -} -tCANStatusCtrl; - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANInit(unsigned long ulBase); -extern void CANEnable(unsigned long ulBase); -extern void CANDisable(unsigned long ulBase); -extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); -extern unsigned long CANReadReg(unsigned long ulRegAddress); -extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); -extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tMsgObjType eMsgType); -extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, - tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); -extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); -extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); -extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); -extern unsigned long CANIntStatus(unsigned long ulBase, - tCANIntStsReg eIntStsReg); -extern tBoolean CANRetryGet(unsigned long ulBase); -extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); -extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, - unsigned long *pulTxCount); -extern long CANGetIntNumber(unsigned long ulBase); -extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); -extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, - int iSize); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#ifdef __cplusplus -} -#endif - -#endif // __CAN_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/comp.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/comp.h deleted file mode 100644 index 60fa1e04e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/comp.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#ifndef DEPRECATED -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#endif -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/cpu.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/cpu.h deleted file mode 100644 index f21f82221..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/debug.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/debug.h deleted file mode 100644 index c64b8fc2d..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/driverlib.r79 b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/driverlib.r79 deleted file mode 100644 index 3e297f9cf989e5fa1211a3a73c3d607fce6129a8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 192492 zcmeFa2Vh;rl{bFtYtnn_%_^29+gPrWEWaz$ELoC4vQ>~|Y!(M0%d#!3hKd^oOgDrO zSW2h~$!1eYVzMFGWJ3ZD!6{4DfSs4JVM+N?NMjSSAql&DzjNl^JNLf#guVYS|NnmZ z?+PqUIp@roGc#xA&dfQZM9gd>uqQk)Fgmh*U~tFKlMzK#`V_UlI~Z7orMwFKiwq15P0kLCP3#y(EOTIBa%g&BU}pF1 z*meRb6Nx(pX9gK&6!FmD_UVby*_mMiD5Qjef#LBTBZK1z2S!I`W=1)y08tQ}ni<$T zJT*NsLD_2jAG95#y~;O#plQ7=XKx!iuxsDQ__o~>W5e6F?-`jI+C4nAZF+Eg$M%W+ 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2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __ETHERNET_H__ -#define __ETHERNET_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EthernetConfigSet as the ulConfig value, and -// returned from EthernetConfigGet. -// -//***************************************************************************** -#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets -#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous -#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast -#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode -#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation -#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding - -//***************************************************************************** -// -// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and -// EthernetIntClear as the ulIntFlags parameter, and returned from -// EthernetIntStatus. -// -//***************************************************************************** -#define ETH_INT_PHY 0x040 // PHY Event/Interrupt -#define ETH_INT_MDIO 0x020 // Management Transaction -#define ETH_INT_RXER 0x010 // RX Error -#define ETH_INT_RXOF 0x008 // RX FIFO Overrun -#define ETH_INT_TX 0x004 // TX Complete -#define ETH_INT_TXER 0x002 // TX Error -#define ETH_INT_RX 0x001 // RX Complete - -//***************************************************************************** -// -// The following define values that can be passed as register addresses to -// EthernetPHYRead and EthernetPHYWrite. -// -//***************************************************************************** -#define PHY_MR0 0 // Control -#define PHY_MR1 1 // Status -#define PHY_MR2 2 // PHY Identifier 1 -#define PHY_MR3 3 // PHY Identifier 2 -#define PHY_MR4 4 // Auto-Neg. Advertisement -#define PHY_MR5 5 // Auto-Neg. Link Partner Ability -#define PHY_MR6 6 // Auto-Neg. Expansion - // 7-15 Reserved/Not Implemented -#define PHY_MR16 16 // Vendor Specific -#define PHY_MR17 17 // Interrupt Control/Status -#define PHY_MR18 18 // Diagnostic Register -#define PHY_MR19 19 // Transceiver Control - // 20-22 Reserved -#define PHY_MR23 23 // LED Configuration Register -#define PHY_MR24 24 // MDI/MDIX Control Register - // 25-31 Reserved/Not Implemented - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR0 register -// -//***************************************************************************** -#define PHY_MR0_RESET 0x8000 // Reset the PHY -#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback -#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection -#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T -#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T -#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable -#define PHY_MR0_PWRDN 0x0800 // Power Down -#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation -#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex -#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode -#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR1 register -// -//***************************************************************************** -#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete -#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected -#define PHY_MR1_LINK 0x0004 // Link Established -#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR17 register -// -//***************************************************************************** -#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt -#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int. -#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int. -#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt -#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt -#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int. - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR18 register -// -//***************************************************************************** -#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed -#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated -#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated -#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated -#define PHY_MR18_RATE 0x0400 // Rate Negotiated -#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T -#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR23 register -// -//***************************************************************************** -#define PHY_MR23_LED1 0x00f0 // LED1 Configuration -#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status -#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity -#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity -#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity -#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity -#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity -#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity -#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity -#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity -#define PHY_MR23_LED0 0x000f // LED0 Configuration -#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status -#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity -#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity -#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity -#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity -#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity -#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity -#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity -#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity - -//***************************************************************************** -// -// The following define bit fields in the ETH_MR24 register -// -//***************************************************************************** -#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration -#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough -#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - big endian/little endian byte swapping macros for -// 32-bit (long) values -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - big endian/little endian byte swapping macros for -// 16-bit (short) values -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_flash.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_IAR/ParTest/ParTest.c b/Demo/CORTEX_LM3S6965_IAR/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.dep deleted file mode 100644 index 478745d3b..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.dep +++ /dev/null @@ -1,856 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\timertest.c - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - $PROJ_DIR$\..\..\Source\queue.c - $PROJ_DIR$\Debug\Obj\heap_2.r79 - $PROJ_DIR$\..\..\Source\list.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - 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XAR - 2 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Demo files - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\blocktim.c - - - $PROJ_DIR$\..\Common\Minimal\death.c - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\timertest.c - - - - Library files - - $PROJ_DIR$\LuminaryDrivers\driverlib.r79 - - - $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c - - - - Scheduler files - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - System files - - $PROJ_DIR$\startup_ewarm.c - - - - uIP files - - $PROJ_DIR$\webserver\emac.c - - - $PROJ_DIR$\webserver\http-strings.c - - - $PROJ_DIR$\webserver\httpd-cgi.c - - - $PROJ_DIR$\webserver\httpd-fs.c - - - $PROJ_DIR$\webserver\httpd.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c - - - $PROJ_DIR$\webserver\uIP_Task.c - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.eww b/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.xcl b/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.xcl deleted file mode 100644 index a7044e640..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/RTOSDemo.xcl +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// webserver-lwip.xcl - Linker script for EW-ARM. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -// -// Set the CPU type to ARM. -// --carm - -// -// Define the size of flash and SRAM. -// --DROMSTART=00000000 --DROMEND=00040000 --DRAMSTART=20000000 --DRAMEND=20010000 - - - -// -// Define the sections to place into flash, and the order to place them. -// --Z(CODE)INTVEC=ROMSTART-ROMEND --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)CODE=ROMSTART-ROMEND --Z(CONST)CODE_ID=ROMSTART-ROMEND --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -// -// Define the sections to place into SRAM, and the order to place them. -// --Z(DATA)VTABLE=RAMSTART-RAMEND --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND --Z(DATA)CODE_I=RAMSTART-RAMEND diff --git a/Demo/CORTEX_LM3S6965_IAR/bitmap.h b/Demo/CORTEX_LM3S6965_IAR/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, -0x00 }; - -#define bmpBITMAP_HEIGHT 50 -#define bmpBITMAP_WIDTH 128 - -#endif diff --git a/Demo/CORTEX_LM3S6965_IAR/lcd_message.h b/Demo/CORTEX_LM3S6965_IAR/lcd_message.h deleted file mode 100644 index adfc18b8a..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/lcd_message.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef LCD_MESSAGE_H -#define LCD_MESSAGE_H - -typedef struct -{ - signed char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S6965_IAR/main.c b/Demo/CORTEX_LM3S6965_IAR/main.c deleted file mode 100644 index 16cc62628..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/main.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - * "uIP" task - This is the task that handles the uIP stack. All TCP/IP - * processing is performed in this task. - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* Size of the stack allocated to the uIP task. */ -#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that handles the uIP stack. All TCP/IP processing is performed in - * this task. - */ -extern void vuIP_Task( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Create the uIP task. */ - xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - vSetupTimer(); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable/Reset the Ethernet Controller */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); - SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S6965_IAR/startup_ewarm.c b/Demo/CORTEX_LM3S6965_IAR/startup_ewarm.c deleted file mode 100644 index af1c8ac18..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/startup_ewarm.c +++ /dev/null @@ -1,265 +0,0 @@ -//***************************************************************************** -// -// startup_ewarm.c - Boot code for Stellaris. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 100 of the Stellaris Ethernet -// Applications Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// External declaration for the interrupt handler used by the application. -// -//***************************************************************************** - - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vEMAC_ISR( void ); -extern Timer0IntHandler( void ); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = -{ - { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - Timer0IntHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // Quadrature Encoder 1 - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // CAN2 - vEMAC_ISR, // Ethernet - IntDefaultHandler // Power Island -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S6965_IAR/timertest.c b/Demo/CORTEX_LM3S6965_IAR/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/Makefile.webserver b/Demo/CORTEX_LM3S6965_IAR/webserver/Makefile.webserver deleted file mode 100644 index f38c47a72..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/Makefile.webserver +++ /dev/null @@ -1 +0,0 @@ -APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/clock-arch.h b/Demo/CORTEX_LM3S6965_IAR/webserver/clock-arch.h deleted file mode 100644 index cde657b62..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include "FreeRTOS.h" - -typedef unsigned long clock_time_t; -#define CLOCK_CONF_SECOND configTICK_RATE_HZ - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/emac.c b/Demo/CORTEX_LM3S6965_IAR/webserver/emac.c deleted file mode 100644 index b5f394442..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/emac.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "Semphr.h" -#include "task.h" - -/* Demo includes. */ -#include "EMAC.h" - -/* uIP includes. */ -#include "uip.h" - -/* Hardware library includes. */ -#include "hw_types.h" -#include "hw_memmap.h" -#include "hw_ints.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "interrupt.h" - -#define emacNUM_RX_BUFFERS 5 -#define emacFRAM_SIZE_BYTES 2 -#define macNEGOTIATE_DELAY 2000 -#define macWAIT_SEND_TIME ( 10 ) - -/* The task that handles the MAC peripheral. This is created at a high -priority and is effectively a deferred interrupt handler. The peripheral -handling is deferred to a task to prevent the entire FIFO having to be read -from within an ISR. */ -void vMACHandleTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used to wake the uIP task when data arrives. */ -xSemaphoreHandle xEMACSemaphore = NULL; - -/* The semaphore used to wake the interrupt handler task. The peripheral -is processed at the task level to prevent the need to read the entire FIFO from -within the ISR itself. */ -xSemaphoreHandle xMACInterruptSemaphore = NULL; - -/* The buffer used by the uIP stack. In this case the pointer is used to -point to one of the Rx buffers. */ -unsigned portCHAR *uip_buf; - -/* Buffers into which Rx data is placed. */ -static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; - -/* The length of the data within each of the Rx buffers. */ -static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; - -/* Used to keep a track of the number of bytes to transmit. */ -static unsigned portLONG ulNextTxSpace; - -/*-----------------------------------------------------------*/ - -portBASE_TYPE vInitEMAC( void ) -{ -unsigned long ulTemp; -portBASE_TYPE xReturn; - - /* Ensure all interrupts are disabled. */ - EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); - - /* Clear any interrupts that were already pending. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Initialise the MAC and connect. */ - EthernetInit( ETH_BASE ); - EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); - EthernetEnable( ETH_BASE ); - - /* Mark each Rx buffer as empty. */ - for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) - { - ulRxLength[ ulTemp ] = 0; - } - - /* Create the queue and task used to defer the MAC processing to the - task level. */ - vSemaphoreCreateBinary( xMACInterruptSemaphore ); - xSemaphoreTake( xMACInterruptSemaphore, 0 ); - xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - vTaskDelay( macNEGOTIATE_DELAY ); - - /* We are only interested in Rx interrupts. */ - IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_ETH ); - EthernetIntEnable(ETH_BASE, ETH_INT_RX); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) -{ -static unsigned long ulNextRxBuffer = 0; -unsigned int iLen; - - iLen = ulRxLength[ ulNextRxBuffer ]; - - if( iLen != 0 ) - { - /* Leave room for the size at the start of the buffer. */ - uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - - ulRxLength[ ulNextRxBuffer ] = 0; - - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - } - - return iLen; -} -/*-----------------------------------------------------------*/ - -void vInitialiseSend( void ) -{ - /* Set the index to the first byte to send - skipping over the size - bytes. */ - ulNextTxSpace = 2; -} -/*-----------------------------------------------------------*/ - -void vIncrementTxLength( unsigned portLONG ulLength ) -{ - ulNextTxSpace += ulLength; -} -/*-----------------------------------------------------------*/ - -void vSendBufferToMAC( void ) -{ -unsigned long *pulSource; -unsigned portSHORT * pus; -unsigned portLONG ulNextWord; - - /* Locate the data to be send. */ - pus = ( unsigned portSHORT * ) uip_buf; - - /* Add in the size of the data. */ - pus--; - *pus = ulNextTxSpace; - - /* Wait for data to be sent if there is no space immediately. */ - while( !EthernetSpaceAvail( ETH_BASE ) ) - { - vTaskDelay( macWAIT_SEND_TIME ); - } - - pulSource = ( unsigned portLONG * ) pus; - - for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) - { - HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; - pulSource++; - } - - /* Go. */ - HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; -} -/*-----------------------------------------------------------*/ - -void vEMAC_ISR( void ) -{ -portBASE_TYPE xSwitchRequired = pdFALSE; -unsigned portLONG ulTemp; - - /* Clear the interrupt. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Was it an Rx interrupt? */ - if( ulTemp & ETH_INT_RX ) - { - xSwitchRequired = pdTRUE; - xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE ); - EthernetIntDisable( ETH_BASE, ETH_INT_RX ); - } - - /* Switch to the uIP task. */ - portEND_SWITCHING_ISR( xSwitchRequired ); -} -/*-----------------------------------------------------------*/ - -void vMACHandleTask( void *pvParameters ) -{ -unsigned long ulLen = 0, i; -unsigned portLONG ulLength, ulInt; -unsigned long *pulBuffer; -static unsigned portLONG ulNextRxBuffer = 0; -portBASE_TYPE xSwitchRequired = pdFALSE; - - for( ;; ) - { - /* Wait for something to do. */ - xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); - - while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) - { - ulLength = HWREG( ETH_BASE + MAC_O_DATA ); - - /* Leave room at the start of the buffer for the size. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - *pulBuffer = ( ulLength >> 16 ); - - /* Get the size of the data. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); - ulLength &= 0xFFFF; - - if( ulLength > 4 ) - { - ulLength -= 4; - - if( ulLength >= UIP_BUFSIZE ) - { - /* The data won't fit in our buffer. Ensure we don't - try to write into the buffer. */ - ulLength = 0; - } - - /* Read out the data into our buffer. */ - for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) - { - *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); - pulBuffer++; - } - - /* Store the length of the data into the separate array. */ - ulRxLength[ ulNextRxBuffer ] = ulLength; - - /* Use the next buffer the next time through. */ - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - - /* Ensure the uIP task is not blocked as data has arrived. */ - xSemaphoreGive( xEMACSemaphore ); - } - } - - EthernetIntEnable( ETH_BASE, ETH_INT_RX ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/emac.h b/Demo/CORTEX_LM3S6965_IAR/webserver/emac.h deleted file mode 100644 index a49b59828..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/emac.h +++ /dev/null @@ -1,322 +0,0 @@ -/*---------------------------------------------------------------------------- - * LPC2378 Ethernet Definitions - *---------------------------------------------------------------------------- - * Name: EMAC.H - * Purpose: Philips LPC2378 EMAC hardware definitions - *---------------------------------------------------------------------------- - * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#ifndef __EMAC_H -#define __EMAC_H - -/* MAC address definition. The MAC address must be unique on the network. */ -#define emacETHADDR0 0 -#define emacETHADDR1 0xbd -#define emacETHADDR2 0x33 -#define emacETHADDR3 0x02 -#define emacETHADDR4 0x64 -#define emacETHADDR5 0x24 - - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ -#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ - -/* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE 0x7FE00000 -#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) -#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) -#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) -#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) -#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) - -/* RX and TX descriptor and status definitions. */ -#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) -#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) -#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) -#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) -#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) -#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) -#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) -#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) -#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* MAC Configuration Register 1 */ -#define MAC1_REC_EN 0x00000001 /* Receive Enable */ -#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ -#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ -#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ -#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ -#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ -#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ -#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ -#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ -#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ -#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ -#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ -#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ -#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ -#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ -#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ -#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ -#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ -#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ -#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ -#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ -#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ -#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ -#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ - -/* Non Back-to-Back Inter-Packet-Gap Register */ -#define IPGR_DEF 0x00000012 /* Recommended value */ - -/* Collision Window/Retry Register */ -#define CLRT_DEF 0x0000370F /* Default value */ - -/* PHY Support Register */ -#undef SUPP_SPEED /* Remove compiler warning. */ -#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ -#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ - -/* Test Register */ -#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ -#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ -#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ - -/* MII Management Configuration Register */ -#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ -#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ -#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ -#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ - -/* MII Management Command Register */ -#undef MCMD_READ /* Remove compiler warning. */ -#define MCMD_READ 0x00000001 /* MII Read */ -#undef MCMD_SCAN /* Remove compiler warning. */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#undef MIND_BUSY /* Remove compiler warning. */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* Command Register */ -#define CR_RX_EN 0x00000001 /* Enable Receive */ -#define CR_TX_EN 0x00000002 /* Enable Transmit */ -#define CR_REG_RES 0x00000008 /* Reset Host Registers */ -#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ -#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ -#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ -#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ -#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ -#define CR_RMII 0x00000200 /* Reduced MII Interface */ -#define CR_FULL_DUP 0x00000400 /* Full Duplex */ - -/* Status Register */ -#define SR_RX_EN 0x00000001 /* Enable Receive */ -#define SR_TX_EN 0x00000002 /* Enable Transmit */ - -/* Transmit Status Vector 0 Register */ -#define TSV0_CRC_ERR 0x00000001 /* CRC error */ -#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ -#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ -#define TSV0_MCAST 0x00000010 /* Multicast Destination */ -#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ -#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ -#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ -#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ -#define TSV0_GIANT 0x00000400 /* Giant Frame */ -#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ -#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ -#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ -#define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ -#define TSV0_VLAN 0x80000000 /* VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ -#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ -#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ -#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ -#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ -#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ -#define RSV_CRC_ERR 0x00100000 /* CRC Error */ -#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ -#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ -#define RSV_REC_OK 0x00800000 /* Frame Received OK */ -#define RSV_MCAST 0x01000000 /* Multicast Frame */ -#define RSV_BCAST 0x02000000 /* Broadcast Frame */ -#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ -#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ -#define RSV_PAUSE 0x10000000 /* Pause Frame */ -#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ -#define RSV_VLAN 0x40000000 /* VLAN Frame */ - -/* Flow Control Counter Register */ -#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ -#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ - -/* Flow Control Status Register */ -#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ - -/* Receive Filter Control Register */ -#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ -#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ -#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ -#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ -#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ -#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ -#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ -#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ -#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ -#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ -#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ -#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ -#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ -#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ -#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ - -/* Interrupt Status/Enable/Clear/Set Registers */ -#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ -#define INT_RX_ERR 0x00000002 /* Receive Error */ -#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ -#define INT_RX_DONE 0x00000008 /* Receive Done */ -#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ -#define INT_TX_ERR 0x00000020 /* Transmit Error */ -#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ -#define INT_TX_DONE 0x00000080 /* Transmit Done */ -#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ -#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ - -/* Power Down Register */ -#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ - -/* RX Descriptor Control Word */ -#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ -#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ -#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define RINFO_SIZE 0x000007FF /* Data size in bytes */ -#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ -#define RINFO_VLAN 0x00080000 /* VLAN Frame */ -#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ -#define RINFO_MCAST 0x00200000 /* Multicast Frame */ -#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ -#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ -#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ -#define RINFO_LEN_ERR 0x02000000 /* Length Error */ -#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ -#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ -#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ -#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ -#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ - RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) - -/* TX Descriptor Control Word */ -#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ -#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ -#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ -#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ -#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ -#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ -#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ -#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ -#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ -#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ -#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ -#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier */ - -// prototypes -portBASE_TYPE vInitEMAC(void); -unsigned short ReadFrameBE_EMAC(void); -void vIncrementTxLength(unsigned long ulLength); -void CopyFromFrame_EMAC(void *Dest, unsigned short Size); -void DummyReadFrame_EMAC(unsigned short Size); -unsigned short StartReadFrame(void); -void EndReadFrame(void); -unsigned int CheckFrameReceived(void); -void vInitialiseSend(void); -unsigned int Rdy4Tx(void); -void vSendBufferToMAC(void); -void vEMACWaitForInput( void ); -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); - - -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings b/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings deleted file mode 100644 index 0d3c30cdd..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings +++ /dev/null @@ -1,35 +0,0 @@ -http_http "http://" -http_200 "200 " -http_301 "301 " -http_302 "302 " -http_get "GET " -http_10 "HTTP/1.0" -http_11 "HTTP/1.1" -http_content_type "content-type: " -http_texthtml "text/html" -http_location "location: " -http_host "host: " -http_crnl "\r\n" -http_index_html "/index.html" -http_404_html "/404.html" -http_referer "Referer:" -http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_content_type_plain "Content-type: text/plain\r\n\r\n" -http_content_type_html "Content-type: text/html\r\n\r\n" -http_content_type_css "Content-type: text/css\r\n\r\n" -http_content_type_text "Content-type: text/text\r\n\r\n" -http_content_type_png "Content-type: image/png\r\n\r\n" -http_content_type_gif "Content-type: image/gif\r\n\r\n" -http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" -http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" -http_html ".html" -http_shtml ".shtml" -http_htm ".htm" -http_css ".css" -http_png ".png" -http_gif ".gif" -http_jpg ".jpg" -http_text ".txt" -http_txt ".txt" - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.c b/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.c deleted file mode 100644 index ef7a41c7d..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.c +++ /dev/null @@ -1,102 +0,0 @@ -const char http_http[8] = -/* "http://" */ -{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; -const char http_200[5] = -/* "200 " */ -{0x32, 0x30, 0x30, 0x20, }; -const char http_301[5] = -/* "301 " */ -{0x33, 0x30, 0x31, 0x20, }; -const char http_302[5] = -/* "302 " */ -{0x33, 0x30, 0x32, 0x20, }; -const char http_get[5] = -/* "GET " */ -{0x47, 0x45, 0x54, 0x20, }; -const char http_10[9] = -/* "HTTP/1.0" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; -const char http_11[9] = -/* "HTTP/1.1" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; -const char http_content_type[15] = -/* "content-type: " */ -{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; -const char http_texthtml[10] = -/* "text/html" */ -{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_location[11] = -/* "location: " */ -{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; -const char http_host[7] = -/* "host: " */ -{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; -const char http_crnl[3] = -/* "\r\n" */ -{0xd, 0xa, }; -const char http_index_html[12] = -/* "/index.html" */ -{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_404_html[10] = -/* "/404.html" */ -{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_referer[9] = -/* "Referer:" */ -{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; -const char http_header_200[84] = -/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_header_404[91] = -/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_content_type_plain[29] = -/* "Content-type: text/plain\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_html[28] = -/* "Content-type: text/html\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_css [27] = -/* "Content-type: text/css\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_text[28] = -/* "Content-type: text/text\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_png [28] = -/* "Content-type: image/png\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_gif [28] = -/* "Content-type: image/gif\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_jpg [29] = -/* "Content-type: image/jpeg\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_binary[43] = -/* "Content-type: application/octet-stream\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; -const char http_html[6] = -/* ".html" */ -{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_shtml[7] = -/* ".shtml" */ -{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_htm[5] = -/* ".htm" */ -{0x2e, 0x68, 0x74, 0x6d, }; -const char http_css[5] = -/* ".css" */ -{0x2e, 0x63, 0x73, 0x73, }; -const char http_png[5] = -/* ".png" */ -{0x2e, 0x70, 0x6e, 0x67, }; -const char http_gif[5] = -/* ".gif" */ -{0x2e, 0x67, 0x69, 0x66, }; -const char http_jpg[5] = -/* ".jpg" */ -{0x2e, 0x6a, 0x70, 0x67, }; -const char http_text[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; -const char http_txt[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.h b/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.h deleted file mode 100644 index acbe7e17f..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/http-strings.h +++ /dev/null @@ -1,34 +0,0 @@ -extern const char http_http[8]; -extern const char http_200[5]; -extern const char http_301[5]; -extern const char http_302[5]; -extern const char http_get[5]; -extern const char http_10[9]; -extern const char http_11[9]; -extern const char http_content_type[15]; -extern const char http_texthtml[10]; -extern const char http_location[11]; -extern const char http_host[7]; -extern const char http_crnl[3]; -extern const char http_index_html[12]; -extern const char http_404_html[10]; -extern const char http_referer[9]; -extern const char http_header_200[84]; -extern const char http_header_404[91]; -extern const char http_content_type_plain[29]; -extern const char http_content_type_html[28]; -extern const char http_content_type_css [27]; -extern const char http_content_type_text[28]; -extern const char http_content_type_png [28]; -extern const char http_content_type_gif [28]; -extern const char http_content_type_jpg [29]; -extern const char http_content_type_binary[43]; -extern const char http_html[6]; -extern const char http_shtml[7]; -extern const char http_htm[5]; -extern const char http_css[5]; -extern const char http_png[5]; -extern const char http_gif[5]; -extern const char http_jpg[5]; -extern const char http_text[5]; -extern const char http_txt[5]; diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.c b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.c deleted file mode 100644 index 803b771e6..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2006, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ - * - */ - -#include "uip.h" -#include "psock.h" -#include "httpd.h" -#include "httpd-cgi.h" -#include "httpd-fs.h" - -#include -#include - -HTTPD_CGI_CALL(file, "file-stats", file_stats); -HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); -HTTPD_CGI_CALL(net, "net-stats", net_stats); -HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); -HTTPD_CGI_CALL(io, "led-io", led_io ); - - -static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; - -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -httpd_cgifunction -httpd_cgi(char *name) -{ - const struct httpd_cgi_call **f; - - /* Find the matching name in the table, return the function. */ - for(f = calls; *f != NULL; ++f) { - if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { - return (*f)->function; - } - } - return nullfunction; -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_file_stats(void *arg) -{ - char *f = (char *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -static unsigned short -generate_tcp_stats(void *arg) -{ - struct uip_conn *conn; - struct httpd_state *s = (struct httpd_state *)arg; - - conn = &uip_conns[s->count]; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "\r\n", - htons(conn->lport), - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & UIP_TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' '); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) -{ - - PSOCK_BEGIN(&s->sout); - - for(s->count = 0; s->count < UIP_CONNS; ++s->count) { - if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { - PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); - } - } - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_net_stats(void *arg) -{ - struct httpd_state *s = (struct httpd_state *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); -} - -static -PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - -#if UIP_STATISTICS - - for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); - ++s->count) { - PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); - } - -#endif /* UIP_STATISTICS */ - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -extern void vTaskList( signed char *pcWriteBuffer ); -static char cCountBuf[ 32 ]; -long lRefreshCount = 0; -static unsigned short -generate_rtos_stats(void *arg) -{ - lRefreshCount++; - sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); - vTaskList( uip_appdata ); - strcat( uip_appdata, cCountBuf ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - - -static -PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -char *pcStatus; -extern unsigned long uxParTestGetLED( unsigned long uxLED ); - -static unsigned short generate_io_state( void *arg ) -{ - if( uxParTestGetLED( 0 ) ) - { - pcStatus = "checked"; - } - else - { - pcStatus = ""; - } - - sprintf( uip_appdata, - "LED"\ - "

"\ - "", - pcStatus ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - -static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); - PSOCK_END(&s->sout); -} - -/** @} */ - - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.h b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.h deleted file mode 100644 index 7ae928321..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-cgi.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface header file - * \author - * Adam Dunkels - * - */ - - - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_CGI_H__ -#define __HTTPD_CGI_H__ - -#include "psock.h" -#include "httpd.h" - -typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); - -httpd_cgifunction httpd_cgi(char *name); - -struct httpd_cgi_call { - const char *name; - const httpd_cgifunction function; -}; - -/** - * \brief HTTPD CGI function declaration - * \param name The C variable name of the function - * \param str The string name of the function, used in the script file - * \param function A pointer to the function that implements it - * - * This macro is used for declaring a HTTPD CGI - * function. This function is then added to the list of - * HTTPD CGI functions with the httpd_cgi_add() function. - * - * \hideinitializer - */ -#define HTTPD_CGI_CALL(name, str, function) \ -static PT_THREAD(function(struct httpd_state *, char *)); \ -static const struct httpd_cgi_call name = {str, function} - -void httpd_cgi_init(void); -#endif /* __HTTPD_CGI_H__ */ - -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.c b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.c deleted file mode 100644 index dc4aef011..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ - -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-fsdata.h" - -#ifndef NULL -#define NULL 0 -#endif /* NULL */ - -#include "httpd-fsdata.c" - -#if HTTPD_FS_STATISTICS -static u16_t count[HTTPD_FS_NUMFILES]; -#endif /* HTTPD_FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -httpd_fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -httpd_fs_open(const char *name, struct httpd_fs_file *file) -{ -#if HTTPD_FS_STATISTICS - u16_t i = 0; -#endif /* HTTPD_FS_STATISTICS */ - struct httpd_fsdata_file_noconst *f; - - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#if HTTPD_FS_STATISTICS - ++count[i]; -#endif /* HTTPD_FS_STATISTICS */ - return 1; - } -#if HTTPD_FS_STATISTICS - ++i; -#endif /* HTTPD_FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_fs_init(void) -{ -#if HTTPD_FS_STATISTICS - u16_t i; - for(i = 0; i < HTTPD_FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* HTTPD_FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#if HTTPD_FS_STATISTICS -u16_t httpd_fs_count -(char *name) -{ - struct httpd_fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* HTTPD_FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.h b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.h deleted file mode 100644 index b594eea56..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FS_H__ -#define __HTTPD_FS_H__ - -#define HTTPD_FS_STATISTICS 1 - -struct httpd_fs_file { - char *data; - int len; -}; - -/* file must be allocated by caller and will be filled in - by the function. */ -int httpd_fs_open(const char *name, struct httpd_fs_file *file); - -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 -u16_t httpd_fs_count(char *name); -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ - -void httpd_fs_init(void); - -#endif /* __HTTPD_FS_H__ */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/404.html b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/404.html deleted file mode 100644 index 43e7f4cad..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/404.html +++ /dev/null @@ -1,8 +0,0 @@ - - -

-

404 - file not found

-

Go here instead.

-
- - \ No newline at end of file diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.html b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.html deleted file mode 100644 index 1d3bbeee1..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.html +++ /dev/null @@ -1,13 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -Loading index.shtml. Click here if not automatically redirected. - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.shtml b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.shtml deleted file mode 100644 index 1923ea762..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/index.shtml +++ /dev/null @@ -1,20 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Task statistics

-Page will refresh every 2 seconds.

-

Task          State  Priority  Stack	#
************************************************

-%! rtos-stats
-
- - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/io.shtml b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/io.shtml deleted file mode 100644 index 07554bb71..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/io.shtml +++ /dev/null @@ -1,28 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-LED and LCD IO
- -

- -Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". - - -

-
-%! led-io -

- - -

- - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/stats.shtml b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/stats.shtml deleted file mode 100644 index d762f40d8..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/stats.shtml +++ /dev/null @@ -1,41 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Network statistics

-
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
%! net-stats
-
- - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/tcp.shtml b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/tcp.shtml deleted file mode 100644 index 654d61f21..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fs/tcp.shtml +++ /dev/null @@ -1,21 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-
-

Network connections

-

- - -%! tcp-connections - - - - - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.c b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.c deleted file mode 100644 index a7fcfab5a..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.c +++ /dev/null @@ -1,470 +0,0 @@ -static const unsigned char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, - 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, - 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, - 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, - 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, - 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, - 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, - 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0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, - 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, - 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, - 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, - 0xa, 0xd, 0xa, 0}; - -const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; - -const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; - -const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; - -const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; - -#define HTTPD_FS_ROOT file_tcp_shtml - -#define HTTPD_FS_NUMFILES 6 diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.h b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.h deleted file mode 100644 index 52d35c265..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd-fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FSDATA_H__ -#define __HTTPD_FSDATA_H__ - -#include "uip.h" - -struct httpd_fsdata_file { - const struct httpd_fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -struct httpd_fsdata_file_noconst { - struct httpd_fsdata_file *next; - char *name; - char *data; - int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -#endif /* __HTTPD_FSDATA_H__ */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.c b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.c deleted file mode 100644 index 644cf16b7..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.c +++ /dev/null @@ -1,346 +0,0 @@ -/** - * \addtogroup apps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - - */ - -/** - * \file - * Web server - * \author - * Adam Dunkels - */ - - -/* - * Copyright (c) 2004, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-cgi.h" -#include "http-strings.h" - -#include - -#define STATE_WAITING 0 -#define STATE_OUTPUT 1 - -#define ISO_nl 0x0a -#define ISO_space 0x20 -#define ISO_bang 0x21 -#define ISO_percent 0x25 -#define ISO_period 0x2e -#define ISO_slash 0x2f -#define ISO_colon 0x3a - - -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_part_of_file(void *state) -{ - struct httpd_state *s = (struct httpd_state *)state; - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - memcpy(uip_appdata, s->file.data, s->len); - - return s->len; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - do { - PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); - s->file.len -= s->len; - s->file.data += s->len; - } while(s->file.len > 0); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_part_of_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND(&s->sout, s->file.data, s->len); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static void -next_scriptstate(struct httpd_state *s) -{ - char *p; - p = strchr(s->scriptptr, ISO_nl) + 1; - s->scriptlen -= (unsigned short)(p - s->scriptptr); - s->scriptptr = p; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_script(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->scriptpt); - - - while(s->file.len > 0) { - - /* Check if we should start executing a script. */ - if(*s->file.data == ISO_percent && - *(s->file.data + 1) == ISO_bang) { - s->scriptptr = s->file.data + 3; - s->scriptlen = s->file.len - 3; - if(*(s->scriptptr - 1) == ISO_colon) { - httpd_fs_open(s->scriptptr + 1, &s->file); - PT_WAIT_THREAD(&s->scriptpt, send_file(s)); - } else { - PT_WAIT_THREAD(&s->scriptpt, - httpd_cgi(s->scriptptr)(s, s->scriptptr)); - } - next_scriptstate(s); - - /* The script is over, so we reset the pointers and continue - sending the rest of the file. */ - s->file.data = s->scriptptr; - s->file.len = s->scriptlen; - } else { - /* See if we find the start of script marker in the block of HTML - to be sent. */ - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - - if(*s->file.data == ISO_percent) { - ptr = strchr(s->file.data + 1, ISO_percent); - } else { - ptr = strchr(s->file.data, ISO_percent); - } - if(ptr != NULL && - ptr != s->file.data) { - s->len = (int)(ptr - s->file.data); - if(s->len >= uip_mss()) { - s->len = uip_mss(); - } - } - PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); - s->file.data += s->len; - s->file.len -= s->len; - - } - } - - PT_END(&s->scriptpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) -{ - char *ptr; - - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND_STR(&s->sout, statushdr); - - ptr = strrchr(s->filename, ISO_period); - if(ptr == NULL) { - PSOCK_SEND_STR(&s->sout, http_content_type_binary); - } else if(strncmp(http_html, ptr, 5) == 0 || - strncmp(http_shtml, ptr, 6) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_html); - } else if(strncmp(http_css, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_css); - } else if(strncmp(http_png, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_png); - } else if(strncmp(http_gif, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_gif); - } else if(strncmp(http_jpg, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_jpg); - } else { - PSOCK_SEND_STR(&s->sout, http_content_type_plain); - } - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_output(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->outputpt); - - if(!httpd_fs_open(s->filename, &s->file)) { - httpd_fs_open(http_404_html, &s->file); - strcpy(s->filename, http_404_html); - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_404)); - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_200)); - ptr = strchr(s->filename, ISO_period); - if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { - PT_INIT(&s->scriptpt); - PT_WAIT_THREAD(&s->outputpt, handle_script(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } - } - PSOCK_CLOSE(&s->sout); - PT_END(&s->outputpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_input(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sin); - - PSOCK_READTO(&s->sin, ISO_space); - - - if(strncmp(s->inputbuf, http_get, 4) != 0) { - PSOCK_CLOSE_EXIT(&s->sin); - } - PSOCK_READTO(&s->sin, ISO_space); - - if(s->inputbuf[0] != ISO_slash) { - PSOCK_CLOSE_EXIT(&s->sin); - } - - if(s->inputbuf[1] == ISO_space) { - strncpy(s->filename, http_index_html, sizeof(s->filename)); - } else { - - s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; - - /* Process any form input being sent to the server. */ - { - extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); - vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); - } - - strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); - } - - /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ - - s->state = STATE_OUTPUT; - - while(1) { - PSOCK_READTO(&s->sin, ISO_nl); - - if(strncmp(s->inputbuf, http_referer, 8) == 0) { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; - /* httpd_log(&s->inputbuf[9]);*/ - } - } - - PSOCK_END(&s->sin); -} -/*---------------------------------------------------------------------------*/ -static void -handle_connection(struct httpd_state *s) -{ - handle_input(s); - if(s->state == STATE_OUTPUT) { - handle_output(s); - } -} -/*---------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); - - if(uip_closed() || uip_aborted() || uip_timedout()) { - } else if(uip_connected()) { - PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); - PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); - PT_INIT(&s->outputpt); - s->state = STATE_WAITING; - /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ - s->timer = 0; - handle_connection(s); - } else if(s != NULL) { - if(uip_poll()) { - ++s->timer; - if(s->timer >= 20) { - uip_abort(); - } - } else { - s->timer = 0; - } - handle_connection(s); - } else { - uip_abort(); - } -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the web server - * - * This function initializes the web server and should be - * called at system boot-up. - */ -void -httpd_init(void) -{ - uip_listen(HTONS(80)); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.h b/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.h deleted file mode 100644 index 7f7a6666e..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/httpd.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2005, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -#include "psock.h" -#include "httpd-fs.h" - -struct httpd_state { - unsigned char timer; - struct psock sin, sout; - struct pt outputpt, scriptpt; - char inputbuf[50]; - char filename[20]; - char state; - struct httpd_fs_file file; - int len; - char *scriptptr; - int scriptlen; - - unsigned short count; -}; - -void httpd_init(void); -void httpd_appcall(void); - -void httpd_log(char *msg); -void httpd_log_file(u16_t *requester, char *file); - -#endif /* __HTTPD_H__ */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/makefsdata b/Demo/CORTEX_LM3S6965_IAR/webserver/makefsdata deleted file mode 100644 index 8d2715a8a..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/makefsdata +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> httpd-fsdata.c"); - -chdir("httpd-fs"); - -opendir(DIR, "."); -@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); -closedir(DIR); - -foreach $file (@files) { - - if(-d $file && $file !~ /^\./) { - print "Processing directory $file\n"; - opendir(DIR, $file); - @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); - closedir(DIR); - printf "Adding files @newfiles\n"; - @files = (@files, map { $_ = "$file/$_" } @newfiles); - next; - } -} - -foreach $file (@files) { - if(-f $file) { - - print "Adding file $file\n"; - - open(FILE, $file) || die "Could not open file $file\n"; - - $file =~ s-^-/-; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - # for AVR, add PROGMEM here - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "0};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@pfiles, $file); - } -} - -for($i = 0; $i < @fvars; $i++) { - $file = $pfiles[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/makestrings b/Demo/CORTEX_LM3S6965_IAR/webserver/makestrings deleted file mode 100644 index 8a13c6d29..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/makestrings +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl - - -sub stringify { - my $name = shift(@_); - open(OUTPUTC, "> $name.c"); - open(OUTPUTH, "> $name.h"); - - open(FILE, "$name"); - - while() { - if(/(.+) "(.+)"/) { - $var = $1; - $data = $2; - - $datan = $data; - $datan =~ s/\\r/\r/g; - $datan =~ s/\\n/\n/g; - $datan =~ s/\\01/\01/g; - $datan =~ s/\\0/\0/g; - - printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); - printf(OUTPUTC "/* \"$data\" */\n"); - printf(OUTPUTC "{"); - for($j = 0; $j < length($datan); $j++) { - printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); - } - printf(OUTPUTC "};\n"); - - printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); - - } - } - close(OUTPUTC); - close(OUTPUTH); -} -stringify("http-strings"); - -exit 0; - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/uIP_Task.c b/Demo/CORTEX_LM3S6965_IAR/webserver/uIP_Task.c deleted file mode 100644 index 55cc8e525..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/uIP_Task.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -#include "lcd_message.h" - -/* uip includes. */ -#include "hw_types.h" - -#include "uip.h" -#include "uip_arp.h" -#include "httpd.h" -#include "timer.h" -#include "clock-arch.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "hw_memmap.h" -#include "lmi_flash.h" - -/* Demo includes. */ -#include "emac.h" -#include "partest.h" - -/*-----------------------------------------------------------*/ - -/* IP address configuration. */ -#define uipIP_ADDR0 172 -#define uipIP_ADDR1 25 -#define uipIP_ADDR2 218 -#define uipIP_ADDR3 9 - -/* How long to wait before attempting to connect the MAC again. */ -#define uipINIT_WAIT 100 - -/* Shortcut to the header within the Rx buffer. */ -#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) - -/* Standard constant. */ -#define uipTOTAL_FRAME_HEADER_SIZE 54 - -/*-----------------------------------------------------------*/ - -/* - * Send the uIP buffer to the MAC. - */ -static void prvENET_Send(void); - -/* - * Setup the MAC address in the MAC itself, and in the uIP stack. - */ -static void prvSetMACAddress( void ); - -/* - * Port functions required by the uIP stack. - */ -void clock_init( void ); -clock_time_t clock_time( void ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used by the ISR to wake the uIP task. */ -extern xSemaphoreHandle xEMACSemaphore; - -/*-----------------------------------------------------------*/ - -void clock_init(void) -{ - /* This is done when the scheduler starts. */ -} -/*-----------------------------------------------------------*/ - -clock_time_t clock_time( void ) -{ - return xTaskGetTickCount(); -} -/*-----------------------------------------------------------*/ - -void vuIP_Task( void *pvParameters ) -{ -portBASE_TYPE i; -uip_ipaddr_t xIPAddr; -struct timer periodic_timer, arp_timer; -extern void ( vEMAC_ISR )( void ); - - /* Create the semaphore used by the ISR to wake this task. */ - vSemaphoreCreateBinary( xEMACSemaphore ); - - /* Initialise the uIP stack. */ - timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); - timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); - uip_init(); - uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); - uip_sethostaddr( xIPAddr ); - httpd_init(); - - while( vInitEMAC() != pdPASS ) - { - vTaskDelay( uipINIT_WAIT ); - } - prvSetMACAddress(); - - - for( ;; ) - { - /* Is there received data ready to be processed? */ - uip_len = uiGetEMACRxData( uip_buf ); - - if( uip_len > 0 ) - { - /* Standard uIP loop taken from the uIP manual. */ - - if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) - { - uip_arp_ipin(); - uip_input(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) - { - uip_arp_arpin(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - prvENET_Send(); - } - } - } - else - { - if( timer_expired( &periodic_timer ) ) - { - timer_reset( &periodic_timer ); - for( i = 0; i < UIP_CONNS; i++ ) - { - uip_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - - /* Call the ARP timer function every 10 seconds. */ - if( timer_expired( &arp_timer ) ) - { - timer_reset( &arp_timer ); - uip_arp_timer(); - } - } - else - { - /* We did not receive a packet, and there was no periodic - processing to perform. Block for a fixed period. If a packet - is received during this period we will be woken by the ISR - giving us the Semaphore. */ - xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvENET_Send(void) -{ - vInitialiseSend(); - vIncrementTxLength( uip_len ); - vSendBufferToMAC(); -} -/*-----------------------------------------------------------*/ - -static void prvSetMACAddress( void ) -{ -unsigned portLONG ulUser0, ulUser1; -unsigned char pucMACArray[8]; -struct uip_eth_addr xAddr; - - /* Get the device MAC address from flash */ - FlashUserGet(&ulUser0, &ulUser1); - - /* Convert the MAC address from flash into sequence of bytes. */ - pucMACArray[0] = ((ulUser0 >> 0) & 0xff); - pucMACArray[1] = ((ulUser0 >> 8) & 0xff); - pucMACArray[2] = ((ulUser0 >> 16) & 0xff); - pucMACArray[3] = ((ulUser1 >> 0) & 0xff); - pucMACArray[4] = ((ulUser1 >> 8) & 0xff); - pucMACArray[5] = ((ulUser1 >> 16) & 0xff); - - /* Program the MAC address. */ - EthernetMACAddrSet(ETH_BASE, pucMACArray); - - xAddr.addr[ 0 ] = pucMACArray[0]; - xAddr.addr[ 1 ] = pucMACArray[1]; - xAddr.addr[ 2 ] = pucMACArray[2]; - xAddr.addr[ 3 ] = pucMACArray[3]; - xAddr.addr[ 4 ] = pucMACArray[4]; - xAddr.addr[ 5 ] = pucMACArray[5]; - uip_setethaddr( xAddr ); -} -/*-----------------------------------------------------------*/ - -void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) -{ -char *c, *pcText; -static portCHAR cMessageForDisplay[ 32 ]; -extern xQueueHandle xOLEDQueue; -xOLEDMessage xOLEDMessage; - - /* Process the form input sent by the IO page of the served HTML. */ - - c = strstr( pcInputString, "?" ); - - if( c ) - { - /* Turn LED's on or off in accordance with the check box status. */ - if( strstr( c, "LED0=1" ) != NULL ) - { - vParTestSetLED( 0, 1 ); - } - else - { - vParTestSetLED( 0, 0 ); - } - - /* Find the start of the text to be displayed on the LCD. */ - pcText = strstr( c, "LCD=" ); - pcText += strlen( "LCD=" ); - - /* Terminate the file name for further processing within uIP. */ - *c = 0x00; - - /* Terminate the LCD string. */ - c = strstr( pcText, " " ); - if( c != NULL ) - { - *c = 0x00; - } - - /* Add required spaces. */ - while( ( c = strstr( pcText, "+" ) ) != NULL ) - { - *c = ' '; - } - - /* Write the message to the LCD. */ - strcpy( cMessageForDisplay, pcText ); - xOLEDMessage.pcMessage = cMessageForDisplay; - xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/uip-conf.h b/Demo/CORTEX_LM3S6965_IAR/webserver/uip-conf.h deleted file mode 100644 index 455540da1..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/uip-conf.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1480 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#define UIP_CONF_EXTERNAL_BUFFER - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_IAR/webserver/webserver.h b/Demo/CORTEX_LM3S6965_IAR/webserver/webserver.h deleted file mode 100644 index 1acb290b8..000000000 --- a/Demo/CORTEX_LM3S6965_IAR/webserver/webserver.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ -#ifndef __WEBSERVER_H__ -#define __WEBSERVER_H__ - -#include "httpd.h" - -typedef struct httpd_state uip_tcp_appstate_t; -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - - -#endif /* __WEBSERVER_H__ */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S6965_KEIL/FreeRTOSConfig.h deleted file mode 100644 index b97aac5b8..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/FreeRTOSConfig.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#define configKERNEL_INTERRUPT_PRIORITY 255 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/DriverLib.lib b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/DriverLib.lib deleted file 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8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & UIP_TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' '); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) -{ - - PSOCK_BEGIN(&s->sout); - - for(s->count = 0; s->count < UIP_CONNS; ++s->count) { - if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { - PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); - } - } - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_net_stats(void *arg) -{ - struct httpd_state *s = (struct httpd_state *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); -} - -static -PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - -#if UIP_STATISTICS - - for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); - ++s->count) { - PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); - } - -#endif /* UIP_STATISTICS */ - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -extern void vTaskList( signed char *pcWriteBuffer ); -static char cCountBuf[ 32 ]; -long lRefreshCount = 0; -static unsigned short -generate_rtos_stats(void *arg) -{ - lRefreshCount++; - sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); - vTaskList( uip_appdata ); - strcat( uip_appdata, cCountBuf ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - - -static -PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -char *pcStatus; -extern unsigned long uxParTestGetLED( unsigned long uxLED ); - -static unsigned short generate_io_state( void *arg ) -{ - if( uxParTestGetLED( 0 ) ) - { - pcStatus = "checked"; - } - else - { - pcStatus = ""; - } - - sprintf( uip_appdata, - "LED"\ - "

"\ - "", - pcStatus ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - -static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); - PSOCK_END(&s->sout); -} - -/** @} */ - - - - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.h deleted file mode 100644 index 7ae928321..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface header file - * \author - * Adam Dunkels - * - */ - - - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_CGI_H__ -#define __HTTPD_CGI_H__ - -#include "psock.h" -#include "httpd.h" - -typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); - -httpd_cgifunction httpd_cgi(char *name); - -struct httpd_cgi_call { - const char *name; - const httpd_cgifunction function; -}; - -/** - * \brief HTTPD CGI function declaration - * \param name The C variable name of the function - * \param str The string name of the function, used in the script file - * \param function A pointer to the function that implements it - * - * This macro is used for declaring a HTTPD CGI - * function. This function is then added to the list of - * HTTPD CGI functions with the httpd_cgi_add() function. - * - * \hideinitializer - */ -#define HTTPD_CGI_CALL(name, str, function) \ -static PT_THREAD(function(struct httpd_state *, char *)); \ -static const struct httpd_cgi_call name = {str, function} - -void httpd_cgi_init(void); -#endif /* __HTTPD_CGI_H__ */ - -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.c deleted file mode 100644 index dc4aef011..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ - -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-fsdata.h" - -#ifndef NULL -#define NULL 0 -#endif /* NULL */ - -#include "httpd-fsdata.c" - -#if HTTPD_FS_STATISTICS -static u16_t count[HTTPD_FS_NUMFILES]; -#endif /* HTTPD_FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -httpd_fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -httpd_fs_open(const char *name, struct httpd_fs_file *file) -{ -#if HTTPD_FS_STATISTICS - u16_t i = 0; -#endif /* HTTPD_FS_STATISTICS */ - struct httpd_fsdata_file_noconst *f; - - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#if HTTPD_FS_STATISTICS - ++count[i]; -#endif /* HTTPD_FS_STATISTICS */ - return 1; - } -#if HTTPD_FS_STATISTICS - ++i; -#endif /* HTTPD_FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_fs_init(void) -{ -#if HTTPD_FS_STATISTICS - u16_t i; - for(i = 0; i < HTTPD_FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* HTTPD_FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#if HTTPD_FS_STATISTICS -u16_t httpd_fs_count -(char *name) -{ - struct httpd_fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* HTTPD_FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.h deleted file mode 100644 index b594eea56..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FS_H__ -#define __HTTPD_FS_H__ - -#define HTTPD_FS_STATISTICS 1 - -struct httpd_fs_file { - char *data; - int len; -}; - -/* file must be allocated by caller and will be filled in - by the function. */ -int httpd_fs_open(const char *name, struct httpd_fs_file *file); - -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 -u16_t httpd_fs_count(char *name); -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ - -void httpd_fs_init(void); - -#endif /* __HTTPD_FS_H__ */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/404.html b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/404.html deleted file mode 100644 index 43e7f4cad..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/404.html +++ /dev/null @@ -1,8 +0,0 @@ - - -

-

404 - file not found

-

Go here instead.

-
- - \ No newline at end of file diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.html b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.html deleted file mode 100644 index 1d3bbeee1..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.html +++ /dev/null @@ -1,13 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -Loading index.shtml. Click here if not automatically redirected. - - - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.shtml b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.shtml deleted file mode 100644 index 1923ea762..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/index.shtml +++ /dev/null @@ -1,20 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Task statistics

-Page will refresh every 2 seconds.

-

Task          State  Priority  Stack	#
************************************************

-%! rtos-stats
-
- - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/io.shtml b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/io.shtml deleted file mode 100644 index 07554bb71..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/io.shtml +++ /dev/null @@ -1,28 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-LED and LCD IO
- -

- -Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". - - -

-
-%! led-io -

- - -

- - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/stats.shtml b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/stats.shtml deleted file mode 100644 index d762f40d8..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/stats.shtml +++ /dev/null @@ -1,41 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-

-

Network statistics

-
LocalRemoteStateRetransmissionsTimerFlags
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zIy%&5aa0Tn&R9ke+q;Mq`)m{~GC{%7lmtXMRSneR=)LzzSHoczuiBsOw_j0r*O- zTM~zNxJPptcWPzKd$Z=GpIRB6E#Smu1l@F@iM#609A0AE?RXzI=6&)2MkF~Xgz_9f zJH@F=_=4E!fK=QOKb0zqG3U%ZkI2FLenls?IFHe8DY=l5{fD&~t6~d`en9%PlK^k* zIZuKpCR4BDKn+jlkVjd{E8FP_54m$Di9`&ejruJ8k61(ZvN?n<1#Nm09oYko>JUQw zpl>;KSP37Z03AcXf`^HlG}#9wH>7I|LMw~-g0nOpC!k|a*T1{#rY%C{hJ%o?e>eyk z2ytJmWzE+_TD2t)HMQm=+r$xUp0tM?8! zWg3(_!~Ga38u_!!Ojd$Yl;3K+mhza~L`s|IeB)DvQc>d^*{q4)NxrOKp@r!Vv So5Wibyj|!dT&> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - big endian/little endian byte swapping macros for -// 16-bit (short) values -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EthernetInit(unsigned long ulBase); -extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); -extern unsigned long EthernetConfigGet(unsigned long ulBase); -extern void EthernetMACAddrSet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetMACAddrGet(unsigned long ulBase, - unsigned char *pucMACAddr); -extern void EthernetEnable(unsigned long ulBase); -extern void EthernetDisable(unsigned long ulBase); -extern tBoolean EthernetPacketAvail(unsigned long ulBase); -extern tBoolean EthernetSpaceAvail(unsigned long ulBase); -extern long EthernetPacketNonBlockingGet(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketNonBlockingPut(unsigned long ulBase, - unsigned char *pucBuf, - long lBufLen); -extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, - long lBufLen); -extern void EthernetIntRegister(unsigned long ulBase, - void (*pfnHandler)(void)); -extern void EthernetIntUnregister(unsigned long ulBase); -extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, - unsigned long ulData); -extern unsigned long EthernetPHYRead(unsigned long ulBase, - unsigned char ucRegAddr); - -#ifdef __cplusplus -} -#endif - -#endif // __ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/gpio.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/gpio.h deleted file mode 100644 index 6e74f9d4f..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/gpio.h +++ /dev/null @@ -1,138 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hibernate.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hibernate.h deleted file mode 100644 index 69a8c144a..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hibernate.h +++ /dev/null @@ -1,107 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HIBERNATE_H__ -#define __HIBERNATE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros needed for selecting the clock source for HibernateClockSelect() -// -//***************************************************************************** -#define HIBERNATE_CLOCK_SEL_RAW 0x04 -#define HIBERNATE_CLOCK_SEL_DIV128 0x00 - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x10 -#define HIBERNATE_WAKE_RTC 0x08 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT 0x20 -#define HIBERNATE_LOW_BAT_ABORT 0xA0 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_PIN_WAKE 0x08 -#define HIBERNATE_INT_LOW_BAT 0x04 -#define HIBERNATE_INT_RTC_MATCH_0 0x01 -#define HIBERNATE_INT_RTC_MATCH_1 0x02 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateEnable(void); -extern void HibernateDisable(void); -extern void HibernateClockSelect(unsigned long ulClockInput); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(unsigned long ulWakeFlags); -extern unsigned long HibernateWakeGet(void); -extern void HibernateLowBatSet(unsigned long ulLowBatFlags); -extern unsigned long HibernateLowBatGet(void); -extern void HibernateRTCSet(unsigned long ulRTCValue); -extern unsigned long HibernateRTCGet(void); -extern void HibernateRTCMatch0Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch0Get(void); -extern void HibernateRTCMatch1Set(unsigned long ulMatch); -extern unsigned long HibernateRTCMatch1Get(void); -extern void HibernateRTCTrimSet(unsigned long ulTrim); -extern unsigned long HibernateRTCTrimGet(void); -extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); -extern void HibernateRequest(void); -extern void HibernateIntEnable(unsigned long ulIntFlags); -extern void HibernateIntDisable(unsigned long ulIntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern unsigned long HibernateIntStatus(tBoolean bMasked); -extern void HibernateIntClear(unsigned long ulIntFlags); -extern unsigned int HibernateIsActive(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_adc.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_adc.h deleted file mode 100644 index 932d3f26e..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_can.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_can.h deleted file mode 100644 index 02f7b7465..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_can.h +++ /dev/null @@ -1,379 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the can. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following define the offsets of the can registers. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // Control register -#define CAN_O_STS 0x00000004 // Status register -#define CAN_O_ERR 0x00000008 // Error register -#define CAN_O_BIT 0x0000000C // Bit Timing register -#define CAN_O_INT 0x00000010 // Interrupt register -#define CAN_O_TST 0x00000014 // Test register -#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register -#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. -#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. -#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register -#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register -#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. -#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. -#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. -#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register -#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register -#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register -#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register -#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. -#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. -#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register -#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register -#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. -#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. -#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. -#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register -#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register -#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register -#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register -#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register -#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register -#define CAN_O_NWDA1 0x00000120 // New Data 1 register -#define CAN_O_NWDA2 0x00000124 // New Data 2 register -#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. -#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. -#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. -#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. - -//***************************************************************************** -// -// The following define the reset values of the can registers. -// -//***************************************************************************** -#define CAN_RV_CTL 0x00000001 -#define CAN_RV_STS 0x00000000 -#define CAN_RV_ERR 0x00000000 -#define CAN_RV_BIT 0x00002301 -#define CAN_RV_INT 0x00000000 -#define CAN_RV_TST 0x00000000 -#define CAN_RV_BRPE 0x00000000 -#define CAN_RV_IF1CRQ 0x00000001 -#define CAN_RV_IF1CMSK 0x00000000 -#define CAN_RV_IF1MSK1 0x0000FFFF -#define CAN_RV_IF1MSK2 0x0000FFFF -#define CAN_RV_IF1ARB1 0x00000000 -#define CAN_RV_IF1ARB2 0x00000000 -#define CAN_RV_IF1MCTL 0x00000000 -#define CAN_RV_IF1DA1 0x00000000 -#define CAN_RV_IF1DA2 0x00000000 -#define CAN_RV_IF1DB1 0x00000000 -#define CAN_RV_IF1DB2 0x00000000 -#define CAN_RV_IF2CRQ 0x00000001 -#define CAN_RV_IF2CMSK 0x00000000 -#define CAN_RV_IF2MSK1 0x0000FFFF -#define CAN_RV_IF2MSK2 0x0000FFFF -#define CAN_RV_IF2ARB1 0x00000000 -#define CAN_RV_IF2ARB2 0x00000000 -#define CAN_RV_IF2MCTL 0x00000000 -#define CAN_RV_IF2DA1 0x00000000 -#define CAN_RV_IF2DA2 0x00000000 -#define CAN_RV_IF2DB1 0x00000000 -#define CAN_RV_IF2DB2 0x00000000 -#define CAN_RV_TXRQ1 0x00000000 -#define CAN_RV_TXRQ2 0x00000000 -#define CAN_RV_NWDA1 0x00000000 -#define CAN_RV_NWDA2 0x00000000 -#define CAN_RV_MSGINT1 0x00000000 -#define CAN_RV_MSGINT2 0x00000000 -#define CAN_RV_MSGVAL1 0x00000000 -#define CAN_RV_MSGVAL2 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test mode enable -#define CAN_CTL_CCE 0x00000040 // Configuration change enable -#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission -#define CAN_CTL_EIE 0x00000008 // Error interrupt enable -#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable -#define CAN_CTL_IE 0x00000002 // Module interrupt enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following define the bit fields in the CAN_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus Off status -#define CAN_STS_EWARN 0x00000040 // Error Warning status -#define CAN_STS_EPASS 0x00000020 // Error Passive status -#define CAN_STS_RXOK 0x00000010 // Received Message Successful -#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful -#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error -#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error -#define CAN_STS_LEC_ACK 0x00000003 // Ack error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error -#define CAN_STS_LEC_CRC 0x00000006 // CRC error - -//***************************************************************************** -// -// The following define the bit fields in the CAN_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Receive error passive status -#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status -#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos -#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status -#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point -#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point -#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width -#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler - -//***************************************************************************** -// -// The following define the bit fields in the CAN_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // CAN_RX pin status -#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin -#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX -#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX -#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX -#define CAN_TST_LBACK 0x00000010 // Loop back mode -#define CAN_TST_SILENT 0x00000008 // Silent mode -#define CAN_TST_BASIC 0x00000004 // Basic mode - -//***************************************************************************** -// -// The following define the bit fields in the CAN_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status -#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read -#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit -#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) -#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) -#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 -#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier -#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction -#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB1_ID 0x0000FFFF // Identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid -#define CAN_IFARB2_XTD 0x00004000 // Extended identifier -#define CAN_IFARB2_DIR 0x00002000 // Message direction -#define CAN_IFARB2_ID 0x00001FFF // Message identifier - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data -#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost -#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending -#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask -#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable -#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable -#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable -#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request -#define CAN_IFMCTL_EOB 0x00000080 // End of buffer -#define CAN_IFMCTL_DLC 0x0000000F // Data length code - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 -// registers. -// Note: All bits may not be available in all registers -// -//***************************************************************************** -#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT1 register. -// -//***************************************************************************** -#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGINT2 register. -// -//***************************************************************************** -#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL1 register. -// -//***************************************************************************** -#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits - -//***************************************************************************** -// -// The following define the bit fields in the CAN_MSGVAL2 register. -// -//***************************************************************************** -#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits - -#endif // __HW_CAN_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_comp.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_comp.h deleted file mode 100644 index d8b355ea9..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ethernet.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ethernet.h deleted file mode 100644 index 7a8d224cd..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ethernet.h +++ /dev/null @@ -1,205 +0,0 @@ -//***************************************************************************** -// -// hw_ethernet.h - Macros used when accessing the ethernet hardware. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ETHERNET_H__ -#define __HW_ETHERNET_H__ - -//***************************************************************************** -// -// The following define the offsets of the MAC registers in the Ethernet -// Controller. -// -//***************************************************************************** -#define MAC_O_IS 0x00000000 // Interrupt Status Register -#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register -#define MAC_O_IM 0x00000004 // Interrupt Mask Register -#define MAC_O_RCTL 0x00000008 // Receive Control Register -#define MAC_O_TCTL 0x0000000C // Transmit Control Register -#define MAC_O_DATA 0x00000010 // Data Register -#define MAC_O_IA0 0x00000014 // Individual Address Register 0 -#define MAC_O_IA1 0x00000018 // Individual Address Register 1 -#define MAC_O_THR 0x0000001C // Threshold Register -#define MAC_O_MCTL 0x00000020 // Management Control Register -#define MAC_O_MDV 0x00000024 // Management Divider Register -#define MAC_O_MADD 0x00000028 // Management Address Register -#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg -#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg -#define MAC_O_NP 0x00000034 // Number of Packets Register -#define MAC_O_TR 0x00000038 // Transmission Request Register - -//***************************************************************************** -// -// The following define the reset values of the MAC registers. -// -//***************************************************************************** -#define MAC_RV_IS 0x00000000 -#define MAC_RV_IACK 0x00000000 -#define MAC_RV_IM 0x0000007F -#define MAC_RV_RCTL 0x00000008 -#define MAC_RV_TCTL 0x00000000 -#define MAC_RV_DATA 0x00000000 -#define MAC_RV_IA0 0x00000000 -#define MAC_RV_IA1 0x00000000 -#define MAC_RV_THR 0x0000003F -#define MAC_RV_MCTL 0x00000000 -#define MAC_RV_MDV 0x00000080 -#define MAC_RV_MADD 0x00000000 -#define MAC_RV_MTXD 0x00000000 -#define MAC_RV_MRXD 0x00000000 -#define MAC_RV_NP 0x00000000 -#define MAC_RV_TR 0x00000000 - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IS register. -// -//***************************************************************************** -#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt -#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete -#define MAC_IS_RXER 0x00000010 // RX Error -#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun -#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy -#define MAC_IS_TXER 0x00000002 // TX Error -#define MAC_IS_RXINT 0x00000001 // RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IACK register. -// -//***************************************************************************** -#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt -#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete -#define MAC_IACK_RXER 0x00000010 // Clear RX Error -#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun -#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy -#define MAC_IACK_TXER 0x00000002 // Clear TX Error -#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IM register. -// -//***************************************************************************** -#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt -#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete -#define MAC_IM_RXERM 0x00000010 // Mask RX Error -#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun -#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy -#define MAC_IM_TXERM 0x00000002 // Mask TX Error -#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available - -//***************************************************************************** -// -// The following define the bit fields in the MAC_RCTL register. -// -//***************************************************************************** -#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO -#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC -#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode -#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets -#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TCTL register. -// -//***************************************************************************** -#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode -#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation -#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding -#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA0 register. -// -//***************************************************************************** -#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address -#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address -#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address -#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_IA1 register. -// -//***************************************************************************** -#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address -#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXTH register. -// -//***************************************************************************** -#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MCTL register. -// -//***************************************************************************** -#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction -#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write -#define MAC_MCTL_START 0x00000001 // Start MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MDV register. -// -//***************************************************************************** -#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MTXD register. -// -//***************************************************************************** -#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction - -//***************************************************************************** -// -// The following define the bit fields in the MAC_MRXD register. -// -//***************************************************************************** -#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. - -//***************************************************************************** -// -// The following define the bit fields in the MAC_NP register. -// -//***************************************************************************** -#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO - -//***************************************************************************** -// -// The following define the bit fields in the MAC_TXRQ register. -// -//***************************************************************************** -#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission - -#endif // __HW_ETHERNET_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_flash.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_flash.h deleted file mode 100644 index c5bea3b26..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_flash.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register -#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 -#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 -#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 -#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 -#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 -#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 -#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 -#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_gpio.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_gpio.h deleted file mode 100644 index 3596325a7..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_gpio.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_LOCK 0x00000520 // Lock register. -#define GPIO_O_CR 0x00000524 // Commit register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the GPIO_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked -#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked -#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_LOCK 0x00000001 // Lock register RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_hibernate.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_hibernate.h deleted file mode 100644 index ee730d4c5..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_hibernate.h +++ /dev/null @@ -1,145 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following define the addresses of the hibernation module registers. -// -//***************************************************************************** -#define HIB_RTCC 0x400fc000 // Hibernate RTC counter -#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 -#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 -#define HIB_RTCLD 0x400fc00C // Hibernate RTC load -#define HIB_CTL 0x400fc010 // Hibernate RTC control -#define HIB_IM 0x400fc014 // Hibernate interrupt mask -#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status -#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat -#define HIB_IC 0x400fc020 // Hibernate interrupt clear -#define HIB_RTCT 0x400fc024 // Hibernate RTC trim -#define HIB_DATA 0x400fc030 // Hibernate data area -#define HIB_DATA_END 0x400fc130 // end of data area, exclusive - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC counter register. -// -//***************************************************************************** -#define HIB_RTCC_MASK 0xffffffff // RTC counter mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 0 register. -// -//***************************************************************************** -#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC match 1 register. -// -//***************************************************************************** -#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC load register. -// -//***************************************************************************** -#define HIB_RTCLD_MASK 0xffffffff // RTC load mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate control register -// -//***************************************************************************** -#define HIB_CTL_VABORT 0x00000080 // low bat abort -#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator -#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect -#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin -#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match -#define HIB_CTL_CLKSEL 0x00000004 // clock input selection -#define HIB_CTL_HIBREQ 0x00000002 // request hibernation -#define HIB_CTL_RTCEN 0x00000001 // RTC enable - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt mask reg. -// -//***************************************************************************** -#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate raw interrupt status. -// -//***************************************************************************** -#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate masked int status. -// -//***************************************************************************** -#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt -#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate interrupt clear reg. -// -//***************************************************************************** -#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt -#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt -#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt -#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate RTC trim register. -// -//***************************************************************************** -#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask - -//***************************************************************************** -// -// The following define the bit fields in the Hibernate data register. -// -//***************************************************************************** -#define HIB_DATA_MASK 0xffffffff // NV memory data mask - -#endif // __HW_HIBERNATE_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_i2c.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_i2c.h deleted file mode 100644 index b90edb7df..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ints.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ints.h deleted file mode 100644 index d2df4ee5b..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_SSI0 23 // SSI0 Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_I2C0 24 // I2C0 Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_QEI0 29 // Quadrature Encoder 0 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 Rx and Tx -#define INT_SSI1 50 // SSI1 Rx and Tx -#define INT_TIMER3A 51 // Timer 3 subtimer A -#define INT_TIMER3B 52 // Timer 3 subtimer B -#define INT_I2C1 53 // I2C1 Master and Slave -#define INT_QEI1 54 // Quadrature Encoder 1 -#define INT_CAN0 55 // CAN0 -#define INT_CAN1 56 // CAN1 -#define INT_ETH 58 // Ethernet -#define INT_HIBERNATE 59 // Hibernation module - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 60 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_memmap.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_memmap.h deleted file mode 100644 index 8ae2a06cd..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_memmap.h +++ /dev/null @@ -1,80 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master -#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave -#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master -#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define ETH_BASE 0x40048000 // Ethernet -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_nvic.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_nvic.h deleted file mode 100644 index 68c8d7c7f..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_nvic.h +++ /dev/null @@ -1,1050 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register -#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register -#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable -#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable -#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable -#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable -#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable -#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable -#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable -#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend -#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend -#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend -#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend -#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend -#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend -#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active -#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active -#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active -#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask -#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask -#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask -#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask -#define NVIC_PRI8_INT35_S 24 -#define NVIC_PRI8_INT34_S 16 -#define NVIC_PRI8_INT33_S 8 -#define NVIC_PRI8_INT32_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask -#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask -#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask -#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask -#define NVIC_PRI9_INT39_S 24 -#define NVIC_PRI9_INT38_S 16 -#define NVIC_PRI9_INT37_S 8 -#define NVIC_PRI9_INT36_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask -#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask -#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask -#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask -#define NVIC_PRI10_INT43_S 24 -#define NVIC_PRI10_INT42_S 16 -#define NVIC_PRI10_INT41_S 8 -#define NVIC_PRI10_INT40_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_pwm.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_pwm.h deleted file mode 100644 index 53609c6f9..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_qei.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_qei.h deleted file mode 100644 index 6d988ba95..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ssi.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ssi.h deleted file mode 100644 index 2af758095..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_sysctl.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_sysctl.h deleted file mode 100644 index 6a2d6312b..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_sysctl.h +++ /dev/null @@ -1,659 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the addresses of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register -#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 -#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 -#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device -#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 -#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 -#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 -#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 -#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 -#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 -#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 -#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 -#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 -#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 -#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 -#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 -#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 -#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 -#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 -#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 -#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 -#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 -#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 -#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 -#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 -#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 -#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 -#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 -#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 -#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 -#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 -#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 -#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 -#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 -#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 -#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 -#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 -#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present -#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#endif -#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#endif -#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present -#ifndef DEPRECATED -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#endif -#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module -#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 -#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#endif -#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 -#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#endif -#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 -#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 -#ifndef DEPRECATED -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#endif -#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_ETH 0x50000000 // ETH module -#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module -#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module -#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider -#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 -#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 -#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 -#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 -#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 -#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 -#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 -#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 -#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 -#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 -#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 -#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 -#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 -#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 -#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 -#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 -#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 -#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 -#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 -#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 -#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 -#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 -#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 -#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 -#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 -#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 -#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 -#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 -#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 -#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 -#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 -#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 -#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 -#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 -#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 -#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 -#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 -#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 -#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 -#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 -#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 -#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 -#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 -#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 -#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 -#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 -#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 -#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 -#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 -#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 -#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 -#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 -#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 -#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 -#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 -#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 -#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 -#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 -#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 -#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 -#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 -#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 -#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 -#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass -#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override -#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 -#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 -#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 -#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 -#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 -#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 -#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 -#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 -#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 -#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 -#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 -#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 -#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 -#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 -#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 -#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 -#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 -#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 -#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 -#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 -#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 -#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 -#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 -#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 -#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 -#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 -#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 -#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 -#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 -#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 -#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 -#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 -#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 -#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 -#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 -#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 -#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 -#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 -#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 -#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 -#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 -#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 -#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 -#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 -#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 -#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 -#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 -#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 -#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 -#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 -#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 -#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 -#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 -#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 -#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 -#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 -#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 -#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 -#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 -#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 -#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 -#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 -#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 -#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_timer.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_timer.h deleted file mode 100644 index eb58abf65..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_types.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_types.h deleted file mode 100644 index 974a85594..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_types.h +++ /dev/null @@ -1,129 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Stellaris silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(DEVICE_IS_SANDSTORM()) -// { -// do some Sandstorm specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Stellaris family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Stellaris silicon. Many compilers will -// then detect the "hard-coded" conditionals, and appropriately optimize the -// code blocks, eliminating any "unreachable" code. This would result in -// a smaller Driverlib, thus producing a smaller final application size, but -// at the cost of limiting the Driverlib binary to a specific Stellaris -// silicon revision. -// -//***************************************************************************** -#ifndef DEVICE_IS_SANDSTORM -#define DEVICE_IS_SANDSTORM \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_SANDSTORM))) -#endif - -#ifndef DEVICE_IS_FURY -#define DEVICE_IS_FURY \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ - SYSCTL_DID0_CLASS_FURY)) -#endif - -#ifndef DEVICE_IS_REVA2 -#define DEVICE_IS_REVA2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#ifndef DEVICE_IS_REVC1 -#define DEVICE_IS_REVC1 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) -#endif - -#ifndef DEVICE_IS_REVC2 -#define DEVICE_IS_REVC2 \ - (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ - ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) -#endif - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_uart.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_uart.h deleted file mode 100644 index e5bb1c47e..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_uart.h +++ /dev/null @@ -1,241 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable -#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_watchdog.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_watchdog.h deleted file mode 100644 index 7a3b5a8d9..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/i2c.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/i2c.h deleted file mode 100644 index 46a28eeb5..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/interrupt.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/interrupt.h deleted file mode 100644 index 1ce70f16b..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_flash.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_flash.h deleted file mode 100644 index 75d30c41c..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_flash.h +++ /dev/null @@ -1,78 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); -extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); -extern long FlashUserSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_timer.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_timer.h deleted file mode 100644 index 85b3160ab..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/lmi_timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.c b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.c deleted file mode 100644 index 3353a82e6..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.c +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ek_lm3sx965_api -//! @{ -// -//***************************************************************************** - -#include "hw_ssi.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "osram128x64x4.h" - -//***************************************************************************** -// -// Flag to indicate if SSI port is enabled for OSRAM usage. -// -//***************************************************************************** -static volatile tBoolean g_bSSIEnabled = false; - -//***************************************************************************** -// -// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in -// several places in the code to switch between vertical and horizontal -// address incrementing. -// -// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is -// defined as follows. -// -// Bit 7: Reserved -// Bit 6: Disable(0)/Enable(1) COM Split Odd Even -// When enabled, the COM signals are split Odd on one side, even on -// the other. Otherwise, they are split 0-39 on one side, 40-79 on -// the other. -// Bit 5: Reserved -// Bit 4: Disable(0)/Enable(1) COM Remap -// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) -// Bit 3: Reserved -// Bit 2: Horizontal(0)/Vertical(1) Address Increment -// When set, data RAM address will increment along the column rather -// than along the row. -// Bit 1: Disable(0)/Enable(1) Nibble Remap -// When enabled, the upper and lower nibbles in the DATA bus for access -// to the data RAM are swapped. -// Bit 0: Disable(0)/Enable(1) Column Address Remap -// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns -// 127-0. -// -//***************************************************************************** -#define OSRAM_INIT_REMAP 0x52 -#define OSRAM_INIT_OFFSET 0x4C -static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; -static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -// Note: This is the same font data that is used in the EK-LM3S811 -// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw -// function to the appropriate four bit-per-pixel gray scale format. -// -//***************************************************************************** -static const unsigned char g_pucFont[96][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the command sequence, followed by that many bytes of command data. -// Note: This initialization sequence is derived from OSRAM App Note AN018. -// -//***************************************************************************** -static const unsigned char g_pucOSRAM128x64x4Init[] = -{ - // - // Column Address - // - 4, 0x15, 0, 63, 0xe3, - - // - // Row Address - // - 4, 0x75, 0, 63, 0xe3, - - // - // Contrast Control - // - 3, 0x81, 50, 0xe3, - - // - // Half Current Range - // - 2, 0x85, 0xe3, - - // - // Display Re-map - // - 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, - - // - // Display Start Line - // - 3, 0xA1, 0, 0xe3, - - // - // Display Offset - // - 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, - - // - // Display Mode Normal - // - 2, 0xA4, 0xe3, - - // - // Multiplex Ratio - // - 3, 0xA8, 63, 0xe3, - - // - // Phase Length - // - 3, 0xB1, 0x22, 0xe3, - - // - // Row Period - // - 3, 0xB2, 70, 0xe3, - - // - // Display Clock Divide - // - 3, 0xB3, 0xF1, 0xe3, - - // - // VSL - // - 3, 0xBF, 0x0D, 0xe3, - - // - // VCOMH - // - 3, 0xBE, 0x02, 0xe3, - - // - // VP - // - 3, 0xBC, 0x10, 0xe3, - - // - // Gamma - // - 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, - - // - // Set DC-DC - 3, 0xAD, 0x03, 0xe3, - - // - // Display ON/OFF - // - 2, 0xAF, 0xe3, -}; - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of command bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Clear the command/control bit to enable command mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of data bytes to the SSD0323 controller. -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) -{ - unsigned long ulTemp; - - // - // Return iff SSI port is not enabled for OSRAM. - // - if(!g_bSSIEnabled) - { - return; - } - - // - // Set the command/control bit to enable data mode. - // - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Write the next byte to the controller. - // - SSIDataPut(SSI0_BASE, *pucBuffer++); - - // - // Dummy read to drain the fifo and time the GPIO signal. - // - SSIDataGet(SSI0_BASE, &ulTemp); - - // - // Decrement the BYTE counter. - // - ulCount--; - } -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display RAM. All pixels in the display will -//! be turned off. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Clear(void) -{ - static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; - static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; - unsigned long ulRow, ulColumn; - static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; - - // - // Set the window to fill the entire display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); - OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // In vertical address increment mode, loop through each column, filling - // each row with 0. - // - for(ulColumn = 0; ulColumn < (128/2); ulColumn++) - { - // - // 8 rows (bytes) per row of text. - // - for(ulRow = 0; ulRow < 80; ulRow += 8) - { - OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); - } - } -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! rows from the top edge of the display. -//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \note Because the OLED display packs 2 pixels of data in a single byte, the -//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY, unsigned char ucLevel) -{ - static unsigned char pucBuffer[8]; - unsigned long ulIdx1, ulIdx2; - unsigned char ucTemp; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT(ucLevel < 16); - - // - // Setup a window starting at the specified column and row, ending - // at the right edge of the display and 8 rows down (single character row). - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = 63; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + 7; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, - sizeof(g_pucOSRAM128x64x4VerticalInc)); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // Get a working copy of the current character and convert to an - // index into the character bit-map array. - // - ucTemp = *pcStr; - ucTemp &= 0x7F; - if(ucTemp < ' ') - { - ucTemp = ' '; - } - else - { - ucTemp -= ' '; - } - - // - // Build and display the character buffer. - // - for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) - { - // - // Convert two columns of 1-bit font data into a single data - // byte column of 4-bit font data. - // - for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) - { - pucBuffer[ulIdx2] = 0; - if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) - { - pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); - } - if((ulIdx1 < 2) && - (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) - { - pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); - } - } - - // - // If there is room, dump the single data byte column to the - // display. Otherwise, bail out. - // - if(ulX < 126) - { - OSRAMWriteData(pucBuffer, 8); - ulX += 2; - } - else - { - return; - } - } - - // - // Advance to the next character. - // - pcStr++; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! rows from the top of the display. -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in rows. -//! -//! This function will display a bitmap graphic on the display. Because of the -//! format of the display RAM, the starting column (/e ulX) and the number of -//! columns (/e ulWidth) must be an integer multiple of two. -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for two columns in the current row, with the leftmost -//! column being contained in bits 7:4 and the rightmost column being contained -//! in bits 3:0. -//! -//! For example, an image six columns wide and seven scan lines tall would -//! be arranged as follows (showing how the twenty one bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------------------+-------------------+-------------------+ -//! | Byte 0 | Byte 1 | Byte 2 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 3 | Byte 4 | Byte 5 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 6 | Byte 7 | Byte 8 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 9 | Byte 10 | Byte 11 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 12 | Byte 13 | Byte 14 | -//! +---------+---------+---------+--3------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 15 | Byte 16 | Byte 17 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! | Byte 18 | Byte 19 | Byte 20 | -//! +---------+---------+---------+---------+---------+---------+ -//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | -//! +---------+---------+---------+---------+---------+---------+ -//! \endverbatim -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by` -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - static unsigned char pucBuffer[8]; - - // - // Check the arguments. - // - ASSERT(ulX < 128); - ASSERT((ulX & 1) == 0); - ASSERT(ulY < 64); - ASSERT((ulX + ulWidth) <= 128); - ASSERT((ulY + ulHeight) <= 64); - ASSERT((ulWidth & 1) == 0); - - // - // Setup a window starting at the specified column and row, and ending - // at the column + width and row+height. - // - pucBuffer[0] = 0x15; - pucBuffer[1] = ulX / 2; - pucBuffer[2] = (ulX + ulWidth - 2) / 2; - OSRAMWriteCommand(pucBuffer, 3); - pucBuffer[0] = 0x75; - pucBuffer[1] = ulY; - pucBuffer[2] = ulY + ulHeight - 1; - OSRAMWriteCommand(pucBuffer, 3); - OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, - sizeof(g_pucOSRAM128x64x4HorizontalInc)); - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write this row of image data. - // - OSRAMWriteData(pucImage, (ulWidth / 2)); - - // - // Advance to the next row of the image. - // - pucImage += (ulWidth / 2); - } -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Enable(unsigned long ulFrequency) -{ - unsigned long ulTemp; - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Configure the SSI0 port for master mode. - // - SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); - - // - // (Re)Enable SSI control of the FSS pin. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Enable the SSI port. - // - SSIEnable(SSI0_BASE); - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Indicate that the OSRAM driver can use the SSI Port. - // - g_bSSIEnabled = true; -} - -//***************************************************************************** -// -//! Enable the SSI component of the OLED display driver. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Disable(void) -{ - unsigned long ulTemp; - - // - // Indicate that the OSRAM driver can no longer use the SSI Port. - // - g_bSSIEnabled = false; - - // - // Drain the receive fifo. - // - while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) - { - } - - // - // Disable the SSI port. - // - SSIDisable(SSI0_BASE); - - // - // Disable SSI control of the FSS pin. - // - GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); - -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param ulFrequency specifies the SSI Clock Frequency to be used. -//! -//! This function initializes the SSI interface to the OLED display and -//! configures the SSD0323 controller on the panel. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4Init(unsigned long ulFrequency) -{ - unsigned long ulIdx; - - // - // Enable the SSI0 and GPIO port blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - - // - // Configure the SSI0CLK and SSIOTX pins for SSI operation. - // - GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the PC7 pin as a D/Cn signal for OLED device. - // - GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, - GPIO_PIN_TYPE_STD); - GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); - - // - // Configure and enable the SSI0 port for master mode. - // - OSRAM128x64x4Enable(ulFrequency); - - // - // Clear the frame buffer. - // - OSRAM128x64x4Clear(); - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOn(void) -{ - unsigned long ulIdx; - - // - // Initialize the SSD0323 controller. Loop through the initialization - // sequence array, sending each command "string" to the controller. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); - ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, - g_pucOSRAM128x64x4Init[ulIdx] - 1); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram128x64x4.c, with -//! osram128x64x4.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAM128x64x4DisplayOff(void) -{ - static const unsigned char pucCommand1[] = - { - 0xAE, 0xAD, 0x02 - }; - - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.h deleted file mode 100644 index 2ba7cb956..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/osram128x64x4.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical -// OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM128X64X4_H__ -#define __OSRAM128X64X4_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAM128x64x4Clear(void); -extern void OSRAM128x64x4StringDraw(const char *pcStr, - unsigned long ulX, - unsigned long ulY, - unsigned char ucLevel); -extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, - unsigned long ulX, - unsigned long ulY, - unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAM128x64x4Init(unsigned long ulFrequency); -extern void OSRAM128x64x4Enable(unsigned long ulFrequency); -extern void OSRAM128x64x4Disable(void); -extern void OSRAM128x64x4DisplayOn(void); -extern void OSRAM128x64x4DisplayOff(void); - -//***************************************************************************** -// -// The following macro(s) map old names for the OSRAM functions to the new -// names. In new code, the new names should be used in favor of the old names. -// -//***************************************************************************** -#ifndef DEPRECATED -#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable -#endif - -#endif // __OSRAM128X64X4_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/pwm.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/pwm.h deleted file mode 100644 index bb67fda19..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/qei.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/qei.h deleted file mode 100644 index 89d5b20bc..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/ssi.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/ssi.h deleted file mode 100644 index 227b6bd9b..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/sysctl.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/sysctl.h deleted file mode 100644 index d2efbca0d..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/sysctl.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100010 // PWM -#define SYSCTL_PERIPH_ADC 0x00100001 // ADC -#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 -#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 -#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H -#define SYSCTL_PERIPH_ETH 0x20105000 // ETH -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/systick.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/systick.h deleted file mode 100644 index f89bf65b8..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/uart.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/uart.h deleted file mode 100644 index a0e16db33..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); -extern void UARTDisableSIR(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/watchdog.h b/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/watchdog.h deleted file mode 100644 index 2d0ad37a0..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/LuminaryDrivers/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1408 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S6965_KEIL/ParTest/ParTest.c b/Demo/CORTEX_LM3S6965_KEIL/ParTest/ParTest.c deleted file mode 100644 index a2a5b5a56..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/ParTest/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* Library includes. */ -#include "hw_types.h" -#include "gpio.h" -#include "hw_memmap.h" - - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); - GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) -{ - /* There is only one LED. */ - ( void ) uxLED; - - return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); -} - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Opt b/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Opt deleted file mode 100644 index 36531627e..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Opt +++ /dev/null @@ -1,70 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' -GRPOPT 1,(Demo_Source),0,0,0 -GRPOPT 2,(Libraries),0,0,0 -GRPOPT 3,(RTOS_Source),0,0,0 -GRPOPT 4,(uIP_Source),1,0,0 - -OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> -OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c> -OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c> -OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c> -OPTFFF 1,5,1,0,0,0,0,0,<.\main.c> -OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c> -OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> -OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> -OPTFFF 1,9,2,0,0,0,0,0,<.\startup_rvmdk.S> -OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c> -OPTFFF 1,11,5,0,0,0,0,0,<.\FreeRTOSConfig.h> -OPTFFF 2,12,4,0,0,0,0,0,<.\LuminaryDrivers\driverlib.lib> -OPTFFF 2,13,1,0,0,0,0,0,<.\LuminaryDrivers\osram128x64x4.c> -OPTFFF 3,14,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 3,15,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 3,16,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 3,17,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> -OPTFFF 3,18,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> -OPTFFF 4,19,1,352321536,0,0,0,0,<.\webserver\uIP_Task.c> -OPTFFF 4,20,1,0,0,0,0,0,<.\webserver\emac.c> -OPTFFF 4,21,1,0,0,0,0,0,<.\webserver\httpd.c> -OPTFFF 4,22,1,0,0,0,0,0,<.\webserver\httpd-cgi.c> -OPTFFF 4,23,1,0,0,0,0,0,<.\webserver\httpd-fs.c> -OPTFFF 4,24,1,0,0,0,0,0,<.\webserver\http-strings.c> -OPTFFF 4,25,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> -OPTFFF 4,26,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> -OPTFFF 4,27,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> -OPTFFF 4,28,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> - - -TARGOPT 1, (FreeRTOS_Demo) - ADSCLK=8000000 - OPTTT 1,1,1,0 - OPTHX 1,65535,0,0,0 - OPTLX 79,66,8,<.\rvmdk\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTAX 255 - OPTBL 0,(Data Sheet) - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) - OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)) - OPTKEY 0,(ARMDBGFLAGS)() - OPTKEY 0,(lmidk-agdi)(-B0 -O1792) - OPTMM 1,2,(0) - OPTDF 0x84 - OPTLE <> - OPTLC <> -EndOpt - diff --git a/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Uv2 b/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Uv2 deleted file mode 100644 index 0a625124a..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/RTOSDemo.Uv2 +++ /dev/null @@ -1,129 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' - -Group (Demo_Source) -Group (Libraries) -Group (RTOS_Source) -Group (uIP_Source) - -File 1,1,<..\Common\Minimal\BlockQ.c> 0x46520544 -File 1,1,<..\Common\Minimal\blocktim.c> 0x46520544 -File 1,1,<..\Common\Minimal\death.c> 0x46520544 -File 1,1,<..\Common\Minimal\integer.c> 0x46520544 -File 1,1,<.\main.c> 0x4664AC5E -File 1,1,<.\ParTest\ParTest.c> 0x46520580 -File 1,1,<..\Common\Minimal\PollQ.c> 0x46520544 -File 1,1,<..\Common\Minimal\semtest.c> 0x46520544 -File 1,2,<.\startup_rvmdk.S> 0x4664B752 -File 1,1,<.\timertest.c> 0x46520544 -File 1,5,<.\FreeRTOSConfig.h> 0x466376CC -File 2,4,<.\LuminaryDrivers\driverlib.lib> 0x46647F6C -File 2,1,<.\LuminaryDrivers\osram128x64x4.c> 0x46649D66 -File 3,1,<..\..\Source\tasks.c> 0x46520544 -File 3,1,<..\..\Source\list.c> 0x46520544 -File 3,1,<..\..\Source\queue.c> 0x46520544 -File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x44FB69B0 -File 3,1,<..\..\Source\portable\MemMang\heap_2.c> 0x46520580 -File 4,1,<.\webserver\uIP_Task.c> 0x4664CFB2 -File 4,1,<.\webserver\emac.c> 0x4664A47C -File 4,1,<.\webserver\httpd.c> 0x46118A3C -File 4,1,<.\webserver\httpd-cgi.c> 0x4651A7C0 -File 4,1,<.\webserver\httpd-fs.c> 0x45613A4C -File 4,1,<.\webserver\http-strings.c> 0x45613A4C -File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> 0x4651BF30 -File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> 0x45613A10 -File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> 0x45613A10 -File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> 0x4651C50C - - -Options 1,0,0 // Target 'FreeRTOS_Demo' - Device (LM3S6965) - Vendor (Luminary Micro) - Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) - FlashUt () - StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) - FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) - DevID (4337) - Rgf (LM3Sxxxx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin () - EnvInc () - EnvLib () - EnvReg (ÿLuminary\) - OrgReg (ÿLuminary\) - TgStat=16 - OutDir (.\rvmdk\) - OutName (RTOSDemo) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=1 - LstDir (.\rvmdk\) - HexSel=1 - MG32K=0 - TGMORE=0 - RunUsr 0 1 - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - CrunUsr 0 0 <> - CrunUsr 1 0 <> - SVCSID <> - GLFLAGS=1790 - ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ACPUTYP ("Cortex-M3") - ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } - OCMADSIROM { 1,0,0,0,0,0,0,4,0 } - OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } - OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } - RV_STAVEC () - ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSCMISC () - ADSCDEFN (RVDS_ARMCM3_LM3S102, "PACK_STRUCT_END=","ALIGN_STRUCT_END=") - ADSCUDEF () - ADSCINCD (.;.\LuminaryDrivers;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;..\Common\ethernet\uIP\uip-1.0\uip;.\webserver) - ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSAMISC () - ADSADEFN () - ADSAUDEF () - ADSAINCD () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSLDTA (0x00000000) - ADSLDDA (0x20000000) - ADSLDSC () - ADSLDIB () - ADSLDIC () - ADSLDMC (--entry Reset_Handler) - ADSLDIF () - ADSLDDW () - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) - OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\lmidk-agdi.dll) - FLASH3 ("" ()) - FLASH4 () -EndOpt - diff --git a/Demo/CORTEX_LM3S6965_KEIL/bitmap.h b/Demo/CORTEX_LM3S6965_KEIL/bitmap.h deleted file mode 100644 index 02ce0b365..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/bitmap.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef BITMAP_H -#define BITMAP_H - -const unsigned char pucImage[] = -{ -0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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char *pcMessage; -} xOLEDMessage; - -#endif /* LCD_MESSAGE_H */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/main.c b/Demo/CORTEX_LM3S6965_KEIL/main.c deleted file mode 100644 index 623c4375f..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/main.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Fast Interrupt Test" - A high frequency periodic interrupt is generated - * using a free running timer to demonstrate the use of the - * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt - * service routine measures the number of processor clocks that occur between - * each interrupt - and in so doing measures the jitter in the interrupt timing. - * The maximum measured jitter time is latched in the ulMaxJitter variable, and - * displayed on the OLED display by the 'Check' task as described below. The - * fast interrupt is configured and handled in the timertest.c source file. - * - * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that - * is permitted to access the display directly. Other tasks wishing to write a - * message to the OLED send the message on a queue to the OLED task instead of - * accessing the OLED themselves. The OLED task just blocks on the queue waiting - * for messages - waking and displaying the messages as they arrive. - * - * "Check" task - This only executes every five seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the standard demo tasks are still operational. Should any - * unexpected behaviour within a demo task be discovered the 'check' task will - * write an error to the OLED (via the OLED task). If all the demo tasks are - * executing with their expected behaviour then the check task writes PASS - * along with the max jitter time to the OLED (again via the OLED task), as - * described above. - * - * "uIP" task - This is the task that handles the uIP stack. All TCP/IP - * processing is performed in this task. - */ - - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "integer.h" -#include "blocktim.h" -#include "flash.h" -#include "partest.h" -#include "semtest.h" -#include "pollq.h" -#include "lcd_message.h" -#include "bitmap.h" - -/* Hardware library includes. */ -#include "hw_memmap.h" -#include "hw_types.h" -#include "sysctl.h" -#include "gpio.h" -#include "osram128x64x4.h" - -/*-----------------------------------------------------------*/ - -/* The time between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* Size of the stack allocated to the uIP task. */ -#define mainBASIC_WEB_STACK_SIZE ( 200 ) - -/* The check task uses the sprintf function so requires a little more stack too. */ -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) - -/* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) - -/* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 - -/* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) - -/* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY 1000000 - -/*-----------------------------------------------------------*/ - -/* - * Checks the status of all the demo tasks then prints a message to the - * display. The message will be either PASS - an include in brackets the - * maximum measured jitter time (as described at the to of the file), or a - * message that describes which of the standard demo tasks an error has been - * discovered in. - * - * Messages are not written directly to the terminal, but passed to vOLEDTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that handles the uIP stack. All TCP/IP processing is performed in - * this task. - */ -extern void vuIP_Task( void *pvParameters ); - -/* - * The display is written two by more than one task so is controlled by a - * 'gatekeeper' task. This is the only task that is actually permitted to - * access the display directly. Other tasks wanting to display a message send - * the message to the gatekeeper. - */ -static void vOLEDTask( void *pvParameters ); - -/* - * Configure the hardware for the demo. - */ -static void prvSetupHardware( void ); - -/* - * Configures the high frequency timers - those used to measure the timing - * jitter while the real time kernel is executing. - */ -extern void vSetupTimer( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to send messages to the OLED task. */ -xQueueHandle xOLEDQueue; - -/* The welcome text. */ -const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); - - /* Create the uIP task. */ - xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Configure the high frequency interrupt used to measure the interrupt - jitter time. */ - #ifdef __ICCARM__ - vSetupTimer(); - #endif - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; -} -/*-----------------------------------------------------------*/ - -void prvSetupHardware( void ) -{ - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - - /* Enable/Reset the Ethernet Controller */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); - SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); - - /* Enable Port F for Ethernet LEDs - LED0 Bit 3 Output - LED1 Bit 2 Output */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); - GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); - GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); - - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; -xOLEDMessage xMessage; -static portCHAR cPassMessage[ mainMAX_MSG_LEN ]; -extern unsigned portLONG ulMaxJitter; - - xLastExecutionTime = xTaskGetTickCount(); - xMessage.pcMessage = cPassMessage; - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN CREATE"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else - { - #ifdef __ICCARM__ - sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK ); - #else - sprintf( cPassMessage, "PASS" ); - #endif - } - - /* Send the message to the OLED gatekeeper for display. */ - xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - -void vOLEDTask( void *pvParameters ) -{ -xOLEDMessage xMessage; -unsigned portLONG ulY = mainMAX_ROWS; - - /* Initialise the OLED and display a startup message. */ - OSRAM128x64x4Init( ulSSI_FREQUENCY ); - - OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= mainMAX_ROWS ) - { - ulY = mainCHARACTER_HEIGHT; - OSRAM128x64x4Clear(); - OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message. */ - OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE ); - } -} diff --git a/Demo/CORTEX_LM3S6965_KEIL/startup_rvmdk.S b/Demo/CORTEX_LM3S6965_KEIL/startup_rvmdk.S deleted file mode 100644 index ddedd9af5..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/startup_rvmdk.S +++ /dev/null @@ -1,248 +0,0 @@ -; <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** -; -; startup_rvmdk.S - Startup code for use with Keil's uVision. -; -; Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. -; -; Software License Agreement -; -; Luminary Micro, Inc. (LMI) is supplying this software for use solely and -; exclusively on LMI's microcontroller products. -; -; The software is owned by LMI and/or its suppliers, and is protected under -; applicable copyright laws. All rights are reserved. Any use in violation -; of the foregoing restrictions may subject the user to criminal sanctions -; under applicable laws, as well as to civil liability for the breach of the -; terms and conditions of this license. -; -; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 1408 of the Stellaris Peripheral Driver Library. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Stack EQU 0x00000800 - -;****************************************************************************** -; -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack -__initial_sp - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -HeapMem - SPACE Heap -__heap_limit - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** - EXPORT __Vectors -__Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD FaultISR ; Hard Fault Handler - DCD IntDefaultHandler ; MPU Fault Handler - DCD IntDefaultHandler ; Bus Fault Handler - DCD IntDefaultHandler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; SVCall Handler - DCD IntDefaultHandler ; Debug Monitor Handler - DCD 0 ; Reserved - EXTERN xPortPendSVHandler - DCD xPortPendSVHandler ; PendSV Handler - EXTERN xPortSysTickHandler - DCD xPortSysTickHandler ; SysTick Handler - DCD IntDefaultHandler ; GPIO Port A - DCD IntDefaultHandler ; GPIO Port B - DCD IntDefaultHandler ; GPIO Port C - DCD IntDefaultHandler ; GPIO Port D - DCD IntDefaultHandler ; GPIO Port E - DCD IntDefaultHandler ; UART0 - DCD IntDefaultHandler ; UART1 - DCD IntDefaultHandler ; SSI - DCD IntDefaultHandler ; I2C - DCD IntDefaultHandler ; PWM Fault - DCD IntDefaultHandler ; PWM Generator 0 - DCD IntDefaultHandler ; PWM Generator 1 - DCD IntDefaultHandler ; PWM Generator 2 - DCD IntDefaultHandler ; Quadrature Encoder - DCD IntDefaultHandler ; ADC Sequence 0 - DCD IntDefaultHandler ; ADC Sequence 1 - DCD IntDefaultHandler ; ADC Sequence 2 - DCD IntDefaultHandler ; ADC Sequence 3 - DCD IntDefaultHandler ; Watchdog - EXTERN Timer0IntHandler - DCD Timer0IntHandler ; Timer 0A - DCD IntDefaultHandler ; Timer 0B - DCD IntDefaultHandler ; Timer 1A - DCD IntDefaultHandler ; Timer 1B - DCD IntDefaultHandler ; Timer 2A - DCD IntDefaultHandler ; Timer 2B - DCD IntDefaultHandler ; Comp 0 - DCD IntDefaultHandler ; Comp 1 - DCD IntDefaultHandler ; Comp 2 - DCD IntDefaultHandler ; System Control - DCD IntDefaultHandler ; Flash Control - DCD IntDefaultHandler ; GPIO Port F - DCD IntDefaultHandler ; GPIO Port G - DCD IntDefaultHandler ; GPIO Port H - DCD IntDefaultHandler ; UART2 Rx and Tx - DCD IntDefaultHandler ; SSI1 Rx and Tx - DCD IntDefaultHandler ; Timer 3 subtimer A - DCD IntDefaultHandler ; Timer 3 subtimer B - DCD IntDefaultHandler ; I2C1 Master and Slave - DCD IntDefaultHandler ; Quadrature Encoder 1 - DCD IntDefaultHandler ; CAN0 - DCD IntDefaultHandler ; CAN1 - DCD 0 ; Reserved - EXTERN vEMAC_ISR - DCD vEMAC_ISR ; Ethernet - DCD IntDefaultHandler ; Hibernate - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** - EXPORT Reset_Handler -Reset_Handler - ; - ; Call the C library enty point that handles startup. This will copy - ; the .data section initializers from flash to SRAM and zero fill the - ; .bss section. It will then call __rt_entry, which will be either the - ; C library version or the one supplied here depending on the - ; configured startup type. - ; - IMPORT __main - B __main - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a NMI. This -; simply enters an infinite loop, preserving the system state for examination -; by a debugger. -; -;****************************************************************************** -NmiSR - B NmiSR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a fault -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -FaultISR - B FaultISR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives an unexpected -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -IntDefaultHandler - B IntDefaultHandler - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Some code in the normal code section for initializing the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; The function expected of the C library startup code for defining the stack -; and heap memory locations. For the C library version of the startup code, -; provide this function so that the C library initialization code can find out -; the location of the stack and heap. -; -;****************************************************************************** - IF :DEF: __MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - ENDIF - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Tell the assembler that we're done. -; -;****************************************************************************** - END diff --git a/Demo/CORTEX_LM3S6965_KEIL/timertest.c b/Demo/CORTEX_LM3S6965_KEIL/timertest.c deleted file mode 100644 index 51513be33..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/timertest.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* High speed timer test as described in main.c. */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Library includes. */ -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "interrupt.h" -#include "sysctl.h" -#include "LMI_timer.h" - -/* The set frequency of the interrupt. Deviations from this are measured as -the jitter. */ -#define timerINTERRUPT_FREQUENCY ( 20000UL ) - -/* The expected time between each of the timer interrupts - if the jitter was -zero. */ -#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) - -/* The highest available interrupt priority. */ -#define timerHIGHEST_PRIORITY ( 0 ) - -/* Misc defines. */ -#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) -#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) - -/*-----------------------------------------------------------*/ - -/* Interrupt handler in which the jitter is measured. */ -void Timer0IntHandler( void ); - -/* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; - -/*-----------------------------------------------------------*/ - -void vSetupTimer( void ) -{ -unsigned long ulFrequency; - - /* Timer zero is used to generate the interrupts, and timer 1 is used - to measure the jitter. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); - TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); - TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); - - /* Set the timer interrupt to be above the kernel - highest. */ - IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); - - /* Just used to measure time. */ - TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); - - /* The rate at which the timer will interrupt. */ - ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; - TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); - IntEnable( INT_TIMER0A ); - TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); - - /* Enable both timers. */ - TimerEnable( TIMER0_BASE, TIMER_A ); - TimerEnable( TIMER1_BASE, TIMER_A ); -} -/*-----------------------------------------------------------*/ - -void Timer0IntHandler( void ) -{ -unsigned portLONG ulDifference, ulCurrentCount; -static portLONG ulMaxDifference = 0, ulLastCount = 0; - - /* We use the timer 1 counter value to measure the clock cycles between - the timer 0 interrupts. */ - ulCurrentCount = timerTIMER_1_COUNT_VALUE; - - if( ulCurrentCount < ulLastCount ) - { - /* How many times has timer 1 counted since the last interrupt? */ - ulDifference = ulLastCount - ulCurrentCount; - - /* Is this the largest difference we have measured yet? */ - if( ulDifference > ulMaxDifference ) - { - ulMaxDifference = ulDifference; - ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; - } - } - - ulLastCount = ulCurrentCount; - - TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); -} - - - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/Makefile.webserver b/Demo/CORTEX_LM3S6965_KEIL/webserver/Makefile.webserver deleted file mode 100644 index f38c47a72..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/Makefile.webserver +++ /dev/null @@ -1 +0,0 @@ -APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/clock-arch.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/clock-arch.h deleted file mode 100644 index cde657b62..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include "FreeRTOS.h" - -typedef unsigned long clock_time_t; -#define CLOCK_CONF_SECOND configTICK_RATE_HZ - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.c deleted file mode 100644 index b5f394442..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "Semphr.h" -#include "task.h" - -/* Demo includes. */ -#include "EMAC.h" - -/* uIP includes. */ -#include "uip.h" - -/* Hardware library includes. */ -#include "hw_types.h" -#include "hw_memmap.h" -#include "hw_ints.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "interrupt.h" - -#define emacNUM_RX_BUFFERS 5 -#define emacFRAM_SIZE_BYTES 2 -#define macNEGOTIATE_DELAY 2000 -#define macWAIT_SEND_TIME ( 10 ) - -/* The task that handles the MAC peripheral. This is created at a high -priority and is effectively a deferred interrupt handler. The peripheral -handling is deferred to a task to prevent the entire FIFO having to be read -from within an ISR. */ -void vMACHandleTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used to wake the uIP task when data arrives. */ -xSemaphoreHandle xEMACSemaphore = NULL; - -/* The semaphore used to wake the interrupt handler task. The peripheral -is processed at the task level to prevent the need to read the entire FIFO from -within the ISR itself. */ -xSemaphoreHandle xMACInterruptSemaphore = NULL; - -/* The buffer used by the uIP stack. In this case the pointer is used to -point to one of the Rx buffers. */ -unsigned portCHAR *uip_buf; - -/* Buffers into which Rx data is placed. */ -static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; - -/* The length of the data within each of the Rx buffers. */ -static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; - -/* Used to keep a track of the number of bytes to transmit. */ -static unsigned portLONG ulNextTxSpace; - -/*-----------------------------------------------------------*/ - -portBASE_TYPE vInitEMAC( void ) -{ -unsigned long ulTemp; -portBASE_TYPE xReturn; - - /* Ensure all interrupts are disabled. */ - EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); - - /* Clear any interrupts that were already pending. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Initialise the MAC and connect. */ - EthernetInit( ETH_BASE ); - EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); - EthernetEnable( ETH_BASE ); - - /* Mark each Rx buffer as empty. */ - for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) - { - ulRxLength[ ulTemp ] = 0; - } - - /* Create the queue and task used to defer the MAC processing to the - task level. */ - vSemaphoreCreateBinary( xMACInterruptSemaphore ); - xSemaphoreTake( xMACInterruptSemaphore, 0 ); - xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - vTaskDelay( macNEGOTIATE_DELAY ); - - /* We are only interested in Rx interrupts. */ - IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_ETH ); - EthernetIntEnable(ETH_BASE, ETH_INT_RX); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) -{ -static unsigned long ulNextRxBuffer = 0; -unsigned int iLen; - - iLen = ulRxLength[ ulNextRxBuffer ]; - - if( iLen != 0 ) - { - /* Leave room for the size at the start of the buffer. */ - uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - - ulRxLength[ ulNextRxBuffer ] = 0; - - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - } - - return iLen; -} -/*-----------------------------------------------------------*/ - -void vInitialiseSend( void ) -{ - /* Set the index to the first byte to send - skipping over the size - bytes. */ - ulNextTxSpace = 2; -} -/*-----------------------------------------------------------*/ - -void vIncrementTxLength( unsigned portLONG ulLength ) -{ - ulNextTxSpace += ulLength; -} -/*-----------------------------------------------------------*/ - -void vSendBufferToMAC( void ) -{ -unsigned long *pulSource; -unsigned portSHORT * pus; -unsigned portLONG ulNextWord; - - /* Locate the data to be send. */ - pus = ( unsigned portSHORT * ) uip_buf; - - /* Add in the size of the data. */ - pus--; - *pus = ulNextTxSpace; - - /* Wait for data to be sent if there is no space immediately. */ - while( !EthernetSpaceAvail( ETH_BASE ) ) - { - vTaskDelay( macWAIT_SEND_TIME ); - } - - pulSource = ( unsigned portLONG * ) pus; - - for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) - { - HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; - pulSource++; - } - - /* Go. */ - HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; -} -/*-----------------------------------------------------------*/ - -void vEMAC_ISR( void ) -{ -portBASE_TYPE xSwitchRequired = pdFALSE; -unsigned portLONG ulTemp; - - /* Clear the interrupt. */ - ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); - EthernetIntClear( ETH_BASE, ulTemp ); - - /* Was it an Rx interrupt? */ - if( ulTemp & ETH_INT_RX ) - { - xSwitchRequired = pdTRUE; - xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE ); - EthernetIntDisable( ETH_BASE, ETH_INT_RX ); - } - - /* Switch to the uIP task. */ - portEND_SWITCHING_ISR( xSwitchRequired ); -} -/*-----------------------------------------------------------*/ - -void vMACHandleTask( void *pvParameters ) -{ -unsigned long ulLen = 0, i; -unsigned portLONG ulLength, ulInt; -unsigned long *pulBuffer; -static unsigned portLONG ulNextRxBuffer = 0; -portBASE_TYPE xSwitchRequired = pdFALSE; - - for( ;; ) - { - /* Wait for something to do. */ - xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); - - while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) - { - ulLength = HWREG( ETH_BASE + MAC_O_DATA ); - - /* Leave room at the start of the buffer for the size. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); - *pulBuffer = ( ulLength >> 16 ); - - /* Get the size of the data. */ - pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); - ulLength &= 0xFFFF; - - if( ulLength > 4 ) - { - ulLength -= 4; - - if( ulLength >= UIP_BUFSIZE ) - { - /* The data won't fit in our buffer. Ensure we don't - try to write into the buffer. */ - ulLength = 0; - } - - /* Read out the data into our buffer. */ - for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) - { - *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); - pulBuffer++; - } - - /* Store the length of the data into the separate array. */ - ulRxLength[ ulNextRxBuffer ] = ulLength; - - /* Use the next buffer the next time through. */ - ulNextRxBuffer++; - if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) - { - ulNextRxBuffer = 0; - } - - /* Ensure the uIP task is not blocked as data has arrived. */ - xSemaphoreGive( xEMACSemaphore ); - } - } - - EthernetIntEnable( ETH_BASE, ETH_INT_RX ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.h deleted file mode 100644 index a49b59828..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/emac.h +++ /dev/null @@ -1,322 +0,0 @@ -/*---------------------------------------------------------------------------- - * LPC2378 Ethernet Definitions - *---------------------------------------------------------------------------- - * Name: EMAC.H - * Purpose: Philips LPC2378 EMAC hardware definitions - *---------------------------------------------------------------------------- - * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#ifndef __EMAC_H -#define __EMAC_H - -/* MAC address definition. The MAC address must be unique on the network. */ -#define emacETHADDR0 0 -#define emacETHADDR1 0xbd -#define emacETHADDR2 0x33 -#define emacETHADDR3 0x02 -#define emacETHADDR4 0x64 -#define emacETHADDR5 0x24 - - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ -#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ - -/* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE 0x7FE00000 -#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) -#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) -#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) -#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) -#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) - -/* RX and TX descriptor and status definitions. */ -#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) -#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) -#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) -#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) -#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) -#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) -#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) -#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) -#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* MAC Configuration Register 1 */ -#define MAC1_REC_EN 0x00000001 /* Receive Enable */ -#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ -#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ -#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ -#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ -#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ -#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ -#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ -#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ -#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ -#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ -#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ -#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ -#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ -#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ -#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ -#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ -#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ -#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ -#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ -#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ -#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ -#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ -#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ - -/* Non Back-to-Back Inter-Packet-Gap Register */ -#define IPGR_DEF 0x00000012 /* Recommended value */ - -/* Collision Window/Retry Register */ -#define CLRT_DEF 0x0000370F /* Default value */ - -/* PHY Support Register */ -#undef SUPP_SPEED /* Remove compiler warning. */ -#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ -#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ - -/* Test Register */ -#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ -#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ -#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ - -/* MII Management Configuration Register */ -#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ -#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ -#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ -#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ - -/* MII Management Command Register */ -#undef MCMD_READ /* Remove compiler warning. */ -#define MCMD_READ 0x00000001 /* MII Read */ -#undef MCMD_SCAN /* Remove compiler warning. */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#undef MIND_BUSY /* Remove compiler warning. */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* Command Register */ -#define CR_RX_EN 0x00000001 /* Enable Receive */ -#define CR_TX_EN 0x00000002 /* Enable Transmit */ -#define CR_REG_RES 0x00000008 /* Reset Host Registers */ -#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ -#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ -#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ -#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ -#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ -#define CR_RMII 0x00000200 /* Reduced MII Interface */ -#define CR_FULL_DUP 0x00000400 /* Full Duplex */ - -/* Status Register */ -#define SR_RX_EN 0x00000001 /* Enable Receive */ -#define SR_TX_EN 0x00000002 /* Enable Transmit */ - -/* Transmit Status Vector 0 Register */ -#define TSV0_CRC_ERR 0x00000001 /* CRC error */ -#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ -#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ -#define TSV0_MCAST 0x00000010 /* Multicast Destination */ -#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ -#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ -#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ -#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ -#define TSV0_GIANT 0x00000400 /* Giant Frame */ -#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ -#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ -#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ -#define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ -#define TSV0_VLAN 0x80000000 /* VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ -#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ -#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ -#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ -#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ -#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ -#define RSV_CRC_ERR 0x00100000 /* CRC Error */ -#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ -#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ -#define RSV_REC_OK 0x00800000 /* Frame Received OK */ -#define RSV_MCAST 0x01000000 /* Multicast Frame */ -#define RSV_BCAST 0x02000000 /* Broadcast Frame */ -#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ -#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ -#define RSV_PAUSE 0x10000000 /* Pause Frame */ -#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ -#define RSV_VLAN 0x40000000 /* VLAN Frame */ - -/* Flow Control Counter Register */ -#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ -#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ - -/* Flow Control Status Register */ -#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ - -/* Receive Filter Control Register */ -#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ -#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ -#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ -#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ -#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ -#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ -#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ -#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ -#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ -#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ -#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ -#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ -#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ -#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ -#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ - -/* Interrupt Status/Enable/Clear/Set Registers */ -#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ -#define INT_RX_ERR 0x00000002 /* Receive Error */ -#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ -#define INT_RX_DONE 0x00000008 /* Receive Done */ -#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ -#define INT_TX_ERR 0x00000020 /* Transmit Error */ -#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ -#define INT_TX_DONE 0x00000080 /* Transmit Done */ -#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ -#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ - -/* Power Down Register */ -#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ - -/* RX Descriptor Control Word */ -#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ -#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ -#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define RINFO_SIZE 0x000007FF /* Data size in bytes */ -#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ -#define RINFO_VLAN 0x00080000 /* VLAN Frame */ -#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ -#define RINFO_MCAST 0x00200000 /* Multicast Frame */ -#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ -#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ -#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ -#define RINFO_LEN_ERR 0x02000000 /* Length Error */ -#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ -#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ -#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ -#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ -#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ - RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) - -/* TX Descriptor Control Word */ -#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ -#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ -#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ -#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ -#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ -#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ -#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ -#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ -#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ -#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ -#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ -#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier */ - -// prototypes -portBASE_TYPE vInitEMAC(void); -unsigned short ReadFrameBE_EMAC(void); -void vIncrementTxLength(unsigned long ulLength); -void CopyFromFrame_EMAC(void *Dest, unsigned short Size); -void DummyReadFrame_EMAC(unsigned short Size); -unsigned short StartReadFrame(void); -void EndReadFrame(void); -unsigned int CheckFrameReceived(void); -void vInitialiseSend(void); -unsigned int Rdy4Tx(void); -void vSendBufferToMAC(void); -void vEMACWaitForInput( void ); -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); - - -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings b/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings deleted file mode 100644 index 0d3c30cdd..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings +++ /dev/null @@ -1,35 +0,0 @@ -http_http "http://" -http_200 "200 " -http_301 "301 " -http_302 "302 " -http_get "GET " -http_10 "HTTP/1.0" -http_11 "HTTP/1.1" -http_content_type "content-type: " -http_texthtml "text/html" -http_location "location: " -http_host "host: " -http_crnl "\r\n" -http_index_html "/index.html" -http_404_html "/404.html" -http_referer "Referer:" -http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_content_type_plain "Content-type: text/plain\r\n\r\n" -http_content_type_html "Content-type: text/html\r\n\r\n" -http_content_type_css "Content-type: text/css\r\n\r\n" -http_content_type_text "Content-type: text/text\r\n\r\n" -http_content_type_png "Content-type: image/png\r\n\r\n" -http_content_type_gif "Content-type: image/gif\r\n\r\n" -http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" -http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" -http_html ".html" -http_shtml ".shtml" -http_htm ".htm" -http_css ".css" -http_png ".png" -http_gif ".gif" -http_jpg ".jpg" -http_text ".txt" -http_txt ".txt" - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.c deleted file mode 100644 index ef7a41c7d..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.c +++ /dev/null @@ -1,102 +0,0 @@ -const char http_http[8] = -/* "http://" */ -{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; -const char http_200[5] = -/* "200 " */ -{0x32, 0x30, 0x30, 0x20, }; -const char http_301[5] = -/* "301 " */ -{0x33, 0x30, 0x31, 0x20, }; -const char http_302[5] = -/* "302 " */ -{0x33, 0x30, 0x32, 0x20, }; -const char http_get[5] = -/* "GET " */ -{0x47, 0x45, 0x54, 0x20, }; -const char http_10[9] = -/* "HTTP/1.0" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; -const char http_11[9] = -/* "HTTP/1.1" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; -const char http_content_type[15] = -/* "content-type: " */ -{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; -const char http_texthtml[10] = -/* "text/html" */ -{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_location[11] = -/* "location: " */ -{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; -const char http_host[7] = -/* "host: " */ -{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; -const char http_crnl[3] = -/* "\r\n" */ -{0xd, 0xa, }; -const char http_index_html[12] = -/* "/index.html" */ -{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_404_html[10] = -/* "/404.html" */ -{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_referer[9] = -/* "Referer:" */ -{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; -const char http_header_200[84] = -/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_header_404[91] = -/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_content_type_plain[29] = -/* "Content-type: text/plain\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_html[28] = -/* "Content-type: text/html\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_css [27] = -/* "Content-type: text/css\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_text[28] = -/* "Content-type: text/text\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_png [28] = -/* "Content-type: image/png\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_gif [28] = -/* "Content-type: image/gif\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_jpg [29] = -/* "Content-type: image/jpeg\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_binary[43] = -/* "Content-type: application/octet-stream\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; -const char http_html[6] = -/* ".html" */ -{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_shtml[7] = -/* ".shtml" */ -{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_htm[5] = -/* ".htm" */ -{0x2e, 0x68, 0x74, 0x6d, }; -const char http_css[5] = -/* ".css" */ -{0x2e, 0x63, 0x73, 0x73, }; -const char http_png[5] = -/* ".png" */ -{0x2e, 0x70, 0x6e, 0x67, }; -const char http_gif[5] = -/* ".gif" */ -{0x2e, 0x67, 0x69, 0x66, }; -const char http_jpg[5] = -/* ".jpg" */ -{0x2e, 0x6a, 0x70, 0x67, }; -const char http_text[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; -const char http_txt[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.h deleted file mode 100644 index acbe7e17f..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/http-strings.h +++ /dev/null @@ -1,34 +0,0 @@ -extern const char http_http[8]; -extern const char http_200[5]; -extern const char http_301[5]; -extern const char http_302[5]; -extern const char http_get[5]; -extern const char http_10[9]; -extern const char http_11[9]; -extern const char http_content_type[15]; -extern const char http_texthtml[10]; -extern const char http_location[11]; -extern const char http_host[7]; -extern const char http_crnl[3]; -extern const char http_index_html[12]; -extern const char http_404_html[10]; -extern const char http_referer[9]; -extern const char http_header_200[84]; -extern const char http_header_404[91]; -extern const char http_content_type_plain[29]; -extern const char http_content_type_html[28]; -extern const char http_content_type_css [27]; -extern const char http_content_type_text[28]; -extern const char http_content_type_png [28]; -extern const char http_content_type_gif [28]; -extern const char http_content_type_jpg [29]; -extern const char http_content_type_binary[43]; -extern const char http_html[6]; -extern const char http_shtml[7]; -extern const char http_htm[5]; -extern const char http_css[5]; -extern const char http_png[5]; -extern const char http_gif[5]; -extern const char http_jpg[5]; -extern const char http_text[5]; -extern const char http_txt[5]; diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.c deleted file mode 100644 index 803b771e6..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-cgi.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2006, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ - * - */ - -#include "uip.h" -#include "psock.h" -#include "httpd.h" -#include "httpd-cgi.h" -#include "httpd-fs.h" - -#include -#include - -HTTPD_CGI_CALL(file, "file-stats", file_stats); -HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); -HTTPD_CGI_CALL(net, "net-stats", net_stats); -HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); -HTTPD_CGI_CALL(io, "led-io", led_io ); - - -static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; - -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -httpd_cgifunction -httpd_cgi(char *name) -{ - const struct httpd_cgi_call **f; - - /* Find the matching name in the table, return the function. */ - for(f = calls; *f != NULL; ++f) { - if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { - return (*f)->function; - } - } - return nullfunction; -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_file_stats(void *arg) -{ - char *f = (char *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -static unsigned short -generate_tcp_stats(void *arg) -{ - struct uip_conn *conn; - struct httpd_state *s = (struct httpd_state *)arg; - - conn = &uip_conns[s->count]; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "

%d%u.%u.%u.%u:%u%s%u%u%c %c
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
%! net-stats
-
- - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/tcp.shtml b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/tcp.shtml deleted file mode 100644 index 654d61f21..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fs/tcp.shtml +++ /dev/null @@ -1,21 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO -

-

-
-

Network connections

-

- - -%! tcp-connections - - - - - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.c deleted file mode 100644 index a7fcfab5a..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.c +++ /dev/null @@ -1,470 +0,0 @@ -static const unsigned char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, - 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, - 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, - 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, - 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, - 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, - 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, - 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0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, - 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, - 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, - 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, - 0xa, 0xd, 0xa, 0}; - -const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; - -const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; - -const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; - -const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; - -#define HTTPD_FS_ROOT file_tcp_shtml - -#define HTTPD_FS_NUMFILES 6 diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.h deleted file mode 100644 index 52d35c265..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd-fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FSDATA_H__ -#define __HTTPD_FSDATA_H__ - -#include "uip.h" - -struct httpd_fsdata_file { - const struct httpd_fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -struct httpd_fsdata_file_noconst { - struct httpd_fsdata_file *next; - char *name; - char *data; - int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -#endif /* __HTTPD_FSDATA_H__ */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.c deleted file mode 100644 index 644cf16b7..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.c +++ /dev/null @@ -1,346 +0,0 @@ -/** - * \addtogroup apps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - - */ - -/** - * \file - * Web server - * \author - * Adam Dunkels - */ - - -/* - * Copyright (c) 2004, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-cgi.h" -#include "http-strings.h" - -#include - -#define STATE_WAITING 0 -#define STATE_OUTPUT 1 - -#define ISO_nl 0x0a -#define ISO_space 0x20 -#define ISO_bang 0x21 -#define ISO_percent 0x25 -#define ISO_period 0x2e -#define ISO_slash 0x2f -#define ISO_colon 0x3a - - -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_part_of_file(void *state) -{ - struct httpd_state *s = (struct httpd_state *)state; - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - memcpy(uip_appdata, s->file.data, s->len); - - return s->len; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - do { - PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); - s->file.len -= s->len; - s->file.data += s->len; - } while(s->file.len > 0); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_part_of_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND(&s->sout, s->file.data, s->len); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static void -next_scriptstate(struct httpd_state *s) -{ - char *p; - p = strchr(s->scriptptr, ISO_nl) + 1; - s->scriptlen -= (unsigned short)(p - s->scriptptr); - s->scriptptr = p; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_script(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->scriptpt); - - - while(s->file.len > 0) { - - /* Check if we should start executing a script. */ - if(*s->file.data == ISO_percent && - *(s->file.data + 1) == ISO_bang) { - s->scriptptr = s->file.data + 3; - s->scriptlen = s->file.len - 3; - if(*(s->scriptptr - 1) == ISO_colon) { - httpd_fs_open(s->scriptptr + 1, &s->file); - PT_WAIT_THREAD(&s->scriptpt, send_file(s)); - } else { - PT_WAIT_THREAD(&s->scriptpt, - httpd_cgi(s->scriptptr)(s, s->scriptptr)); - } - next_scriptstate(s); - - /* The script is over, so we reset the pointers and continue - sending the rest of the file. */ - s->file.data = s->scriptptr; - s->file.len = s->scriptlen; - } else { - /* See if we find the start of script marker in the block of HTML - to be sent. */ - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - - if(*s->file.data == ISO_percent) { - ptr = strchr(s->file.data + 1, ISO_percent); - } else { - ptr = strchr(s->file.data, ISO_percent); - } - if(ptr != NULL && - ptr != s->file.data) { - s->len = (int)(ptr - s->file.data); - if(s->len >= uip_mss()) { - s->len = uip_mss(); - } - } - PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); - s->file.data += s->len; - s->file.len -= s->len; - - } - } - - PT_END(&s->scriptpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) -{ - char *ptr; - - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND_STR(&s->sout, statushdr); - - ptr = strrchr(s->filename, ISO_period); - if(ptr == NULL) { - PSOCK_SEND_STR(&s->sout, http_content_type_binary); - } else if(strncmp(http_html, ptr, 5) == 0 || - strncmp(http_shtml, ptr, 6) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_html); - } else if(strncmp(http_css, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_css); - } else if(strncmp(http_png, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_png); - } else if(strncmp(http_gif, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_gif); - } else if(strncmp(http_jpg, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_jpg); - } else { - PSOCK_SEND_STR(&s->sout, http_content_type_plain); - } - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_output(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->outputpt); - - if(!httpd_fs_open(s->filename, &s->file)) { - httpd_fs_open(http_404_html, &s->file); - strcpy(s->filename, http_404_html); - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_404)); - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_200)); - ptr = strchr(s->filename, ISO_period); - if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { - PT_INIT(&s->scriptpt); - PT_WAIT_THREAD(&s->outputpt, handle_script(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } - } - PSOCK_CLOSE(&s->sout); - PT_END(&s->outputpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_input(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sin); - - PSOCK_READTO(&s->sin, ISO_space); - - - if(strncmp(s->inputbuf, http_get, 4) != 0) { - PSOCK_CLOSE_EXIT(&s->sin); - } - PSOCK_READTO(&s->sin, ISO_space); - - if(s->inputbuf[0] != ISO_slash) { - PSOCK_CLOSE_EXIT(&s->sin); - } - - if(s->inputbuf[1] == ISO_space) { - strncpy(s->filename, http_index_html, sizeof(s->filename)); - } else { - - s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; - - /* Process any form input being sent to the server. */ - { - extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); - vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); - } - - strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); - } - - /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ - - s->state = STATE_OUTPUT; - - while(1) { - PSOCK_READTO(&s->sin, ISO_nl); - - if(strncmp(s->inputbuf, http_referer, 8) == 0) { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; - /* httpd_log(&s->inputbuf[9]);*/ - } - } - - PSOCK_END(&s->sin); -} -/*---------------------------------------------------------------------------*/ -static void -handle_connection(struct httpd_state *s) -{ - handle_input(s); - if(s->state == STATE_OUTPUT) { - handle_output(s); - } -} -/*---------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); - - if(uip_closed() || uip_aborted() || uip_timedout()) { - } else if(uip_connected()) { - PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); - PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); - PT_INIT(&s->outputpt); - s->state = STATE_WAITING; - /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ - s->timer = 0; - handle_connection(s); - } else if(s != NULL) { - if(uip_poll()) { - ++s->timer; - if(s->timer >= 20) { - uip_abort(); - } - } else { - s->timer = 0; - } - handle_connection(s); - } else { - uip_abort(); - } -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the web server - * - * This function initializes the web server and should be - * called at system boot-up. - */ -void -httpd_init(void) -{ - uip_listen(HTONS(80)); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.h deleted file mode 100644 index 7f7a6666e..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/httpd.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2005, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -#include "psock.h" -#include "httpd-fs.h" - -struct httpd_state { - unsigned char timer; - struct psock sin, sout; - struct pt outputpt, scriptpt; - char inputbuf[50]; - char filename[20]; - char state; - struct httpd_fs_file file; - int len; - char *scriptptr; - int scriptlen; - - unsigned short count; -}; - -void httpd_init(void); -void httpd_appcall(void); - -void httpd_log(char *msg); -void httpd_log_file(u16_t *requester, char *file); - -#endif /* __HTTPD_H__ */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/makefsdata b/Demo/CORTEX_LM3S6965_KEIL/webserver/makefsdata deleted file mode 100644 index 8d2715a8a..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/makefsdata +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> httpd-fsdata.c"); - -chdir("httpd-fs"); - -opendir(DIR, "."); -@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); -closedir(DIR); - -foreach $file (@files) { - - if(-d $file && $file !~ /^\./) { - print "Processing directory $file\n"; - opendir(DIR, $file); - @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); - closedir(DIR); - printf "Adding files @newfiles\n"; - @files = (@files, map { $_ = "$file/$_" } @newfiles); - next; - } -} - -foreach $file (@files) { - if(-f $file) { - - print "Adding file $file\n"; - - open(FILE, $file) || die "Could not open file $file\n"; - - $file =~ s-^-/-; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - # for AVR, add PROGMEM here - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "0};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@pfiles, $file); - } -} - -for($i = 0; $i < @fvars; $i++) { - $file = $pfiles[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/makestrings b/Demo/CORTEX_LM3S6965_KEIL/webserver/makestrings deleted file mode 100644 index 8a13c6d29..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/makestrings +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl - - -sub stringify { - my $name = shift(@_); - open(OUTPUTC, "> $name.c"); - open(OUTPUTH, "> $name.h"); - - open(FILE, "$name"); - - while() { - if(/(.+) "(.+)"/) { - $var = $1; - $data = $2; - - $datan = $data; - $datan =~ s/\\r/\r/g; - $datan =~ s/\\n/\n/g; - $datan =~ s/\\01/\01/g; - $datan =~ s/\\0/\0/g; - - printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); - printf(OUTPUTC "/* \"$data\" */\n"); - printf(OUTPUTC "{"); - for($j = 0; $j < length($datan); $j++) { - printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); - } - printf(OUTPUTC "};\n"); - - printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); - - } - } - close(OUTPUTC); - close(OUTPUTH); -} -stringify("http-strings"); - -exit 0; - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/uIP_Task.c b/Demo/CORTEX_LM3S6965_KEIL/webserver/uIP_Task.c deleted file mode 100644 index c6c2f3597..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/uIP_Task.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -#include "lcd_message.h" - -/* uip includes. */ -#include "hw_types.h" - -#include "uip.h" -#include "uip_arp.h" -#include "httpd.h" -#include "timer.h" -#include "clock-arch.h" -#include "hw_ethernet.h" -#include "ethernet.h" -#include "hw_memmap.h" -#include "lmi_flash.h" - -/* Demo includes. */ -#include "emac.h" -#include "partest.h" - -/*-----------------------------------------------------------*/ - -/* IP address configuration. */ -#define uipIP_ADDR0 172 -#define uipIP_ADDR1 25 -#define uipIP_ADDR2 218 -#define uipIP_ADDR3 9 - -/* How long to wait before attempting to connect the MAC again. */ -#define uipINIT_WAIT 100 - -/* Shortcut to the header within the Rx buffer. */ -#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) - -/* Standard constant. */ -#define uipTOTAL_FRAME_HEADER_SIZE 54 - -/*-----------------------------------------------------------*/ - -/* - * Send the uIP buffer to the MAC. - */ -static void prvENET_Send(void); - -/* - * Setup the MAC address in the MAC itself, and in the uIP stack. - */ -static void prvSetMACAddress( void ); - -/* - * Port functions required by the uIP stack. - */ -void clock_init( void ); -clock_time_t clock_time( void ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used by the ISR to wake the uIP task. */ -extern xSemaphoreHandle xEMACSemaphore; - -/*-----------------------------------------------------------*/ - -void clock_init(void) -{ - /* This is done when the scheduler starts. */ -} -/*-----------------------------------------------------------*/ - -clock_time_t clock_time( void ) -{ - return xTaskGetTickCount(); -} -/*-----------------------------------------------------------*/ - -void vuIP_Task( void *pvParameters ) -{ -portBASE_TYPE i; -uip_ipaddr_t xIPAddr; -struct timer periodic_timer, arp_timer; -extern void ( vEMAC_ISR )( void ); - - /* Create the semaphore used by the ISR to wake this task. */ - vSemaphoreCreateBinary( xEMACSemaphore ); - - /* Initialise the uIP stack. */ - timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); - timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); - uip_init(); - uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); - uip_sethostaddr( xIPAddr ); - httpd_init(); - - while( vInitEMAC() != pdPASS ) - { - vTaskDelay( uipINIT_WAIT ); - } - prvSetMACAddress(); - - - for( ;; ) - { - /* Is there received data ready to be processed? */ - uip_len = uiGetEMACRxData( uip_buf ); - - if( uip_len > 0 ) - { - /* Standard uIP loop taken from the uIP manual. */ - - if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) - { - uip_arp_ipin(); - uip_input(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) - { - uip_arp_arpin(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - prvENET_Send(); - } - } - } - else - { - if( timer_expired( &periodic_timer ) ) - { - timer_reset( &periodic_timer ); - for( i = 0; i < UIP_CONNS; i++ ) - { - uip_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - - /* Call the ARP timer function every 10 seconds. */ - if( timer_expired( &arp_timer ) ) - { - timer_reset( &arp_timer ); - uip_arp_timer(); - } - } - else - { - /* We did not receive a packet, and there was no periodic - processing to perform. Block for a fixed period. If a packet - is received during this period we will be woken by the ISR - giving us the Semaphore. */ - xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvENET_Send(void) -{ - vInitialiseSend(); - vIncrementTxLength( uip_len ); - vSendBufferToMAC(); -} -/*-----------------------------------------------------------*/ - -static void prvSetMACAddress( void ) -{ -unsigned portLONG ulUser0, ulUser1; -unsigned char pucMACArray[8]; -struct uip_eth_addr xAddr; - - /* Get the device MAC address from flash */ - FlashUserGet(&ulUser0, &ulUser1); - - /* Convert the MAC address from flash into sequence of bytes. */ - pucMACArray[0] = ((ulUser0 >> 0) & 0xff); - pucMACArray[1] = ((ulUser0 >> 8) & 0xff); - pucMACArray[2] = ((ulUser0 >> 16) & 0xff); - pucMACArray[3] = ((ulUser1 >> 0) & 0xff); - pucMACArray[4] = ((ulUser1 >> 8) & 0xff); - pucMACArray[5] = ((ulUser1 >> 16) & 0xff); - - /* Program the MAC address. */ - EthernetMACAddrSet(ETH_BASE, pucMACArray); - - xAddr.addr[ 0 ] = pucMACArray[0]; - xAddr.addr[ 1 ] = pucMACArray[1]; - xAddr.addr[ 2 ] = pucMACArray[2]; - xAddr.addr[ 3 ] = pucMACArray[3]; - xAddr.addr[ 4 ] = pucMACArray[4]; - xAddr.addr[ 5 ] = pucMACArray[5]; - uip_setethaddr( xAddr ); -} -/*-----------------------------------------------------------*/ - -void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) -{ -char *c, *pcText; -static portCHAR cMessageForDisplay[ 32 ]; -extern xQueueHandle xOLEDQueue; -xOLEDMessage xOLEDMessage; - - /* Process the form input sent by the IO page of the served HTML. */ - - c = strstr( pcInputString, "?" ); - - if( c ) - { - /* Turn LED's on or off in accordance with the check box status. */ - if( strstr( c, "LED0=1" ) != NULL ) - { - vParTestSetLED( 0, 1 ); - } - else - { - vParTestSetLED( 0, 0 ); - } - - /* Find the start of the text to be displayed on the LCD. */ - pcText = strstr( c, "LCD=" ); - pcText += strlen( "LCD=" ); - - /* Terminate the file name for further processing within uIP. */ - *c = 0x00; - - /* Terminate the LCD string. */ - c = strstr( pcText, " " ); - if( c != NULL ) - { - *c = 0x00; - } - - /* Add required spaces. */ - while( ( c = strstr( pcText, "+" ) ) != NULL ) - { - *c = ' '; - } - - /* Write the message to the LCD. */ - strcpy( cMessageForDisplay, pcText ); - xOLEDMessage.pcMessage = cMessageForDisplay; - xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); - } -} - diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/uip-conf.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/uip-conf.h deleted file mode 100644 index 664077d89..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/uip-conf.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1500 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#define UIP_CONF_EXTERNAL_BUFFER - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/CORTEX_LM3S6965_KEIL/webserver/webserver.h b/Demo/CORTEX_LM3S6965_KEIL/webserver/webserver.h deleted file mode 100644 index 1acb290b8..000000000 --- a/Demo/CORTEX_LM3S6965_KEIL/webserver/webserver.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ -#ifndef __WEBSERVER_H__ -#define __WEBSERVER_H__ - -#include "httpd.h" - -typedef struct httpd_state uip_tcp_appstate_t; -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - - -#endif /* __WEBSERVER_H__ */ -- 2.39.5
LocalRemoteStateRetransmissionsTimerFlags