From e76812eb832bb43e716c226307c94763a17574d5 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sun, 30 Mar 2008 21:15:19 +0000 Subject: [PATCH] Add PPC405 port in V10.1 format. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@287 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../RTOSDemo/FreeRTOSConfig.h | 99 + .../RTOSDemo/RTOSDemo_linker_script.ld | 224 ++ .../PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c | 670 ++++ .../RTOSDemo/partest/partest.c | 167 + .../RTOSDemo/serial/serial.c | 227 ++ .../TestApp_Peripheral/executable.elf | Bin 0 -> 76646 bytes .../src/TestApp_Peripheral.c | 107 + .../src/TestApp_Peripheral_LinkScr.ld | 224 ++ .../TestApp_Peripheral/src/gpio_header.h | 12 + .../TestApp_Peripheral/src/intc_header.h | 12 + .../TestApp_Peripheral/src/uartlite_header.h | 11 + .../src/uartlite_intr_header.h | 14 + .../src/xgpio_tapp_example.c | 311 ++ .../src/xintc_tapp_example.c | 263 ++ .../src/xuartlite_intr_tapp_example.c | 461 +++ .../src/xuartlite_selftest_example.c | 147 + .../__xps/.dswkshop/IMG_LicensedCore.bmp | Bin 0 -> 636 bytes .../__xps/.dswkshop/IMG_closeBranch.gif | Bin 0 -> 865 bytes .../__xps/.dswkshop/IMG_openBranch.gif | Bin 0 -> 868 bytes .../.dswkshop/MdtXdsGen_HTMLDatasheet.css | 119 + .../.dswkshop/MdtXdsGen_HTMLDatasheet.xsl | 1211 ++++++++ .../.dswkshop/MdtXdsGen_HTMLIPSection.xsl | 611 ++++ .../.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl | 86 + .../.dswkshop/MdtXdsGen_HTMLPeripherals.xsl | 141 + .../__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl | 235 ++ .../__xps/.dswkshop/MdtXdsSVG_BlkDBifDefs.xsl | 211 ++ .../.dswkshop/MdtXdsSVG_BlkDBusLaneSpaces.xsl | 2365 ++++++++++++++ .../.dswkshop/MdtXdsSVG_BlkDCalculations.xsl | 1146 +++++++ .../.dswkshop/MdtXdsSVG_BlkDDimensions.xsl | 138 + .../.dswkshop/MdtXdsSVG_BlkDModuleDefs.xsl | 29 + .../.dswkshop/MdtXdsSVG_BlkDPeripherals.xsl | 1439 +++++++++ .../__xps/.dswkshop/MdtXdsSVG_BlkdBusses.xsl | 546 ++++ .../__xps/.dswkshop/MdtXdsSVG_BlkdIOPorts.xsl | 512 +++ .../.dswkshop/MdtXdsSVG_BlkdProcessors.xsl | 398 +++ .../.dswkshop/MdtXdsSVG_BlockDiagram.xsl | 2747 +++++++++++++++++ .../__xps/.dswkshop/MdtXdsSVG_Colors.xsl | 131 + .../__xps/.dswkshop/MdtXdsSVG_Render.css | 312 ++ .../__xps/.dswkshop/ds_Report.css | 9 + .../__xps/.dswkshop/ds_Report.js | 27 + .../__xps/.dswkshop/svg10.dtd | 1704 ++++++++++ .../__xps/bitinit.opt | 1 + .../__xps/libgen.opt | 1 + .../__xps/platgen.opt | 2 + .../__xps/rtosdemo_compiler.opt | 20 + .../__xps/simgen.opt | 1 + .../__xps/system.gui | 101 + .../__xps/system_routed | 0 .../__xps/testapp_peripheral_compiler.opt | 20 + .../PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt | 1 + .../__xps/xplorer.opt | 1 + .../__xps/xpsxflow.opt | 1 + .../blkdiagram/svg10.dtd | 1704 ++++++++++ .../blkdiagram/system.css | 312 ++ .../blkdiagram/system.html | 155 + .../blkdiagram/system.svg | 1427 +++++++++ .../PPC405_Xilinx_Virtex4_GCC/data/system.ucf | 339 ++ Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut | 20 + .../etc/download.cmd | 6 + .../etc/fast_runtime.opt | 82 + .../etc/xmd_ppc405_0.opt | 1 + Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt | 5 + Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb | 1 + Demo/PPC405_Xilinx_Virtex4_GCC/system.make | 269 ++ Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs | 180 ++ Demo/PPC405_Xilinx_Virtex4_GCC/system.mss | 76 + Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp | 73 + .../system_incl.make | 141 + Demo/PPC405_Xilinx_Virtex4_GCC/xc95144xl.bsd | 826 +++++ 68 files changed, 22832 insertions(+) create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/executable.elf create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_LicensedCore.bmp create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_closeBranch.gif create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_openBranch.gif create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsSVG_BlkDBifDefs.xsl create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsSVG_BlkDBusLaneSpaces.xsl create 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create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.js create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/bitinit.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system_routed create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt create mode 100644 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Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make create mode 100644 Demo/PPC405_Xilinx_Virtex4_GCC/xc95144xl.bsd diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..47e556786 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,99 @@ +/* + FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) /* Clock setup from start.asm in the demo application. */ +#define configTICK_RATE_HZ ( (portTickType) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_TRACE_FACILITY 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_COUNTING_SEMAPHORES 1 + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define configUSE_RECURSIVE_MUTEXES 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld new file mode 100644 index 000000000..84040a576 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld @@ -0,0 +1,224 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 10.1 EDK_K.15 */ +/* */ +/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : PowerPC405 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400; + +/* Define Memories in the system */ + +MEMORY +{ + SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC +} + +/* Specify the default entry point to the program */ + +ENTRY(_boot) +STARTUP(boot.o) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors : { + __vectors_start = .; + *(.vectors) + __vectors_end = .; +} > SRAM_C_MEM0_BASEADDR + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > SRAM_C_MEM0_BASEADDR + +.init : { + KEEP (*(.init)) +} > SRAM_C_MEM0_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > SRAM_C_MEM0_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.got : { + *(.got) +} > SRAM_C_MEM0_BASEADDR + +.got1 : { + *(.got1) +} > SRAM_C_MEM0_BASEADDR + +.got2 : { + *(.got2) +} > SRAM_C_MEM0_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > SRAM_C_MEM0_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > SRAM_C_MEM0_BASEADDR + +.jcr : { + *(.jcr) +} > SRAM_C_MEM0_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > SRAM_C_MEM0_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + __sbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.bss : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.boot0 0xFFFFFFEC : { + __boot0_start = .; + *(.boot0) + __boot0_end = .; +} + +.boot 0xFFFFFFFC : { + __boot_start = .; + *(.boot) + __boot_end = .; +} + +/* Generate Stack and Heap Sections */ + +.stack : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + __stack = .; +} > SRAM_C_MEM0_BASEADDR + +.heap : { + . = ALIGN(16); + _heap_start = .; + . += _HEAP_SIZE; + . = ALIGN(16); + _heap_end = .; + _end = .; +} > SRAM_C_MEM0_BASEADDR + +} + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c new file mode 100644 index 000000000..5033e1c77 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/main.c @@ -0,0 +1,670 @@ +/* + FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * In addition to the standard demo tasks, the follow demo specific tasks are + * create: + * + * The "Check" task. This only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the other tasks are still operational. Most tasks maintain + * a unique count that is incremented each time the task successfully completes + * its function. Should any error occur within such a task the count is + * permanently halted. The check task inspects the count of each task to ensure + * it has changed since the last time the check task executed. If all the count + * variables have changed all the tasks are still executing error free, and the + * check task toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * The "Register Check" tasks. These tasks fill the CPU registers with known + * values, then check that each register still contains the expected value, the + * discovery of an unexpected value being indicative of an error in the RTOS + * context switch mechanism. The register check tasks operate at low priority + * so are switched in and out frequently. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Xilinx library includes. */ +#include "xcache_l.h" +#include "xintc.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "flop.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "blocktim.h" +#include "death.h" +#include "partest.h" +#include "countsem.h" +#include "recmutex.h" + +/* Priorities assigned to the demo tasks. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The first LED used by the COM test and check tasks respectively. */ +#define mainCOM_TEST_LED ( 4 ) +#define mainCHECK_TEST_LED ( 3 ) + +/* The baud rate used by the comtest tasks is set by the hardware, so the +baud rate parameters passed into the comtest initialisation has no effect. */ +#define mainBAUD_SET_IN_HARDWARE ( 0 ) + +/* Delay periods used by the check task. If no errors have been found then +the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an +error has been found at any time then the toggle rate will increase to +mainERROR_CHECK_DELAY milliseconds. */ +#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) + + +/* + * The tasks defined within this file - described within the comments at the + * head of this page. + */ +static void prvRegTestTask1( void *pvParameters ); +static void prvRegTestTask2( void *pvParameters ); +static void prvErrorChecks( void *pvParameters ); + +/* + * Called by the 'check' task to inspect all the standard demo tasks within + * the system, as described within the comments at the head of this page. + */ +static portSHORT prvCheckOtherTasksAreStillRunning( void ); + +/* + * Perform any hardware initialisation required by the demo application. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they +discover an unexpected value. */ +static unsigned portBASE_TYPE xRegTestStatus = pdPASS; + +/* Counters used to ensure the regtest tasks are still running. */ +static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Must be called prior to installing any interrupt handlers! */ + vPortSetupInterruptController(); + + /* In this case prvSetupHardware() just enables the caches and and + configures the IO ports for the LED outputs. */ + prvSetupHardware(); + + /* Start the standard demo application tasks. Note that the baud rate used + by the comtest tasks is set by the hardware, so the baud rate parameter + passed has no effect. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartQueuePeekTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + + /* Create the tasks defined within this file. */ + xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The suicide tasks must be started last as they record the number of other + tasks that exist within the system. The value is then used to ensure at run + time the number of tasks that exists is within expected bounds. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* Now start the scheduler. Following this call the created tasks should + be executing. */ + vTaskStartScheduler( ); + + /* vTaskStartScheduler() will only return if an error occurs while the + idle task is being created. */ + for( ;; ); + + return 0; +} +/*-----------------------------------------------------------*/ + +static portSHORT prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE lReturn = pdPASS; +static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + /* Have the register test tasks found any errors? */ + if( xRegTestStatus != pdPASS ) + { + lReturn = pdFAIL; + } + + /* Are the register test tasks still looping? */ + if( ulLastRegTest1Counter == ulRegTest1Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest1Counter = ulRegTest1Counter; + } + + if( ulLastRegTest2Counter == ulRegTest2Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest2Counter = ulRegTest2Counter; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + +static void prvErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; +volatile unsigned portBASE_TYPE uxFreeStack; + + /* This call is just to demonstrate the use of the function - nothing is + done with the value. You would expect the stack high water mark to be + lower (the function to return a larger value) here at function entry than + later following calls to other functions. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Again just for demo purposes - uxFreeStack should have a lower value + here than following the call to uxTaskGetStackHighWaterMark() on the + task entry. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED( mainCHECK_TEST_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + XCache_EnableICache( 0x80000000 ); + XCache_EnableDCache( 0x80000000 ); + + /* Setup the IO port for use with the LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvRegTest1Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest1Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTest2Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest2Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTestFail( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + xRegTestStatus = pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask1( void *pvParameters ) +{ + /* The first register test task as described at the top of this file. The + values used in the registers are different to those use in the second + register test task. Also, unlike the second register test task, this task + yields between setting the register values and subsequently checking the + register values. */ + asm volatile + ( + "RegTest1Start: \n\t" \ + " \n\t" \ + " li 0, 301 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 501 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 1 \n\t" \ + " li 2, 2 \n\t" \ + " li 3, 3 \n\t" \ + " li 4, 4 \n\t" \ + " li 5, 5 \n\t" \ + " li 6, 6 \n\t" \ + " li 7, 7 \n\t" \ + " li 8, 8 \n\t" \ + " li 9, 9 \n\t" \ + " li 10, 10 \n\t" \ + " li 11, 11 \n\t" \ + " li 12, 12 \n\t" \ + " li 13, 13 \n\t" \ + " li 14, 14 \n\t" \ + " li 15, 15 \n\t" \ + " li 16, 16 \n\t" \ + " li 17, 17 \n\t" \ + " li 18, 18 \n\t" \ + " li 19, 19 \n\t" \ + " li 20, 20 \n\t" \ + " li 21, 21 \n\t" \ + " li 22, 22 \n\t" \ + " li 23, 23 \n\t" \ + " li 24, 24 \n\t" \ + " li 25, 25 \n\t" \ + " li 26, 26 \n\t" \ + " li 27, 27 \n\t" \ + " li 28, 28 \n\t" \ + " li 29, 29 \n\t" \ + " li 30, 30 \n\t" \ + " li 31, 31 \n\t" \ + " \n\t" \ + " sc \n\t" \ + " nop \n\t" \ + " \n\t" \ + " cmpwi 0, 1 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 2, 2 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 3, 3 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 4, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 5, 5 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 6, 6 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 7, 7 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 8, 8 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 9, 9 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 10, 10 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 11, 11 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 12, 12 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 13, 13 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 14, 14 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 15, 15 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 16, 16 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 17, 17 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 18, 18 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 19, 19 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 20, 20 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 21, 21 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 22, 22 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 23, 23 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 24, 24 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 25, 25 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 26, 26 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 27, 27 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 28, 28 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 29, 29 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 30, 30 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 31, 31 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 301 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 501 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " bl prvRegTest1Pass \n\t" \ + " b RegTest1Start \n\t" \ + " \n\t" \ + "RegTest1Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest1Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask2( void *pvParameters ) +{ + /* The second register test task as described at the top of this file. + Note that this task fills the registers with different values to the + first register test task. */ + asm volatile + ( + "RegTest2Start: \n\t" \ + " \n\t" \ + " li 0, 300 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 500 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 11 \n\t" \ + " li 2, 12 \n\t" \ + " li 3, 13 \n\t" \ + " li 4, 14 \n\t" \ + " li 5, 15 \n\t" \ + " li 6, 16 \n\t" \ + " li 7, 17 \n\t" \ + " li 8, 18 \n\t" \ + " li 9, 19 \n\t" \ + " li 10, 110 \n\t" \ + " li 11, 111 \n\t" \ + " li 12, 112 \n\t" \ + " li 13, 113 \n\t" \ + " li 14, 114 \n\t" \ + " li 15, 115 \n\t" \ + " li 16, 116 \n\t" \ + " li 17, 117 \n\t" \ + " li 18, 118 \n\t" \ + " li 19, 119 \n\t" \ + " li 20, 120 \n\t" \ + " li 21, 121 \n\t" \ + " li 22, 122 \n\t" \ + " li 23, 123 \n\t" \ + " li 24, 124 \n\t" \ + " li 25, 125 \n\t" \ + " li 26, 126 \n\t" \ + " li 27, 127 \n\t" \ + " li 28, 128 \n\t" \ + " li 29, 129 \n\t" \ + " li 30, 130 \n\t" \ + " li 31, 131 \n\t" \ + " \n\t" \ + " cmpwi 0, 11 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 2, 12 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 3, 13 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 4, 14 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 5, 15 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 6, 16 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 7, 17 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 8, 18 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 9, 19 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 10, 110 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 11, 111 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 12, 112 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 13, 113 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 14, 114 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 15, 115 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 16, 116 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 17, 117 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 18, 118 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 19, 119 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 20, 120 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 21, 121 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 22, 122 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 23, 123 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 24, 124 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 25, 125 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 26, 126 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 27, 127 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 28, 128 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 29, 129 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 30, 130 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 31, 131 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 300 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 500 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " bl prvRegTest2Pass \n\t" \ + " b RegTest2Start \n\t" \ + " \n\t" \ + "RegTest2Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest2Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +/* This hook function will get called if there is a suspected stack overflow. +An overflow can cause the task name to be corrupted, in which case the task +handle needs to be used to determine the offending task. */ +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ); +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ) +{ + /* The following three calls are simply to stop compiler warnings about the + functions not being used - they are called from the inline assembly. */ + prvRegTest1Pass(); + prvRegTest2Pass(); + prvRegTestFail(); + + for( ;; ); +} + + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c new file mode 100644 index 000000000..0d8d9c129 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c @@ -0,0 +1,167 @@ +/* + FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xgpio_l.h" + +/* Misc hardware specific definitions. */ +#define partstALL_AS_OUTPUT 0x00 +#define partstCHANNEL_1 0x01 +#define partstMAX_4BIT_LED 0x03 + +/* The outputs are split into two IO sections, these variables maintain the +current value of either section. */ +static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; + +/*-----------------------------------------------------------*/ +/* + * Setup the IO for the LED outputs. + */ +void vParTestInitialise( void ) +{ + /* Set both sets of LED's on the demo board to outputs. */ + XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + + /* Start with all outputs off. */ + uxCurrentOutput4Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); + uxCurrentOutput5Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being set/cleared belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( xValue ) + { + *puxCurrentValue |= uxLED; + } + else + { + *puxCurrentValue &= ~uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being toggled belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( *puxCurrentValue & uxLED ) + { + *puxCurrentValue &= ~uxLED; + } + else + { + *puxCurrentValue |= uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..a610822d7 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c @@ -0,0 +1,227 @@ +/* + FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xuartlite.h" +#include "xuartlite_l.h" + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Structure that maintains information on the UART being used. */ +static XUartLite xUART; + +/* + * Sample UART interrupt handler. Note this is used to demonstrate the kernel + * features and test the port - it is not intended to represent an efficient + * implementation. + */ +static void vSerialISR( XUartLite *pxUART ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* NOTE: The baud rate used by this driver is determined by the hardware + parameterization of the UART Lite peripheral, and the baud value passed to + this function has no effect. */ + ( void ) ulWantedBaud; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Only initialise the UART if the queues were created correctly. */ + if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) ) + { + + XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID ); + XUartLite_ResetFifos( &xUART ); + XUartLite_DisableInterrupt( &xUART ); + + if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS ) + { + /* xPortInstallInterruptHandler() could fail if + vPortSetupInterruptController() has not been called prior to this + function. */ + XUartLite_EnableInterrupt( &xUART ); + } + } + + /* There is only one port so the handle is not used. */ + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one UART. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn = pdTRUE; + + portENTER_CRITICAL(); + { + /* If the UART FIFO is full we can block posting the new data on the + Tx queue. */ + if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* Otherwise, if there is data already in the queue we should add the + new data to the back of the queue to ensure the sequencing is + maintained. */ + else if( uxQueueMessagesWaiting( xCharsForTx ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* If the UART FIFO is not full and there is no data already in the + queue we can write directly to the FIFO without disrupting the + sequence. */ + else + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +static void vSerialISR( XUartLite *pxUART ) +{ +unsigned portLONG ulISRStatus; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE, lDidSomething; +portCHAR cChar; + + do + { + lDidSomething = pdFALSE; + + ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + + if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 ) + { + /* A character is available - place it in the queue of received + characters. This might wake a task that was blocked waiting for + data. */ + cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); + xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx ); + lDidSomething = pdTRUE; + } + + if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) + { + /* There is space in the FIFO - if there are any characters queue for + transmission they can be sent to the UART now. This might unblock a + task that was waiting for space to become available on the Tx queue. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); + lDidSomething = pdTRUE; + } + } + } while( lDidSomething == pdTRUE ); + + /* If we woke any tasks we may require a context switch. */ + if( xTaskWokenByTx || xTaskWokenByRx ) + { + portYIELD_FROM_ISR(); + } +} + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/executable.elf b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/executable.elf new file mode 100644 index 0000000000000000000000000000000000000000..b7d9312eca38ebb7dcb298ead9e50ade8e43face GIT binary patch literal 76646 zcmeEv4}6wox&M7X&%3d)0Rtuu_JR za`pmFYfqMYdb^f;M!Qn)L48)cnnQfJedHf_PioJRdul`^!8-Ar?n@!dmn|4sLSnyz6GPy?oy>zvmbBw^A7f3|C9IM`KRiCro=^3`v|$y z|J}FT|4i}g)bZ(ll~F=|JUTs zv%F_5@Q-eRcX0ksJ{$l4=-zNv|9A_$gYnV-?=e0~lpE+W;4Xi~+wOnQ^ML_xx&Qwk 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INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * Xilinx EDK 10.1 EDK_K.15 + * + * This file is a sample test application + * + * This application is intended to test and/or illustrate some + * functionality of your system. The contents of this file may + * vary depending on the IP in your system and may use existing + * IP driver functions. These drivers will be generated in your + * XPS project when you run the "Generate Libraries" menu item + * in XPS. + * + * Your XPS project directory is at: + * C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\ + */ + + +// Located in: ppc405_0/include/xparameters.h +#include "xparameters.h" + +#include "xcache_l.h" + +#include "xintc.h" +#include "xexception_l.h" +#include "intc_header.h" +#include "xuartlite.h" +#include "uartlite_header.h" +#include "uartlite_intr_header.h" +#include "xbasic_types.h" +#include "xgpio.h" +#include "gpio_header.h" + +//==================================================== + +int main (void) { + + + static XIntc intc; + + XCache_EnableICache(0x00000001); + XCache_EnableDCache(0x00000001); + static XUartLite RS232_Uart_UartLite; + + + { + XStatus status; + +// status = IntcSelfTestExample(XPAR_XPS_INTC_0_DEVICE_ID); + + } + + { + XStatus Status; + +// Status = IntcInterruptSetup(&intc, XPAR_XPS_INTC_0_DEVICE_ID); + + } + + + { + XStatus status; + + // status = UartLiteSelfTestExample(XPAR_RS232_UART_DEVICE_ID); + } + + { + XStatus Status; +// Status = UartLiteIntrExample(&intc, &RS232_Uart_UartLite, \ +// XPAR_RS232_UART_DEVICE_ID, \ +// XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR); + } + + + { + XStatus status; + + status = GpioOutputExample(XPAR_LEDS_4BIT_DEVICE_ID,4); + } + + + { + XStatus status; + + status = GpioOutputExample(XPAR_LEDS_POSITIONS_DEVICE_ID,5); + } + + XCache_DisableDCache(); + XCache_DisableICache(); + return 0; +} + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld new file mode 100644 index 000000000..39fbb5494 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld @@ -0,0 +1,224 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 10.1 EDK_K.15 */ +/* */ +/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : PowerPC405 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +/* Define Memories in the system */ + +MEMORY +{ + SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC +} + +/* Specify the default entry point to the program */ + +ENTRY(_boot) +STARTUP(boot.o) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors : { + __vectors_start = .; + *(.vectors) + __vectors_end = .; +} > SRAM_C_MEM0_BASEADDR + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > SRAM_C_MEM0_BASEADDR + +.init : { + KEEP (*(.init)) +} > SRAM_C_MEM0_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > SRAM_C_MEM0_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.got : { + *(.got) +} > SRAM_C_MEM0_BASEADDR + +.got1 : { + *(.got1) +} > SRAM_C_MEM0_BASEADDR + +.got2 : { + *(.got2) +} > SRAM_C_MEM0_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > SRAM_C_MEM0_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > SRAM_C_MEM0_BASEADDR + +.jcr : { + *(.jcr) +} > SRAM_C_MEM0_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > SRAM_C_MEM0_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + __sbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.bss : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.boot0 0xFFFFFFEC : { + __boot0_start = .; + *(.boot0) + __boot0_end = .; +} + +.boot 0xFFFFFFFC : { + __boot_start = .; + *(.boot) + __boot_end = .; +} + +/* Generate Stack and Heap Sections */ + +.stack : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + __stack = .; +} > SRAM_C_MEM0_BASEADDR + +.heap : { + . = ALIGN(16); + _heap_start = .; + . += _HEAP_SIZE; + . = ALIGN(16); + _heap_end = .; + _end = .; +} > SRAM_C_MEM0_BASEADDR + +} + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h new file mode 100644 index 000000000..1582a545e --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h @@ -0,0 +1,12 @@ +#define TESTAPP_GEN + +/* $Id: gpio_header.h,v 1.1 2007/05/15 06:49:42 mta Exp $ */ + + +#include "xbasic_types.h" +#include "xstatus.h" + +XStatus GpioOutputExample(Xuint16 DeviceId, Xuint32 GpioWidth); +XStatus GpioInputExample(Xuint16 DeviceId, Xuint32 *DataRead); + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h new file mode 100644 index 000000000..08a6f8b96 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h @@ -0,0 +1,12 @@ +#define TESTAPP_GEN + +/* $Id: intc_header.h,v 1.1 2007/05/15 07:08:08 mta Exp $ */ + + +#include "xbasic_types.h" +#include "xstatus.h" + +XStatus IntcSelfTestExample(Xuint16 DeviceId); +XStatus IntcInterruptSetup(XIntc *IntcInstancePtr, Xuint16 DeviceId); + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h new file mode 100644 index 000000000..cb5cbeffc --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h @@ -0,0 +1,11 @@ +#define TESTAPP_GEN + +/* $Id: uartlite_header.h,v 1.1 2007/05/15 07:00:27 mta Exp $ */ + + +#include "xbasic_types.h" +#include "xstatus.h" + +XStatus UartLiteSelfTestExample(Xuint16 DeviceId); + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h new file mode 100644 index 000000000..93a099901 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h @@ -0,0 +1,14 @@ +#define TESTAPP_GEN + +/* $Id: uartlite_intr_header.h,v 1.1 2007/05/15 07:00:27 mta Exp $ */ + + +#include "xbasic_types.h" +#include "xstatus.h" + +XStatus UartLiteIntrExample(XIntc* IntcInstancePtr, \ + XUartLite* UartLiteInstancePtr, \ + Xuint16 UartLiteDeviceId, \ + Xuint16 UartLiteIntrId); + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c new file mode 100644 index 000000000..e5f199a56 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c @@ -0,0 +1,311 @@ +#define TESTAPP_GEN + +/* $Id: xgpio_tapp_example.c,v 1.1 2007/05/15 06:49:42 mta Exp $ */ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2005 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xgpio_tapp_example.c +* +* This file contains a example for using GPIO hardware and driver. +* This example assumes that there is a UART Device or STDIO Device in the +* hardware system. +* +* This example can be run on the Xilinx ML300 board with either the PowerPC or +* the MicroBlaze processor using the Prototype Pins & LEDs of the board +* connected to the GPIO and the Push Buttons connected. +* +* @note +* +* None +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   04/15/05 Initial release for TestApp integration.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xgpio.h" +#include "stdio.h" +#include "xstatus.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constant is used to wait after an LED is turned on to make + * sure that it is visible to the human eye. This constant might need to be + * tuned for faster or slower processor speeds. + */ +#define LED_DELAY 1000000 + +/* following constant is used to determine which channel of the GPIO is + * used if there are 2 channels supported in the GPIO. + */ +#define LED_CHANNEL 1 + +#define LED_MAX_BLINK 0x1 /* Number of times the LED Blinks */ + +#define GPIO_BITWIDTH 16 /* This is the width of the GPIO */ + +#define printf xil_printf /* A smaller footprint printf */ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#ifndef TESTAPP_GEN +#define GPIO_OUTPUT_DEVICE_ID XPAR_LEDS_4BIT_DEVICE_ID +#define GPIO_INPUT_DEVICE_ID XPAR_LEDS_4BIT_DEVICE_ID +#endif /* TESTAPP_GEN */ + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions *******************/ + + +/************************** Function Prototypes ****************************/ + +XStatus GpioOutputExample(Xuint16 DeviceId, Xuint32 GpioWidth); + +XStatus GpioInputExample(Xuint16 DeviceId, Xuint32 *DataRead); + +void GpioDriverHandler(void *CallBackRef); + + + +/************************** Variable Definitions **************************/ + +/* + * The following are declared globally so they are zeroed and so they are + * easily accessible from a debugger + */ +XGpio GpioOutput; /* The driver instance for GPIO Device configured as O/P */ +XGpio GpioInput; /* The driver instance for GPIO Device configured as I/P */ + + +/*****************************************************************************/ +/** +* Main function to call the example.This function is not included if the +* example is generated from the TestAppGen test tool. +* +* @param None +* +* @return XST_SUCCESS if successful, XST_FAILURE if unsuccessful +* +* @note None +* +******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + Xuint32 InputData; + + Status = GpioOutputExample(GPIO_OUTPUT_DEVICE_ID, GPIO_BITWIDTH); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + Status = GpioInputExample(GPIO_INPUT_DEVICE_ID, &InputData); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + printf("Data read from GPIO Input is 0x%x \n", (int)InputData); + + return XST_SUCCESS; +} +#endif + + +/*****************************************************************************/ +/** +* +* This function does a minimal test on the GPIO device configured as OUTPUT +* and driver as a example. +* +* +* @param DeviceId is the XPAR__DEVICE_ID value from +* xparameters.h +* @param GpioWidth is the width of the GPIO +* +* @return XST_SUCCESS if successful, XST_FAILURE if unsuccessful +* +* @note None +* +****************************************************************************/ +XStatus GpioOutputExample(Xuint16 DeviceId, Xuint32 GpioWidth) +{ + Xuint32 Data; + volatile int Delay; + Xuint32 LedBit; + Xuint32 LedLoop; + XStatus Status; + + /* + * Initialize the GPIO driver so that it's ready to use, + * specify the device ID that is generated in xparameters.h + */ + Status = XGpio_Initialize(&GpioOutput, DeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + + /* + * Set the direction for all signals to be outputs + */ + XGpio_SetDataDirection(&GpioOutput, LED_CHANNEL, 0x0); + + /* + * Set the GPIO outputs to low + */ + XGpio_DiscreteWrite(&GpioOutput, LED_CHANNEL, 0x0); + + for (LedBit = 0x0; LedBit < GpioWidth; LedBit++) + { + + for (LedLoop = 0; LedLoop < LED_MAX_BLINK; LedLoop++) + { + + /* + * Set the GPIO Output to High + */ + XGpio_DiscreteWrite(&GpioOutput, LED_CHANNEL, 1 << LedBit); + +#ifndef __SIM__ + /* + * Wait a small amount of time so the LED is visible + */ + for (Delay = 0; Delay < LED_DELAY; Delay++); + +#endif + /* + * Read the state of the data so that it can be verified + */ + /* Data = XGpio_DiscreteRead(&GpioOutput, LED_CHANNEL); */ + + + /* + * If the data read back is not the same as the data + * written then return FAILURE + */ + /*if (Data != (1 << LedBit)) + { + return XST_FAILURE; + }*/ + + + /* + * Clear the GPIO Output + */ + XGpio_DiscreteClear(&GpioOutput, LED_CHANNEL, 1 << LedBit); + + + /* + * Read the state of the data so that it can be verified + */ + /* Data = XGpio_DiscreteRead(&GpioOutput, LED_CHANNEL);*/ + + + /* + * If the data read back is not the same as the data + * written then return FAILURE + */ + /* if (Data & ( 1 << LedBit)) + { + return XST_FAILURE; + }*/ + + +#ifndef __SIM__ + /* + * Wait a small amount of time so the LED is visible + */ + for (Delay = 0; Delay < LED_DELAY; Delay++); +#endif + + } + + } + + return XST_SUCCESS; + +} + + +/******************************************************************************/ +/** +* +* This function performs a test on the GPIO driver/device with the GPIO +* configured as INPUT +* +* @param DeviceId is the XPAR__DEVICE_ID value from +* xparameters.h +* @param DataRead is the pointer where the data read from GPIO Input is +* returned +* +* @return XST_SUCCESS if the Test is successful, otherwise XST_FAILURE +* +* @note None. +* +******************************************************************************/ +XStatus GpioInputExample(Xuint16 DeviceId, Xuint32 *DataRead) +{ + XStatus Status; + + /* + * Initialize the GPIO driver so that it's ready to use, + * specify the device ID that is generated in xparameters.h + */ + Status = XGpio_Initialize(&GpioInput, DeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Set the direction for all signals to be inputs + */ + XGpio_SetDataDirection(&GpioInput, LED_CHANNEL, 0xFFFFFFFF); + + /* + * Read the state of the data so that it can be verified + */ + *DataRead = XGpio_DiscreteRead(&GpioInput, LED_CHANNEL); + + return XST_SUCCESS; + +} + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c new file mode 100644 index 000000000..de77eac89 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c @@ -0,0 +1,263 @@ +#define TESTAPP_GEN + + +/* $Id: xintc_tapp_example.c,v 1.1 2007/05/15 07:08:09 mta Exp $ */ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002-2006 Xilinx Inc. +* All rights reserved. +* +*******************************************************************************/ +/******************************************************************************/ +/** +* +* @file xintc_tapp_example.c +* +* This file contains a self test example using the Interrupt Controller driver +* (XIntc) and hardware device. Please reference other device driver examples to +* see more examples of how the intc and interrupts can be used by a software +* application. +* +* This example shows the use of the Interrupt Controller both with a PowerPC405 +* and MicroBlaze processor. +* +* The TestApp Gen utility uses this file to perform the self test and setup +* of intc for interrupts. +* +* @note +* +* None +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a sv   06/29/05  Created for Test App Integration
+* 1.00c sn   05/09/06  Added Interrupt Setup Function
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xstatus.h" +#include "xintc.h" +#ifdef __MICROBLAZE__ +#include "mb_interface.h" +#endif +#ifdef __PPC__ +#include "xexception_l.h" +#endif + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. This definition is not + * included if the example is generated from the TestAppGen test tool. + */ +#ifndef TESTAPP_GEN +#define INTC_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#endif + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus IntcSelfTestExample(Xuint16 DeviceId); +XStatus IntcInterruptSetup(XIntc *IntcInstancePtr, Xuint16 DeviceId); + +/************************** Variable Definitions *****************************/ + +static XIntc InterruptController; /* Instance of the Interrupt Controller */ + + +/*****************************************************************************/ +/** +* +* This is the main function for the Interrupt Controller example. This +* function is not included if the example is generated from the TestAppGen test +* tool. +* +* @param None. +* +* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the Intc example , specify the Device ID generated in xparameters.h + */ + Status = IntcSelfTestExample(INTC_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} +#endif + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the driver/device. This is a destructive +* test. This function is an example of how to use the interrupt controller +* driver component (XIntc) and the hardware device. This function is designed +* to work without any hardware devices to cause interrupts. It may not return +* if the interrupt controller is not properly connected to the processor in +* either software or hardware. +* +* This function relies on the fact that the interrupt controller hardware +* has come out of the reset state such that it will allow interrupts to be +* simulated by the software. +* +* @param DeviceId is device ID of the Interrupt Controller Device , typically +* XPAR__DEVICE_ID value from xparameters.h +* +* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE +* +* @note None. +* +******************************************************************************/ +XStatus IntcSelfTestExample(Xuint16 DeviceId) +{ + XStatus Status; + + /* + * Initialize the interrupt controller driver so that it is ready to use. + */ + Status = XIntc_Initialize(&InterruptController, DeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + + /* + * Perform a self-test to ensure that the hardware was built correctly + */ + Status = XIntc_SelfTest(&InterruptController); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} + + +/*****************************************************************************/ +/** +* +* This function is used by the TestAppGen generated application to setup +* the interrupt controller. +* +* @param IntcInstancePtr is the reference to the Interrupt Controller +* instance. +* @param DeviceId is device ID of the Interrupt Controller Device , typically +* XPAR__DEVICE_ID value from xparameters.h +* +* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE +* +* @note None. +* +******************************************************************************/ +XStatus IntcInterruptSetup(XIntc *IntcInstancePtr, Xuint16 DeviceId) +{ + + XStatus Status; + + /* + * Initialize the interrupt controller driver so that it is ready to use. + */ + Status = XIntc_Initialize(IntcInstancePtr, DeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Perform a self-test to ensure that the hardware was built correctly. + */ + Status = XIntc_SelfTest(IntcInstancePtr); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + +#ifdef __MICROBLAZE__ + /* + * Enable the microblaze Interrupts + */ + microblaze_enable_interrupts(); +#endif + +#ifdef __PPC__ /*PPC*/ + + /* + * Initialize the PPC405 exception table + */ + XExc_Init(); + + /* + * Register the interrupt controller handler with the exception table + */ + XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, + (XExceptionHandler)XIntc_DeviceInterruptHandler, + (void*) 0); + + /* + * Enable non-critical exceptions + */ + XExc_mEnableExceptions(XEXC_NON_CRITICAL); +#endif + + + /* + * Start the interrupt controller such that interrupts are enabled for + * all devices that cause interrupts. + */ + Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c new file mode 100644 index 000000000..09109b82e --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c @@ -0,0 +1,461 @@ +#define TESTAPP_GEN + +/* $Id: xuartlite_intr_tapp_example.c,v 1.1 2007/05/15 07:00:27 mta Exp $ */ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002-2006 Xilinx Inc. +* All rights reserved. +* +*******************************************************************************/ +/******************************************************************************/ +/** +* +* @file xuartlite_intr_tapp_example.c +* +* This file contains a design example using the UartLite driver and +* hardware device using the interrupt mode for transmission of data. +* +* This example works with a PPC processor. Refer the examples of Interrupt +* controller for an example of using interrupts with the MicroBlaze processor. +* +* @note +* +* None. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b sv   06/08/06 Created for supporting Test App Interrupt examples
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xuartlite.h" +#include "xintc.h" + +#ifdef __MICROBLAZE__ +#include "mb_interface.h" +#else +#include "xexception_l.h" +#endif + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#ifndef TESTAPP_GEN +#define UARTLITE_DEVICE_ID XPAR_RS232_UART_DEVICE_ID +#define INTC_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define UARTLITE_IRPT_INTR XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR +#endif + +/* + * The following constant controls the length of the buffers to be sent + * and received with the UartLite device. + */ +#define TEST_BUFFER_SIZE 100 + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus UartLiteIntrExample(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstancePtr, + Xuint16 UartLiteDeviceId, + Xuint16 UartLiteIntrId); + + +static void UartLiteSendHandler(void *CallBackRef, unsigned int EventData); + +static void UartLiteRecvHandler(void *CallBackRef, unsigned int EventData); + + +static XStatus UartLiteSetupIntrSystem(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstancePtr, + Xuint16 UartLiteIntrId); + +static void UartLiteDisableIntrSystem(XIntc *IntrInstancePtr, + Xuint16 UartLiteIntrId); + + +/************************** Variable Definitions *****************************/ + +/* + * The instances to support the device drivers are global such that the + * are initialized to zero each time the program runs. + */ +#ifndef TESTAPP_GEN +static XIntc IntcInstance; /* The instance of the Interrupt Controller */ +static XUartLite UartLiteInst; /* The instance of the UartLite Device */ +#endif + + + +/* + * The following variables are shared between non-interrupt processing and + * interrupt processing such that they must be global. + */ + +/* + * The following buffers are used in this example to send and receive data + * with the UartLite. + */ +Xuint8 SendBuffer[TEST_BUFFER_SIZE]; +Xuint8 ReceiveBuffer[TEST_BUFFER_SIZE]; + +/* + * The following counter is used to determine when the entire buffer has + * been sent. + */ +static volatile int TotalSentCount; + + +/******************************************************************************/ +/** +* +* Main function to call the UartLite interrupt example. +* +* @param None. +* +* @return XST_SUCCESS if successful, else XST_FAILURE. +* +* @note None +* +*******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the UartLite Interrupt example , specify the Device ID that is + * generated in xparameters.h. + */ + Status = UartLiteIntrExample(&IntcInstance, + &UartLiteInst, + UARTLITE_DEVICE_ID, + UARTLITE_IRPT_INTR); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif + +/****************************************************************************/ +/** +* +* This function does a minimal test on the UartLite device and driver as a +* design example. The purpose of this function is to illustrate how to use +* the XUartLite component. +* +* This function sends data and expects to receive the same data through the +* UartLite. The user must provide a physical loopback such that data which +* is transmitted will be received. +* +* This function uses the interrupt driver mode of the UartLite. The calls to +* the UartLite driver in the interrupt handlers, should only use the +* non-blocking calls. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC component. +* @param UartLiteInstPtr is a pointer to the instance of UartLite component. +* @param UartLiteDeviceId is the Device ID of the UartLite Device and is the +* XPAR__DEVICE_ID value from xparameters.h. +* @param UartLiteIntrId is the Interrupt ID and is typically +* XPAR___IP2INTC_IRPT_INTR +* value from xparameters.h. +* +* @return XST_SUCCESS if successful, otherwise XST_FAILURE. +* +* @note +* +* This function contains an infinite loop such that if interrupts are not +* working it may never return. +* +****************************************************************************/ +XStatus UartLiteIntrExample(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstPtr, + Xuint16 UartLiteDeviceId, + Xuint16 UartLiteIntrId) + +{ + XStatus Status; + Xuint32 Index; + + /* + * Initialize the UartLite driver so that it's ready to use. + */ + Status = XUartLite_Initialize(UartLiteInstPtr, UartLiteDeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Perform a self-test to ensure that the hardware was built correctly. + */ + Status = XUartLite_SelfTest(UartLiteInstPtr); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Connect the UartLite to the interrupt subsystem such that interrupts can + * occur. This function is application specific. + */ + Status = UartLiteSetupIntrSystem(IntcInstancePtr, + UartLiteInstPtr, + UartLiteIntrId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Setup the handlers for the UartLite that will be called from the + * interrupt context when data has been sent and received, + * specify a pointer to the UartLite driver instance as the callback + * reference so the handlers are able to access the instance data. + */ + XUartLite_SetSendHandler(UartLiteInstPtr, UartLiteSendHandler, + UartLiteInstPtr); + XUartLite_SetRecvHandler(UartLiteInstPtr, UartLiteRecvHandler, + UartLiteInstPtr); + + /* + * Enable the interrupt of the UartLite so that the interrupts will occur. + */ + XUartLite_EnableInterrupt(UartLiteInstPtr); + + /* + * Initialize the send buffer bytes with a pattern to send. + */ + for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) + { + SendBuffer[Index] = Index; + } + + /* + * Send the buffer using the UartLite. + */ + XUartLite_Send(UartLiteInstPtr, SendBuffer, TEST_BUFFER_SIZE); + + /* + * Wait for the entire buffer to be transmitted, the function may get + * locked up in this loop if the interrupts are not working correctly. + */ + while ((TotalSentCount != TEST_BUFFER_SIZE)) + { + } + + + UartLiteDisableIntrSystem(IntcInstancePtr, UartLiteIntrId); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function is the handler which performs processing to send data to the +* UartLite. It is called from an interrupt context such that the amount of +* processing performed should be minimized. It is called when the transmit +* FIFO of the UartLite is empty and more data can be sent through the UartLite. +* +* This handler provides an example of how to handle data for the UartLite, but +* is application specific. +* +* @param CallBackRef contains a callback reference from the driver. +* In this case it is the instance pointer for the UartLite driver. +* @param EventData contains the number of bytes sent or received for sent and +* receive events. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +static void UartLiteSendHandler(void *CallBackRef, unsigned int EventData) +{ + TotalSentCount = EventData; +} + +/****************************************************************************/ +/** +* +* This function is the handler which performs processing to receive data from +* the UartLite. It is called from an interrupt context such that the amount of +* processing performed should be minimized. It is called when any data is +* present in the receive FIFO of the UartLite such that the data can be +* retrieved from the UartLite. The amount of data present in the FIFO is not +* known when this function is called. +* +* This handler provides an example of how to handle data for the UartLite, but +* is application specific. +* +* @param CallBackRef contains a callback reference from the driver, in this +* case it is the instance pointer for the UartLite driver. +* @param EventData contains the number of bytes sent or received for sent and +* receive events. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +static void UartLiteRecvHandler(void *CallBackRef, unsigned int EventData) +{ + +} + +/****************************************************************************/ +/** +* +* This function setups the interrupt system such that interrupts can occur +* for the UartLite. This function is application specific since the actual +* system may or may not have an interrupt controller. The UartLite could be +* directly connected to a processor without an interrupt controller. The +* user should modify this function to fit the application. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC component. +* @param UartLiteInstPtr is a pointer to the instance of UartLite component. +* XPAR__DEVICE_ID value from xparameters.h. +* @param UartLiteIntrId is the Interrupt ID and is typically +* XPAR___IP2INTC_IRPT_INTR +* value from xparameters.h. +* +* @return XST_SUCCESS if successful, otherwise XST_FAILURE. +* +* @note None. +* +****************************************************************************/ +XStatus UartLiteSetupIntrSystem(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstPtr, + Xuint16 UartLiteIntrId) +{ + XStatus Status; + +#ifndef TESTAPP_GEN + /* + * Initialize the interrupt controller driver so that it is ready to use. + */ + Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } +#endif + + /* + * Connect a device driver handler that will be called when an interrupt + * for the device occurs, the device driver handler performs the specific + * interrupt processing for the device. + */ + Status = XIntc_Connect(IntcInstancePtr, UartLiteIntrId, + (XInterruptHandler)XUartLite_InterruptHandler, + (void *)UartLiteInstPtr); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + +#ifndef TESTAPP_GEN + /* + * Start the interrupt controller such that interrupts are enabled for + * all devices that cause interrupts, specific real mode so that + * the UART can cause interrupts thru the interrupt controller. + */ + Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } +#endif + + /* + * Enable the interrupt for the UartLite. + */ + XIntc_Enable(IntcInstancePtr, UartLiteIntrId); + +#ifndef TESTAPP_GEN + + /* + * Initialize the PPC exception table. + */ + XExc_Init(); + + /* + * Register the interrupt controller handler with the exception table. + */ + XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, + (XExceptionHandler)XIntc_InterruptHandler, + IntcInstancePtr); + + /* + * Enable non-critical exceptions. + */ + XExc_mEnableExceptions(XEXC_NON_CRITICAL); + + +#endif /* TESTAPP_GEN */ + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the interrupts that occur for the UartLite. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC component. +* @param UartLiteIntrId is the Interrupt ID and is typically +* XPAR___IP2INTC_IRPT_INTR +* value from xparameters.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void UartLiteDisableIntrSystem(XIntc *IntcInstancePtr, + Xuint16 UartLiteIntrId) +{ + + /* + * Disconnect and disable the interrupt for the UartLite + */ + XIntc_Disconnect(IntcInstancePtr, UartLiteIntrId); + +} + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c new file mode 100644 index 000000000..c4340633f --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c @@ -0,0 +1,147 @@ +#define TESTAPP_GEN + +/* $Id: xuartlite_selftest_example.c,v 1.1 2007/05/15 07:00:27 mta Exp $ */ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2005 Xilinx Inc. +* All rights reserved. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartlite_selftest_example.c +* +* This file contains a design example using the UartLite driver (XUartLite) and +* hardware device. +* +* @note +* +* None +* +* MODIFICATION HISTORY: +* 
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/25/04 First Release.
+* 1.00a sv   06/13/05 Minor changes to comply to Doxygen and Coding guidelines
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xuartlite.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define UARTLITE_DEVICE_ID XPAR_RS232_UART_DEVICE_ID + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus UartLiteSelfTestExample(Xuint16 DeviceId); + +/************************** Variable Definitions *****************************/ + +XUartLite UartLite; /* Instance of the UartLite device */ + +/*****************************************************************************/ +/** +* +* Main function to call the example. This function is not included if the +* example is generated from the TestAppGen test tool. +* +* @param None. +* +* @return XST_SUCCESS if succesful, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the UartLite self test example, specify the the Device ID that is + * generated in xparameters.h + */ + Status = UartLiteSelfTestExample(UARTLITE_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} +#endif + +/*****************************************************************************/ +/** +* +* This function does a minimal test on the UartLite device and driver as a +* design example. The purpose of this function is to illustrate +* how to use the XUartLite component. +* +* +* @param DeviceId is the XPAR__DEVICE_ID value from +* xparameters.h. +* +* @return XST_SUCCESS if succesful, otherwise XST_FAILURE. +* +* @note None. +* +****************************************************************************/ +XStatus UartLiteSelfTestExample(Xuint16 DeviceId) +{ + XStatus Status; + + /* + * Initialize the UartLite driver so that it is ready to use. + */ + Status = XUartLite_Initialize(&UartLite, DeviceId); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + /* + * Perform a self-test to ensure that the hardware was built correctly. + */ + Status = XUartLite_SelfTest(&UartLite); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_LicensedCore.bmp b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_LicensedCore.bmp new file mode 100644 index 0000000000000000000000000000000000000000..739605f2c6a7f46562c9c3b5230b6d0988fefa9f GIT binary patch literal 636 zcmZ?rtzlvSgDOS_1`Qxf0E!tII3N;0QivOZ1A%N1o;GbdgTurB4Bk)vF=!MmVrXb+ zW@!2Jhhf&NxeUIG+!^8%5*SiaQW-pE@iJs&W;1xsHDZ`EXD-9UiIW%>EndWso14oJ zx+;xf`u6h-7cN|4aIRUwpph|y!Mb@3L+!^u46SYLKrF-3+f@zhRir+rqGO=N<;neajhKcg$u;N=jykj*ez1EG%Zw zXb=mNq5tti zhWy*t7<7SlMem)-VA{NvL8EpZgMZ6fhVqIk2Jy@P8Tc;zV^FVI$H02_Kg0k3|H0wv z?=Qmaq2(?n=IAQLEaDFY%zi$M;&O(pOx}LXAil4kkDWD_gSNi6pD&cJX0K?jql(}& zx(KrKm>~EHJZ8Ee{V?@LPNp_ovIst-8@r$-OkNaZpR*oFy(q|hAx|){wK9+q0`dJ> z7+8QLnYdv9IO<(br2lVL2D_cP{pY}f{J96II@@l| zBo2<^OBAR0%l8n?@aKjkC+D1ecW-}pYx`(Xi~1*3M^;6ZS6P)h%dCt_ue3^aF|r~m zyuvEfy`JS!?&Vgl9@k(Wu2r{D3CY*a0U5qY&1BL7GWu!GpzM1Fb$$cT*-O z#KkZYeXJ!j_2Xz?$Gy8aPS`e&t90)$x?LaM_2{spk1!NA(jeV889W+zK=T~966T?a zRp(mbA@but$BW0=nO?ckpZ-s1@>W0R*Cs#KKb=pOSKnM6++SbJExrHp^7P^Q>&n9G m+q-Y~zo*YPKmS?zezH4#_VGA>-5meDT>mhAb$NF9PCHLlkz}6$ literal 0 HcmV?d00001 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_openBranch.gif b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/IMG_openBranch.gif new file mode 100644 index 0000000000000000000000000000000000000000..d9e7ef561c004388f1cf628b5a3c27e3d4a14c72 GIT binary patch literal 868 zcmchWu}a-x48_j{kt;Y{aS;)z6rEfoON&J)Vykqha|cC-Or44kpit=GBsdtS_7U7V zcW}xJbn^k+OQ-ag?;)Du&kadV&N=z+`=fWSUZ2f0(;ulivMQ>)%Bs{^W@S`*rB$kn zkrh$l6;`3{^(>EaFSl~_sAXA{d6|_7q*9imC-O|;h=(R}mG)og48BImXQYtO0{GETKh>#b5&s7Q<>mof95m5o&#` zC36qAaJ5`mP&5y-Frgk&^oBfSA>`o)G?~T@^g{xLum%j$u%s0pECw5Bu++|VnVc|p zwUOv!Et#2{@D;hRpy)CeKH@Y6z>9W_MlDw22Q-<+4mcqgg|G$;(o8}N9xMhMX!VJ@ zn=&~eE{2ilV=bAfA4mH-?%l<4!nS!_rF)0b?fUSpM~5AKgrTsJ2I;=Z;L*SXn&-fk zFb_?vy3!I4kstp#HvY~{dgXS1`ahxRTRkkSO~1dmyqYerzPUSo`t@yoY476a@%h2$ r<%N@6dHC^oy}sj%zi(b1-fVune?HvV{BS!v{j|OEWo!TIWTM@FCr)7- literal 0 HcmV?d00001 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css new file mode 100644 index 000000000..c1b40cf88 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css @@ -0,0 +1,119 @@ + text.busintlabel { + fill: #810017; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.proclabel { + fill: #810017; + stroke: none; + font-size: 14pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.opblabel { + fill: #339900; + stroke: none; + font-size: 11pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.lmblabel { + fill: #9999FF; + stroke: none; + font-size: 11pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl new file mode 100644 index 000000000..f91415383 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl @@ -0,0 +1,1211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Table of Contents + + + + + + + + + + + + + +EDK Project Report + + + + + + + + + + +Block Diagram + + + + + + + + + + + BlockDiagram + +

+

+ +

+ + + + + + + + + + EDK PROJECT REPORT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ Printable Version +
+ + + + +

+

+ +
+ + + + +

+

+ BlockDiagram +
+ + + + +

+

+ +
+ + + + +

+ + + + + + + + + + + + +
+ +
+ +
+
+ + + + + + + + + + +
+ +
+
+ + + + + + + + + + +
+ +
+
+ + + + + + + + + + +
+ +
+
+

+ + + + + + + + + + +
+ +
+ +
+ + + + + + + + + + + +
+ +
+
+ + + + + + + + + + + +
+ +
+
+ + + + + + + + + + + +
+ +
+
+ + + + +

+ + + + + + + +
+ +
+
+ + + + +

+

+ +
+

+

+ + + + + +
line
+ + + www.xilinx.com +

+ 1-800-255-7778 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TABLE OF CONTENTS
+

+ Overview + +

+ Block Diagram + +

+ External Ports + + + +

+ + + Processors + + + Processor + + + + +

+     + +

+           memory map + + + + +

+ Debuggers + + +

+     + + + + +

+ Interrupt Controllers + + +

+     + + + + +

+ Busses + + +

+     + + + + +

+ Bridges + + +

+     + + + + +

+ Memory + + +

+     + + + + +

+ Memory Controllers + + +

+     + + + + +

+ Peripherals + + +

+     + + + + +

+ IP + + +

+     + + + +

+ Timing Information +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ Overview +
+ Generated on + + +
+ Source + + + + + +
+ EDK Version + + + + + + NA + +
+ FPGA Family + + + + + + NA + +
+ Device + + + + + + - + +
+ # IP Instantiated + + +
+ # Processors + + +
+ # Busses + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EXTERNAL PORTS
+ + These are the external ports defined in the MHS file. + +
+ Attributes Key +

+ The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file +

+ CLK +   indicates Clock ports, (SIGIS = CLK)  +

+ INTR +   indicates Interrupt ports,(SIGIS = INTR)  +

+ RESET +   indicates Reset ports, (SIGIS = RST)  +

+ BUF or REG +   Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
+ 		+   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
 
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Post Synthesis Clock Limits
+ + No clocks could be identified in the design. Run platgen to generate synthesis information. + + + + These are the post synthesis clock frequencies. The critical frequencies are marked with + + + green. + +

+ + The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. + +
MODULECLK PortMAX FREQ
+ + + + + + + + + + + +
+ + + + + + +

+

+

+ + + + + + + + +
TOCTOP
+ + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl new file mode 100644 index 000000000..4e7beaa51 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl @@ -0,0 +1,611 @@ + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + +    + + +

+ + + + + +

+

+

+
+ {@INSTANCE} IP Image + + +

+

+
+ +
+ +

+

+ + + + + + + + + + + 1 + 0 + + + + + + + + + + 1 + 0 + + + + + + + 4 + 2 + + + + 2 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
General
IP Core + + + + + + + + + + +
Version
Driver + + API + +
License
TYPE + +
EXPIRES ON + +
Parameters
+ + These are parameters set for this module. + + Refer to the IP documentation for complete information about module parameters. + + +

+ + Parameters marked with + + yellow + + indicate parameters set by the user. + +

+ + Parameters marked with + + blue + + indicate parameters set by the system. + +
NameValue
+ + + + +
+ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
+ + + + +
+ + + + +
+ 		+ + +
 
+ 		+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
+ + + + +
+ + + + +
 
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Post Synthesis Device Utilization
+ + Device utilization information is not available for this IP. Run platgen to generate synthesis information. + +
Resource TypeUsedAvailablePercent
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NA + + + + + + + + NA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
+ + The ports listed here are only those connected in the MHS file. + + Refer to the IP documentation for complete information about module ports. + + +
#NAMEDIR[LSB:MSB]SIGNAL
:1
+ Bus Interfaces +
MASTERSHIPNAMESTDBUSP2P
Bus Connections
TYPENAMEBIF
+ Interrupt Priorities +
PrioritySIGMODULE
+ + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl new file mode 100644 index 000000000..96e9f0cc7 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl @@ -0,0 +1,86 @@ + + + + + +]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ■ +   + + + + + ■ + + +   + + + + + + + + + + + + +
+ + MEMORY MAP +
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
DIBASEHIGHMODULE
+ + : + +
+ + + + + + + + + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl new file mode 100644 index 000000000..c3f6b3239 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl @@ -0,0 +1,141 @@ + + + + + + + + + + + + + + + +

+

+

+

+ + + +

+ ________________________________________________ + +

+

+ + + + + +
+ + + + +
+ {@INSTANCE} IP Image +
+ +
+ 		+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
General
Type
Version
Parameters
+ + The paramaters listed here are only those set in the MHS file. Refer to the IP + documentation for complete information about module parameters. + +
NameValue
Device Utilization
+ + Device utilization information is not available for this IP. + + Resource TypeUsedAvailablePercent
+ + + + + + + + + + + + + + + + + + + + + + + +
PINOUT
+ + The ports listed here are only those connected in the MHS file. Refer to the IP + documentation for complete information about module ports. + +
#NAMEDIRSIGNAL
+ + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl new file mode 100644 index 000000000..862b7107b --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl @@ -0,0 +1,235 @@ + + + + + + +Table of Contents + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TABLE OF CONTENTS
+

+ Overview + +

+ Block Diagram + +

+ External Ports + +

+ + + +
+ + Processors  + + + Processor  + + +
+ + + + +    

+ +           memory map

+ + + + + + +
+ Debuggers  + +
+ + + + +    

+ + + + + + +
+ Interrupt Controllers  + +
+ + + + +    

+ + + + + +
+ Busses  + +
+ + + + +    

+ + + + + +
+ Bridges  + +
+ + + +    

+ + + + + +
+ Memory  + +
+ + + +    

+ + + + + +
+ Memory Controllers  + +
+ + + +    

+ + + + + +
+ Peripherals  + +
+ + + +    

+ + + + + +
+ IP  + +
+ + + +    

+ + + + + Timing Information

+ + +
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italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ioplblgrp { + fill: #000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + tspan.iopgrp { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: 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font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.keylblul { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + text-decoration: underline; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.specsvalue { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsvaluemid { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.intrsymbol { + fill: #000000; + stroke: none; + font-size: 8pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.css b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.css new file mode 100644 index 000000000..a5edc929d --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.css @@ -0,0 +1,9 @@ + .trigger{ + cursor : hand; + cursor : pointer; + } + + .branch{ + display : none; + margin-left : 16px; + } \ No newline at end of file diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.js b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.js new file mode 100644 index 000000000..126889b7f --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/ds_Report.js @@ -0,0 +1,27 @@ + + var openImg = new Image(); + openImg.src = "imgs/IMG_openBranch.gif"; + + var closeImg = new Image(); + closeImg.src = "imgs/IMG_closeBranch.gif"; + + function showBranch(branchId) { + + var branchObj = document.getElementById(branchId).style; + + if(branchObj.display== "block") + branchObj.display = "none"; + else + branchObj.display = "block"; + } + + function swapBranchImg(branchImgId) { + + branchImg = document.getElementById(branchImgId); + + if(branchImg.src.indexOf('IMG_closeBranch.gif') > -1) + branchImg.src = openImg.src; + else + branchImg.src = closeImg.src; + } + \ No newline at end of file diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd @@ -0,0 +1,1704 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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file mode 100644 index 000000000..3645236a6 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/bitinit.opt @@ -0,0 +1 @@ + -pe ppc405_0 $(PPC405_0_BOOTLOOP) diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt new file mode 100644 index 000000000..77b154845 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex4 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt new file mode 100644 index 000000000..25299b7db --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc4vfx12ff668-10 -lang vhdl + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..e3a95656b --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt @@ -0,0 +1,20 @@ +ppc405_0 +RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c +RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= + $(RTOSDEMO_CC_INFERRED_FLAGS) \ diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt new file mode 100644 index 000000000..547618f96 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -pe ppc405_0 $(PPC405_0_BOOTLOOP) -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/ -E C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/ diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui new file mode 100644 index 000000000..ff6232e64 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system.gui @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system_routed b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/system_routed new file mode 100644 index 000000000..e69de29bb diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt new file mode 100644 index 000000000..d6693d0bf --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt @@ -0,0 +1,20 @@ +ppc405_0 +TESTAPP_PERIPHERAL_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c +TESTAPP_PERIPHERAL_HEADERS = /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h +TESTAPP_PERIPHERAL_CC = powerpc-eabi-gcc +TESTAPP_PERIPHERAL_CC_SIZE = powerpc-eabi-size +TESTAPP_PERIPHERAL_CC_OPT = -O2 +TESTAPP_PERIPHERAL_CFLAGS = +TESTAPP_PERIPHERAL_CC_SEARCH = # -B +TESTAPP_PERIPHERAL_LIBPATH = -L./ppc405_0/lib/ # -L +TESTAPP_PERIPHERAL_INCLUDES = -I./ppc405_0/include/ -ITestApp_Peripheral/src/ # -I +TESTAPP_PERIPHERAL_LFLAGS = # -l +TESTAPP_PERIPHERAL_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld +TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g +TESTAPP_PERIPHERAL_CC_PROFILE_FLAG = # -pg +TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -msdata=eabi +TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS= +TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= + $(TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS) \ diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt new file mode 100644 index 000000000..8ea8f6640 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/vpgen.opt @@ -0,0 +1 @@ + -p xc4vfx12ff668-10 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt new file mode 100644 index 000000000..37e5b1190 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xplorer.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10data/system.ucf7 0 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt new file mode 100644 index 000000000..33391f035 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10data/system.ucf 0 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd @@ -0,0 +1,1704 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ioplblgrp { + fill: #000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + tspan.iopgrp { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: Arial Courier san-serif; + } + + + text.biflabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.p2pbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.sharedbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.bciplabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.bciptype { + fill: #AA0017; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.splitbustxt { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: sans-serif; + } + + text.horizp2pbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.keytitle { + fill: #AA0017; + stroke: none; + font-size: 12pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keyheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keylabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.keylblul { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + text-decoration: underline; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.specsvalue { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsvaluemid { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.intrsymbol { + fill: #000000; + stroke: none; + font-size: 8pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html new file mode 100644 index 000000000..39f83488e --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.html @@ -0,0 +1,155 @@ + + + +Block Diagram + + +

+ + + + + + + +
EXTERNAL PORTS
+ These are the external ports defined in the MHS file. +
+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ +fpga_0_RS232_Uart_RX_pinI1fpga_0_RS232_Uart_RX
+ +fpga_0_RS232_Uart_TX_pinO1fpga_0_RS232_Uart_TX
+ +fpga_0_LEDs_4Bit_GPIO_IO_pinIO0:3fpga_0_LEDs_4Bit_GPIO_IO
+ +fpga_0_LEDs_Positions_GPIO_IO_pinIO0:4fpga_0_LEDs_Positions_GPIO_IO
+ +fpga_0_SRAM_Mem_A_pinO9:29fpga_0_SRAM_Mem_A
+ +fpga_0_SRAM_Mem_BEN_pinO0:3fpga_0_SRAM_Mem_BEN
+ +fpga_0_SRAM_Mem_WEN_pinO1fpga_0_SRAM_Mem_WEN
+ +fpga_0_SRAM_Mem_DQ_pinIO0:31fpga_0_SRAM_Mem_DQ
+ +fpga_0_SRAM_Mem_OEN_pinO0:0fpga_0_SRAM_Mem_OEN
+ +fpga_0_SRAM_Mem_CEN_pinO0:0fpga_0_SRAM_Mem_CEN
+ +fpga_0_SRAM_Mem_ADV_LDN_pinO1fpga_0_SRAM_Mem_ADV_LDN
+ +fpga_0_SRAM_CLOCKO1sys_clk_s
+ +sys_clk_pinI1dcm_clk_s CLK 
+ +sys_rst_pinI1sys_rst_s RESET 
+
+ + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg new file mode 100644 index 000000000..4af3f7fa1 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg @@ -0,0 +1,1427 @@ + + + + + + + + + x + + + + + + x + + + + + y + x + + + + + KEY + + SYMBOLS + + bus interface + + shared bus + Bus connections + + master or initiator + + slave or target + + master slave + + monitor + External Ports + + input + + output + + inout + Interrupts + + interrupt + controller + + interrupted + processor + + interrupt + source + x = controller ID + y = priority + + COLORS + Bus Standards + + DCR + + FCB + + FSL + + LMB + + OPB + + PLB + + SOCM + + XIL (prefix) P2P + + GEN. P2P, USER, etc + + + + + SPECS + + EDK VERSION + 10.1 + + ARCH + virtex4 + + PART + xc4vfx12ff668-10 + + GENERATED + Sun Mar 30 21:27:05 2008 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + plb + + + + + + + + + + + A + xps_gpio + LEDs_4Bit + + + SPLB + + + + + + B + xps_gpio + LEDs_Positions + + + SPLB + + + + + + C + xps_uartlite + RS232_Uart + + + SPLB + + + 0 + 0 + + + + + + D + xps_mch_emc + SRAM + + + SPLB + + + + + xps_intc + xps_intc_0 + + + SPLB + + + 0 + + + + + + + + + + + + + + + + + + + util_bus_split + SRAM_util_bus_split_1 + + E + + + + + clock_generator + clock_generator_0 + + F + + + + + + + + + + jtagppc_cntlr + jtagppc_0 + + + JTAG + + + + + proc_sys_reset + proc_sys_reset_0 + + G + + + RESE + + + + + ppc405_virtex4 + ppc405_0 + + + JTAG + + + IPLB0 + + + DPLB0 + + + RESE + + + + 0 + + + + + + + SLAVES OF plb + + PROCESSOR + + + + jtagppc_0_0 + + + + + + + + + + + + + + + + + + ppc_reset_bus + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IP + + + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf b/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf new file mode 100644 index 000000000..ed2e6bbe7 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf @@ -0,0 +1,339 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AE14; +Net sys_clk_pin IOSTANDARD = LVCMOS33; +Net sys_rst_pin LOC=D6; +Net sys_rst_pin PULLUP; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; +NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; +TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; +Net fpga_0_SRAM_CLOCK LOC=AF7; +Net fpga_0_SRAM_CLOCK SLEW = FAST; +Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_CLOCK DRIVE = 16; + +## IO Devices constraints + +#### Module RS232_Uart constraints + +Net fpga_0_RS232_Uart_RX_pin LOC=W2; +Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_TX_pin LOC=W1; +Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; + +#### Module LEDs_4Bit constraints + +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; + +#### Module LEDs_Positions constraints + +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; + +#### Module SRAM constraints + +Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; +Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; +Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; +Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; +Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; +Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; +Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; +Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; +Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; +Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; +Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; +Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; +Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; +Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; +Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; +Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; +Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; +Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; +Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; +Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; +Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; +Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; +Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; +Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; +Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; +Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; +Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; +Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; +Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; +Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; +Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; +Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; +Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; +Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; +Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; +Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; +Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; +Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; +Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; +Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; +Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; +Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; +Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; +Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; +Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; +Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; +Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; +Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; +Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; +Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; +Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; +Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; +Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; +Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; +Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; +Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; +Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; +Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; +Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; +Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; +Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; +Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; +Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; +Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut new file mode 100644 index 000000000..976536332 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut @@ -0,0 +1,20 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +#-m +-g Persist:No diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd new file mode 100644 index 000000000..15728dcff --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt new file mode 100644 index 000000000..6cc2599ab --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt @@ -0,0 +1,82 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt new file mode 100644 index 000000000..65076f3a8 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt @@ -0,0 +1 @@ +connect ppc hw -debugdevice cpunr 1 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt new file mode 100644 index 000000000..185473585 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/platgen.opt @@ -0,0 +1,5 @@ +-p +xc4vfx12ff668-10 +-lang +vhdl +system.mhs diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb b/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb new file mode 100644 index 000000000..2901d857e --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system.bsb @@ -0,0 +1 @@ +„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Db`\bDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@š˜h`f@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðhDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@DˆŠ¬’†Š¾¦’´ŠD@DðÆhìÌðbdDv%„æÄ®ÒôttªàÈÂèʌ Ž‚@D ‚†–‚ŽŠD@DÌÌllpDv&„æÄ®ÒôttªàÈÂèʌ Ž‚@D¦ ŠŠˆŽ¤‚ˆŠD@DZb`Dv3„æÄ®Òôtt¦Êè¦òæèÊÚ@DààÆh`j¾ìÒäèÊðh¾àØÄìhlD@Db\``\ÂDv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D„ª¦¾Œ¤Š¢D@Db``\``````Dv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D†˜–¾Œ¤Š¢D@Db``\``````Dv-„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D ¤ž†¾Œ¤Š¢D@Db``\``````Dv(„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv1„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DààÆh`j¾`D@DààÆh`j¾ìÒäèÊðhDv/„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†‚†ŠD@DbDv3„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†¾ª¦Š¾Œ ªD@D`Dv:„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@DˆŠ„ªŽ¾’ŒD@DŒ Ž‚@”¨‚ŽDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dˆž†š@¦’´ŠD@DœžœŠDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D’ž†š@¦’´ŠD@DœžœŠDv2„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dž†š¾žœ˜²D@D`Dv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@Dðàæ¾êÂäèØÒèÊDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv7„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾žˆˆ¾ ‚¤’¨²D@D`Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ª¦Š¾ ‚¤’¨²D@D`Dv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D’ž¨² ŠD@D°’˜¾ª‚¤¨¾¬bDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv-„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèD@Dðàæ¾ÎàÒÞDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@Dðàæ¾ÎàÒÞDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv+„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦¤‚šD@Dðàæ¾ÚÆоÊÚÆDv5„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦¤‚šD@D’ž¨² ŠD@D°’˜¾Šš†¾¬bDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†‚†Š¾†‚œˆ’ˆ‚¨Š¦D@D¦¤‚švDv8„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾ˆ†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@Dˆ†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv/„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@DŒ‚˜¦ŠDv1„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠDv)„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾¦®‚  ¦D@DDv7„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv0„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾„žž¨šŠšD@D¦¤‚šDv.„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆ’œD@DœÞÜÊDv/„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆžª¨D@DœÞÜÊDv@„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾’œ¦D@D¦¤‚šDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvA„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾’œ¦D@D¦¤‚šDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤Dv \ No newline at end of file diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system.make b/Demo/PPC405_Xilinx_Virtex4_GCC/system.make new file mode 100644 index 000000000..8aa93f00c --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system.make @@ -0,0 +1,269 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs +# The software specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss + +include system_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: vpclean + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " " + @echo " libs : Configures the sw libraries for this system" + @echo " program : Compiles the program sources for all the processor instances" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization" + @echo " structural_model : Generates structural simulation HDL models with BRAM initialization" + @echo " timing : Generates timing simulation HDL models with BRAM initialization" + @echo " vp : Generates virtual platform model" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " libsclean: Deletes sw libraries" + @echo " programclean: Deletes compiled ELF files" + @echo " swclean : Deletes sw libraries and ELF files" + @echo " simclean : Deletes simulation dir" + @echo " vpclean : Deletes virtualplatform dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + @echo " make : (Default)" + @echo " Creates a Microprocessor system using default initializations" + @echo " specified for each processor in MSS file" + + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +netlist: $(POSTSYN_NETLIST) + +libs: $(LIBRARIES) + +program: $(ALL_USER_ELF_FILES) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral; \ + $(SIM_CMD) & + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +vp: $(VPEXEC) + +clean: hwclean libsclean programclean simclean vpclean + rm -f _impact.cmd + rm -f *.log + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + +swclean: libsclean programclean + @echo "" + +libsclean: $(LIBSCLEAN_TARGETS) + rm -f libgen.log + +programclean: $(PROGRAMCLEAN_TARGETS) + +vpclean: + rm -rf virtualplatform + rm -f vpgen.log + +################################################################# +# SOFTWARE PLATFORM FLOW +################################################################# + + +$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt + @echo "*********************************************" + @echo "Creating software libraries..." + @echo "*********************************************" + libgen $(LIBGEN_OPTIONS) $(MSSFILE) + + +ppc405_0_libsclean: + rm -rf ppc405_0/ + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDemo_program: $(RTOSDEMO_OUTPUT) + +$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ + $(LIBRARIES) __xps/rtosdemo_compiler.opt + @mkdir -p $(RTOSDEMO_OUTPUT_DIR) + $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ + $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ + $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) + $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) + @echo "" + +RTOSDemo_programclean: + rm -f $(RTOSDEMO_OUTPUT) + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + + +$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) + @mkdir -p $(BOOTLOOP_DIR) + cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + bash -c "cd synthesis; ./synthesis.sh" + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS) + xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed + xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt + # @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) + @echo "*********************************************" + @echo "Creating system ace file" + @echo "*********************************************" + xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +################################################################# +# VIRTUAL PLATFORM FLOW +################################################################# + + +$(VPEXEC): $(MHSFILE) __xps/vpgen.opt + @echo "****************************************************" + @echo "Creating virtual platform for hardware specification.." + @echo "****************************************************" + vpgen $(VPGEN_OPTIONS) $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs b/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs new file mode 100644 index 000000000..b20af6f26 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system.mhs @@ -0,0 +1,180 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15 +# Sun Mar 30 11:39:33 2008 +# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 +# Family: virtex4 +# Device: xc4vfx12 +# Package: ff668 +# Speed Grade: -10 +# Processor: ppc405_0 +# Processor clock frequency: 100.00 MHz +# Bus clock frequency: 100.00 MHz +# Total Off Chip Memory : 1 MB +# - SRAM = 1 MB +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I + PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O + PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4] + PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29] + PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3] + PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O + PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31] + PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0] + PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0] + PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O + PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O + PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 + PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST + + +BEGIN ppc405_virtex4 + PARAMETER INSTANCE = ppc405_0 + PARAMETER HW_VER = 2.01.a + PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 + PARAMETER C_IDCR_BASEADDR = 0b0100000000 + PARAMETER C_IDCR_HIGHADDR = 0b0111111111 + BUS_INTERFACE JTAGPPC = jtagppc_0_0 + BUS_INTERFACE IPLB0 = plb + BUS_INTERFACE DPLB0 = plb + BUS_INTERFACE RESETPPC = ppc_reset_bus + PORT CPMC405CLOCK = sys_clk_s + PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ +END + +BEGIN jtagppc_cntlr + PARAMETER INSTANCE = jtagppc_0 + PARAMETER HW_VER = 2.01.a + BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 +END + +BEGIN plb_v46 + PARAMETER INSTANCE = plb + PARAMETER C_DCR_INTFCE = 0 + PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 + PARAMETER HW_VER = 1.02.a + PORT PLB_Clk = sys_clk_s + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_uartlite + PARAMETER INSTANCE = RS232_Uart + PARAMETER HW_VER = 1.00.a + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 + PARAMETER C_BASEADDR = 0x84000000 + PARAMETER C_HIGHADDR = 0x8400ffff + BUS_INTERFACE SPLB = plb + PORT RX = fpga_0_RS232_Uart_RX + PORT TX = fpga_0_RS232_Uart_TX + PORT Interrupt = RS232_Uart_Interrupt +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_4Bit + PARAMETER HW_VER = 1.00.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x81420000 + PARAMETER C_HIGHADDR = 0x8142ffff + BUS_INTERFACE SPLB = plb + PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER HW_VER = 1.00.a + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x81400000 + PARAMETER C_HIGHADDR = 0x8140ffff + BUS_INTERFACE SPLB = plb + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO +END + +BEGIN xps_mch_emc + PARAMETER INSTANCE = SRAM + PARAMETER HW_VER = 1.00.a + PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000 + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_MAX_MEM_WIDTH = 32 + PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 + PARAMETER C_MEM0_WIDTH = 32 + PARAMETER C_SYNCH_MEM_0 = 1 + PARAMETER C_TCEDV_PS_MEM_0 = 0 + PARAMETER C_TWC_PS_MEM_0 = 0 + PARAMETER C_TAVDV_PS_MEM_0 = 0 + PARAMETER C_TWP_PS_MEM_0 = 0 + PARAMETER C_THZCE_PS_MEM_0 = 0 + PARAMETER C_TLZWE_PS_MEM_0 = 0 + PARAMETER C_MEM0_BASEADDR = 0xfff00000 + PARAMETER C_MEM0_HIGHADDR = 0xffffffff + BUS_INTERFACE SPLB = plb + PORT Mem_A = fpga_0_SRAM_Mem_A_split + PORT Mem_BEN = fpga_0_SRAM_Mem_BEN + PORT Mem_WEN = fpga_0_SRAM_Mem_WEN + PORT Mem_DQ = fpga_0_SRAM_Mem_DQ + PORT Mem_OEN = fpga_0_SRAM_Mem_OEN + PORT Mem_CEN = fpga_0_SRAM_Mem_CEN + PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN +END + +BEGIN util_bus_split + PARAMETER INSTANCE = SRAM_util_bus_split_1 + PARAMETER HW_VER = 1.00.a + PARAMETER C_SIZE_IN = 32 + PARAMETER C_LEFT_POS = 9 + PARAMETER C_SPLIT = 30 + PORT Sig = fpga_0_SRAM_Mem_A_split + PORT Out1 = fpga_0_SRAM_Mem_A +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PARAMETER C_CLKIN_FREQ = 100000000 + PARAMETER C_CLKOUT0_FREQ = 100000000 + PARAMETER C_CLKOUT0_BUF = TRUE + PARAMETER C_CLKOUT0_PHASE = 0 + PARAMETER C_CLKOUT0_GROUP = NONE + PORT CLKOUT0 = sys_clk_s + PORT CLKIN = dcm_clk_s + PORT LOCKED = Dcm_all_locked + PORT RST = net_gnd +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + BUS_INTERFACE RESETPPC0 = ppc_reset_bus + PORT Slowest_sync_clk = sys_clk_s + PORT Dcm_locked = Dcm_all_locked + PORT Ext_Reset_In = sys_rst_s + PORT Bus_Struct_Reset = sys_bus_reset + PORT Peripheral_Reset = sys_periph_reset +END + +BEGIN xps_intc + PARAMETER INSTANCE = xps_intc_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x81800000 + PARAMETER C_HIGHADDR = 0x8180ffff + BUS_INTERFACE SPLB = plb + PORT Irq = EICC405EXTINPUTIRQ + PORT Intr = RS232_Uart_Interrupt +END + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss b/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss new file mode 100644 index 000000000..a928cfaad --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system.mss @@ -0,0 +1,76 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 2.00.a + PARAMETER PROC_INSTANCE = ppc405_0 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_ppc405 + PARAMETER DRIVER_VER = 1.10.a + PARAMETER HW_INSTANCE = ppc405_0 + PARAMETER COMPILER = powerpc-eabi-gcc + PARAMETER ARCHIVER = powerpc-eabi-ar + PARAMETER CORE_CLOCK_FREQ_HZ = 100000000 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = jtagppc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.12.a + PARAMETER HW_INSTANCE = RS232_Uart +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.11.a + PARAMETER HW_INSTANCE = LEDs_4Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.11.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emc + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = SRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = SRAM_util_bus_split_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = clock_generator_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = proc_sys_reset_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.10.c + PARAMETER HW_INSTANCE = xps_intc_0 +END + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp b/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp new file mode 100644 index 000000000..0c98e8f1e --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system.xmp @@ -0,0 +1,73 @@ +#Please do not modify this file by hand +XmpVersion: 10.1 +VerMgmt: 10.1 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +NPL File: projnav/system.ise +Architecture: virtex4 +Device: xc4vfx12 +Package: ff668 +SpeedGrade: -10 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +TopInst: system_i +GenSimTB: 0 +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +Simulator: mti +SimModel: BEHAVIORAL +MixLangSim: 1 +UcfFile: data/system.ucf +FpgaImpMode: 0 +EnableParTimingError: 1 +EnableResetOptimization: 0 +ShowLicenseDialog: 1 +ICacheAddr: SRAM, +DCacheAddr: SRAM, +Processor: ppc405_0 +BootLoop: 1 +XmdStub: 0 +SwProj: RTOSDemo +Processor: ppc405_0 +Executable: RTOSDemo/executable.elf +Source: RTOSDemo/../../Common/Minimal/BlockQ.c +Source: RTOSDemo/../../Common/Minimal/blocktim.c +Source: RTOSDemo/../../Common/Minimal/comtest.c +Source: RTOSDemo/../../Common/Minimal/countsem.c +Source: RTOSDemo/../../Common/Minimal/death.c +Source: RTOSDemo/../../Common/Minimal/dynamic.c +Source: RTOSDemo/../../Common/Minimal/flash.c +Source: RTOSDemo/../../Common/Minimal/flop.c +Source: RTOSDemo/../../Common/Minimal/GenQTest.c +Source: RTOSDemo/../../Common/Minimal/integer.c +Source: RTOSDemo/../../Common/Minimal/QPeek.c +Source: RTOSDemo/../../Common/Minimal/recmutex.c +Source: RTOSDemo/../../Common/Minimal/semtest.c +Source: RTOSDemo/../../../Source/tasks.c +Source: RTOSDemo/../../../Source/list.c +Source: RTOSDemo/../../../Source/queue.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c +Source: RTOSDemo/main.c +Source: RTOSDemo/serial/serial.c +Source: RTOSDemo/partest/partest.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S +Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c +Header: RTOSDemo/FreeRTOSConfig.h +DefaultInit: EXECUTABLE +InitBram: 0 +Active: 1 +CompilerOptLevel: 0 +GlobPtrOpt: 0 +DebugSym: 1 +ProfileFlag: 0 +ProgStart: +StackSize: +HeapSize: +LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld +ProgCCFlags: -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +CompileInXps: 1 +NonXpsApp: 0 diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make b/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make new file mode 100644 index 000000000..44228feff --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/system_incl.make @@ -0,0 +1,141 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/10.1/EDK +NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/10.1/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +MSSFILE = system.mss + +FPGA_ARCH = virtex4 + +DEVICE = xc4vfx12ff668-10 + +LANGUAGE = vhdl + +SEARCHPATHOPT = + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) + +LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) + +VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) + +MANAGE_FASTRT_OPTIONS = -reduce_fanout no + +OBSERVE_PAR_OPTIONS = -error yes + +RTOSDEMO_OUTPUT_DIR = RTOSDemo +RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf + +BRAMINIT_ELF_FILES = +BRAMINIT_ELF_FILE_ARGS = + +ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) + +SIM_CMD = vsim + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti -X ./ -E ./ + + +LIBRARIES = \ + ppc405_0/lib/libxil.a +VPEXEC = virtualplatform/vpexec.exe + +LIBSCLEAN_TARGETS = ppc405_0_libsclean + +PROGRAMCLEAN_TARGETS = RTOSDemo_programclean + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \ +implementation/jtagppc_0_wrapper.ngc \ +implementation/plb_wrapper.ngc \ +implementation/rs232_uart_wrapper.ngc \ +implementation/leds_4bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/sram_wrapper.ngc \ +implementation/sram_util_bus_split_1_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/xps_intc_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = etc/bitgen.ut + +XFLOW_OPT_FILE = etc/fast_runtime.opt +XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) + +XPLORER_DEPENDENCY = __xps/xplorer.opt +XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 + +FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY) + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c + +RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h + +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= +RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ + $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \ + $(RTOSDEMO_CC_INFERRED_FLAGS) \ + $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG) diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/xc95144xl.bsd b/Demo/PPC405_Xilinx_Virtex4_GCC/xc95144xl.bsd new file mode 100644 index 000000000..6ad508401 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/xc95144xl.bsd @@ -0,0 +1,826 @@ +-- +-- BSDL File created/edited by XILINX bsdl.pl script +-- +--Package: DIE_BOND +--RCS:$Header: /devl/xcs/repo/env/Jobs/iMPACT/data/xc9500xl/xc95144xl.bsd,v 1.2 2001/01/18 04:42:23 sanjays Exp $ +--BSDE:$Revision: 1.2 $ +--BSDE: Xilinx xc95144xl macrocell FastFlash ISP CPLD +-- +entity xc95144xl is + + +generic (PHYSICAL_PIN_MAP : string := "DIE_BOND" ); + +port ( + PB00_00: inout bit; + PB00_01: inout bit; + PB00_02: inout bit; + PB00_03: inout bit; + PB00_04: inout bit; + PB00_05: inout bit; + PB00_06: inout bit; + PB00_07: inout bit; + PB00_08: inout bit; + PB00_09: inout bit; + PB00_10: inout bit; + PB00_11: inout bit; + PB00_12: inout bit; + PB00_13: inout bit; + PB00_14: inout bit; + PB00_15: inout bit; + PB00_16: inout bit; + PB01_00: inout bit; + PB01_01: inout bit; + PB01_02: inout bit; + PB01_03: inout bit; + PB01_04: inout bit; + PB01_05: inout bit; + PB01_06: inout bit; + PB01_07: inout bit; + PB01_08: inout bit; + PB01_09: inout bit; + PB01_10: inout bit; + PB01_11: inout bit; + PB01_12: inout bit; + PB01_13: inout bit; + PB01_14: inout bit; + PB01_15: inout bit; + PB01_16: inout bit; + PB02_00: inout bit; + PB02_01: inout bit; + PB02_02: inout bit; + PB02_03: inout bit; + PB02_04: inout bit; + PB02_05: inout bit; + PB02_06: inout bit; + PB02_07: inout bit; + PB02_08: inout bit; + PB02_09: inout bit; + PB02_10: inout bit; + PB02_11: inout bit; + PB02_12: inout bit; + PB02_13: inout bit; + PB02_14: inout bit; + PB02_15: inout bit; + PB02_16: inout bit; + PB03_00: inout bit; + PB03_01: inout bit; + PB03_02: inout bit; + PB03_03: inout bit; + PB03_04: inout bit; + PB03_05: inout bit; + PB03_06: inout bit; + PB03_07: inout bit; + PB03_08: inout bit; + PB03_09: inout bit; + PB03_10: inout bit; + PB03_11: inout bit; + PB03_12: inout bit; + PB03_13: inout bit; + PB03_14: inout bit; + PB03_15: inout bit; + PB03_16: inout bit; + PB04_00: inout bit; + PB04_01: inout bit; + PB04_02: inout bit; + PB04_03: inout bit; + PB04_04: inout bit; + PB04_05: inout bit; + PB04_06: inout bit; + PB04_07: inout bit; + PB04_08: inout bit; + PB04_09: inout bit; + PB04_10: inout bit; + PB04_11: inout bit; + PB04_12: inout bit; + PB04_13: inout bit; + PB04_14: inout bit; + PB04_15: inout bit; + PB04_16: inout bit; + PB05_01: inout bit; + PB05_02: inout bit; + PB05_03: inout bit; + PB05_04: inout bit; + PB05_05: inout bit; + PB05_06: inout bit; + PB05_07: inout bit; + PB05_08: inout bit; + PB05_09: inout bit; + PB05_10: inout bit; + PB05_11: inout bit; + PB05_12: inout bit; + PB05_13: inout bit; + PB05_14: inout bit; + PB05_15: inout bit; + PB05_16: inout bit; + PB06_01: inout bit; + PB06_02: inout bit; + PB06_03: inout bit; + PB06_04: inout bit; + PB06_05: inout bit; + PB06_06: inout bit; + PB06_07: inout bit; + PB06_08: inout bit; + PB06_09: inout bit; + PB06_10: inout bit; + PB06_11: inout bit; + PB06_12: inout bit; + PB06_13: inout bit; + PB06_14: inout bit; + PB06_15: inout bit; + PB06_16: inout bit; + PB07_01: inout bit; + PB07_02: inout bit; + PB07_03: inout bit; + PB07_04: inout bit; + PB07_05: inout bit; + PB07_06: inout bit; + PB07_07: inout bit; + PB07_08: inout bit; + PB07_09: inout bit; + PB07_10: inout bit; + PB07_11: inout bit; + PB07_12: inout bit; + PB07_13: inout bit; + PB07_14: inout bit; + PB07_15: inout bit; + PB07_16: inout bit; + TCK: in bit; + TDI: in bit; + TDO: out bit; + TMS: in bit; + Vccint_1: linkage bit; + Vccint_2: linkage bit; + Vccint_3: linkage bit; + VccInt_Vpp: linkage bit; + Vccio_1: linkage bit; + Vccio_2: linkage bit; + Vccio_3: linkage bit; + Vccio_4: linkage bit; + Vccio_5: linkage bit; + Vccio_6: linkage bit; + Vssint_1: linkage bit; + Vssint_2: linkage bit; + Vssint_3: linkage bit; + Vssint_4: linkage bit; + Vssint_Vnn: linkage bit; + Vssio_1: linkage bit; + Vssio_2: linkage bit; + Vssio_3: linkage bit; + Vssio_4: linkage bit; + Vssio_5: linkage bit; + Vssio_6: linkage bit; + Vssio_7: linkage bit; + Vssio_8: linkage bit; + Vssio_9: linkage bit ); + +use STD_1149_1_1994.all; + +attribute COMPONENT_CONFORMANCE of xc95144xl : entity is "STD_1149_1_1993"; + +attribute PIN_MAP of xc95144xl : entity is PHYSICAL_PIN_MAP; + +constant DIE_BOND: PIN_MAP_STRING:= + "PB00_00:PAD25," & + "PB00_01:PAD18," & + "PB00_02:PAD19," & + "PB00_03:PAD27," & + "PB00_04:PAD21," & + "PB00_05:PAD22," & + "PB00_06:PAD32," & + "PB00_07:PAD23," & + "PB00_08:PAD24," & + "PB00_09:PAD34," & + "PB00_10:PAD26," & + "PB00_11:PAD28," & + "PB00_12:PAD38," & + "PB00_13:PAD29," & + "PB00_14:PAD30," & + "PB00_15:PAD39," & + "PB00_16:PAD33," & + "PB01_00:PAD159," & + "PB01_01:PAD160," & + "PB01_02:PAD3," & + "PB01_03:PAD5," & + "PB01_04:PAD2," & + "PB01_05:PAD4," & + "PB01_06:PAD7," & + "PB01_07:PAD6," & + "PB01_08:PAD8," & + "PB01_09:PAD9," & + "PB01_10:PAD11," & + "PB01_11:PAD12," & + "PB01_12:PAD14," & + "PB01_13:PAD13," & + "PB01_14:PAD15," & + "PB01_15:PAD16," & + "PB01_16:PAD17," & + "PB02_00:PAD43," & + "PB02_01:PAD35," & + "PB02_02:PAD45," & + "PB02_03:PAD48," & + "PB02_04:PAD36," & + "PB02_05:PAD37," & + "PB02_06:PAD50," & + "PB02_07:PAD42," & + "PB02_08:PAD44," & + "PB02_09:PAD52," & + "PB02_10:PAD47," & + "PB02_11:PAD49," & + "PB02_12:PAD53," & + "PB02_13:PAD54," & + "PB02_14:PAD56," & + "PB02_15:PAD55," & + "PB02_16:PAD57," & + "PB03_00:PAD133," & + "PB03_01:PAD141," & + "PB03_02:PAD148," & + "PB03_03:PAD150," & + "PB03_04:PAD143," & + "PB03_05:PAD144," & + "PB03_06:PAD151," & + "PB03_07:PAD145," & + "PB03_08:PAD146," & + "PB03_09:PAD152," & + "PB03_10:PAD147," & + "PB03_11:PAD149," & + "PB03_12:PAD154," & + "PB03_13:PAD153," & + "PB03_14:PAD155," & + "PB03_15:PAD156," & + "PB03_16:PAD157," & + "PB04_00:PAD65," & + "PB04_01:PAD58," & + "PB04_02:PAD66," & + "PB04_03:PAD67," & + "PB04_04:PAD59," & + "PB04_05:PAD60," & + "PB04_06:PAD74," & + "PB04_07:PAD62," & + "PB04_08:PAD63," & + "PB04_09:PAD76," & + "PB04_10:PAD64," & + "PB04_11:PAD68," & + "PB04_12:PAD78," & + "PB04_13:PAD69," & + "PB04_14:PAD72," & + "PB04_15:PAD83," & + "PB04_16:PAD77," & + "PB05_01:PAD118," & + "PB05_02:PAD120," & + "PB05_03:PAD124," & + "PB05_04:PAD123," & + "PB05_05:PAD125," & + "PB05_06:PAD126," & + "PB05_07:PAD127," & + "PB05_08:PAD130," & + "PB05_09:PAD129," & + "PB05_10:PAD134," & + "PB05_11:PAD135," & + "PB05_12:PAD131," & + "PB05_13:PAD136," & + "PB05_14:PAD139," & + "PB05_15:PAD132," & + "PB05_16:PAD140," & + "PB06_01:PAD79," & + "PB06_02:PAD84," & + "PB06_03:PAD85," & + "PB06_04:PAD82," & + "PB06_05:PAD86," & + "PB06_06:PAD87," & + "PB06_07:PAD88," & + "PB06_08:PAD90," & + "PB06_09:PAD89," & + "PB06_10:PAD92," & + "PB06_11:PAD95," & + "PB06_12:PAD91," & + "PB06_13:PAD96," & + "PB06_14:PAD97," & + "PB06_15:PAD93," & + "PB06_16:PAD98," & + "PB07_01:PAD102," & + "PB07_02:PAD106," & + "PB07_03:PAD108," & + "PB07_04:PAD103," & + "PB07_05:PAD104," & + "PB07_06:PAD110," & + "PB07_07:PAD105," & + "PB07_08:PAD107," & + "PB07_09:PAD113," & + "PB07_10:PAD109," & + "PB07_11:PAD112," & + "PB07_12:PAD115," & + "PB07_13:PAD114," & + "PB07_14:PAD116," & + "PB07_15:PAD119," & + "PB07_16:PAD117," & + "TCK:PAD75," & + "TDI:PAD71," & + "TDO:PAD137," & + "TMS:PAD73," & + "Vccint_1:PAD46," & + "Vccint_2:PAD94," & + "Vccint_3:PAD158," & + "VccInt_Vpp:PAD10," & + "Vccio_1:PAD1," & + "Vccio_2:PAD41," & + "Vccio_3:PAD61," & + "Vccio_4:PAD81," & + "Vccio_5:PAD122," & + "Vccio_6:PAD142," & + "Vssint_1:PAD31," & + "Vssint_2:PAD70," & + "Vssint_3:PAD100," & + "Vssint_4:PAD128," & + "Vssint_Vnn:PAD101," & + "Vssio_1:PAD20," & + "Vssio_2:PAD40," & + "Vssio_3:PAD51," & + "Vssio_4:PAD80," & + "Vssio_5:PAD99," & + "Vssio_6:PAD111," & + "Vssio_7:PAD121," & + "Vssio_8:PAD138," & + "Vssio_9:PAD161"; + +attribute TAP_SCAN_IN of TDI : signal is true; +attribute TAP_SCAN_OUT of TDO : signal is true; +attribute TAP_SCAN_MODE of TMS : signal is true; +attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH); +attribute INSTRUCTION_LENGTH of xc95144xl : entity is 8; + +attribute INSTRUCTION_OPCODE of xc95144xl : entity is + "BYPASS ( 11111111)," & + "CLAMP ( 11111010)," & + "ISPEX ( 11110000)," & + "EXTEST ( 00000000),"& + "FBLANK ( 11100101),"& + "FBULK ( 11101101),"& + "FERASE ( 11101100),"& + "FPGM ( 11101010)," & + "FPGMI ( 11101011)," & + "FVFY ( 11101110)," & + "FVFYI ( 11101111)," & + "HIGHZ ( 11111100),"& + "IDCODE ( 11111110),"& + "INTEST ( 00000010),"& + "ISPEN ( 11101000)," & + "ISPENC ( 11101001)," & + "SAMPLE ( 00000001)," & + "USERCODE ( 11111101)"; + +attribute INSTRUCTION_CAPTURE of xc95144xl: entity is "000XXX01"; + +attribute IDCODE_REGISTER of xc95144xl: entity is + "XXXX" & -- version + "1001011000001000" & -- part number + "00001001001" & -- manufacturer's id + "1"; -- required by standard + +attribute USERCODE_REGISTER of xc95144xl: entity is + "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + + +attribute REGISTER_ACCESS of xc95144xl : entity is + "BYPASS ( ISPEX, HIGHZ, CLAMP )," & + "ISCENABLE[6] ( ISPEN, ISPENC )," & + "ISDATA[66] ( FPGMI, FVFYI ),"& + "ISADDRESS[18] ( FERASE, FBULK, FBLANK ),"& + "ISCONFIGURATION[82] ( FPGM, FVFY )"; +attribute BOUNDARY_LENGTH of xc95144xl : entity is 432; + +attribute BOUNDARY_REGISTER of xc95144xl : entity is + " 431 (BC_1, PB00_00, input, X), " & + " 430 (BC_1, PB00_00, output3, X, 429, 0, Z)," & + " 429 (BC_1, *, controlr, 0)," & + " 428 (BC_1, PB00_01, input, X), " & + " 427 (BC_1, PB00_01, output3, X, 426, 0, Z)," & + " 426 (BC_1, *, controlr, 0)," & + " 425 (BC_1, PB00_02, input, X), " & + " 424 (BC_1, PB00_02, output3, X, 423, 0, Z)," & + " 423 (BC_1, *, controlr, 0)," & + " 422 (BC_1, PB00_03, input, X), " & + " 421 (BC_1, PB00_03, output3, X, 420, 0, Z)," & + " 420 (BC_1, *, controlr, 0)," & + " 419 (BC_1, PB00_04, input, X), " & + " 418 (BC_1, PB00_04, output3, X, 417, 0, Z)," & + " 417 (BC_1, *, controlr, 0)," & + " 416 (BC_1, PB00_05, input, X), " & + " 415 (BC_1, PB00_05, output3, X, 414, 0, Z)," & + " 414 (BC_1, *, controlr, 0)," & + " 413 (BC_1, PB00_06, input, X), " & + " 412 (BC_1, PB00_06, output3, X, 411, 0, Z)," & + " 411 (BC_1, *, controlr, 0)," & + " 410 (BC_1, PB00_07, input, X), " & + " 409 (BC_1, PB00_07, output3, X, 408, 0, Z)," & + " 408 (BC_1, *, controlr, 0)," & + " 407 (BC_1, PB00_08, input, X), " & + " 406 (BC_1, PB00_08, output3, X, 405, 0, Z)," & + " 405 (BC_1, *, controlr, 0)," & + " 404 (BC_1, PB00_09, input, X), " & + " 403 (BC_1, PB00_09, output3, X, 402, 0, Z)," & + " 402 (BC_1, *, controlr, 0)," & + " 401 (BC_1, PB00_10, input, X), " & + " 400 (BC_1, PB00_10, output3, X, 399, 0, Z)," & + " 399 (BC_1, *, controlr, 0)," & + " 398 (BC_1, PB00_11, input, X), " & + " 397 (BC_1, PB00_11, output3, X, 396, 0, Z)," & + " 396 (BC_1, *, controlr, 0)," & + " 395 (BC_1, PB00_12, input, X), " & + " 394 (BC_1, PB00_12, output3, X, 393, 0, Z)," & + " 393 (BC_1, *, controlr, 0)," & + " 392 (BC_1, PB00_13, input, X), " & + " 391 (BC_1, PB00_13, output3, X, 390, 0, Z)," & + " 390 (BC_1, *, controlr, 0)," & + " 389 (BC_1, PB00_14, input, X), " & + " 388 (BC_1, PB00_14, output3, X, 387, 0, Z)," & + " 387 (BC_1, *, controlr, 0)," & + " 386 (BC_1, PB00_15, input, X), " & + " 385 (BC_1, PB00_15, output3, X, 384, 0, Z)," & + " 384 (BC_1, *, controlr, 0)," & + " 383 (BC_1, PB00_16, input, X), " & + " 382 (BC_1, PB00_16, output3, X, 381, 0, Z)," & + " 381 (BC_1, *, controlr, 0)," & + " 380 (BC_1, *, internal, X)," & + " 379 (BC_1, *, internal, X)," & + " 378 (BC_1, *, internal, X)," & + " 377 (BC_1, PB01_00, input, X), " & + " 376 (BC_1, PB01_00, output3, X, 375, 0, Z)," & + " 375 (BC_1, *, controlr, 0)," & + " 374 (BC_1, PB01_01, input, X), " & + " 373 (BC_1, PB01_01, output3, X, 372, 0, Z)," & + " 372 (BC_1, *, controlr, 0)," & + " 371 (BC_1, PB01_02, input, X), " & + " 370 (BC_1, PB01_02, output3, X, 369, 0, Z)," & + " 369 (BC_1, *, controlr, 0)," & + " 368 (BC_1, PB01_03, input, X), " & + " 367 (BC_1, PB01_03, output3, X, 366, 0, Z)," & + " 366 (BC_1, *, controlr, 0)," & + " 365 (BC_1, PB01_04, input, X), " & + " 364 (BC_1, PB01_04, output3, X, 363, 0, Z)," & + " 363 (BC_1, *, controlr, 0)," & + " 362 (BC_1, PB01_05, input, X), " & + " 361 (BC_1, PB01_05, output3, X, 360, 0, Z)," & + " 360 (BC_1, *, controlr, 0)," & + " 359 (BC_1, PB01_06, input, X), " & + " 358 (BC_1, PB01_06, output3, X, 357, 0, Z)," & + " 357 (BC_1, *, controlr, 0)," & + " 356 (BC_1, PB01_07, input, X), " & + " 355 (BC_1, PB01_07, output3, X, 354, 0, Z)," & + " 354 (BC_1, *, controlr, 0)," & + " 353 (BC_1, PB01_08, input, X), " & + " 352 (BC_1, PB01_08, output3, X, 351, 0, Z)," & + " 351 (BC_1, *, controlr, 0)," & + " 350 (BC_1, PB01_09, input, X), " & + " 349 (BC_1, PB01_09, output3, X, 348, 0, Z)," & + " 348 (BC_1, *, controlr, 0)," & + " 347 (BC_1, PB01_10, input, X), " & + " 346 (BC_1, PB01_10, output3, X, 345, 0, Z)," & + " 345 (BC_1, *, controlr, 0)," & + " 344 (BC_1, PB01_11, input, X), " & + " 343 (BC_1, PB01_11, output3, X, 342, 0, Z)," & + " 342 (BC_1, *, controlr, 0)," & + " 341 (BC_1, PB01_12, input, X), " & + " 340 (BC_1, PB01_12, output3, X, 339, 0, Z)," & + " 339 (BC_1, *, controlr, 0)," & + " 338 (BC_1, PB01_13, input, X), " & + " 337 (BC_1, PB01_13, output3, X, 336, 0, Z)," & + " 336 (BC_1, *, controlr, 0)," & + " 335 (BC_1, PB01_14, input, X), " & + " 334 (BC_1, PB01_14, output3, X, 333, 0, Z)," & + " 333 (BC_1, *, controlr, 0)," & + " 332 (BC_1, PB01_15, input, X), " & + " 331 (BC_1, PB01_15, output3, X, 330, 0, Z)," & + " 330 (BC_1, *, controlr, 0)," & + " 329 (BC_1, PB01_16, input, X), " & + " 328 (BC_1, PB01_16, output3, X, 327, 0, Z)," & + " 327 (BC_1, *, controlr, 0)," & + " 326 (BC_1, *, internal, X)," & + " 325 (BC_1, *, internal, X)," & + " 324 (BC_1, *, internal, X)," & + " 323 (BC_1, PB02_00, input, X), " & + " 322 (BC_1, PB02_00, output3, X, 321, 0, Z)," & + " 321 (BC_1, *, controlr, 0)," & + " 320 (BC_1, PB02_01, input, X), " & + " 319 (BC_1, PB02_01, output3, X, 318, 0, Z)," & + " 318 (BC_1, *, controlr, 0)," & + " 317 (BC_1, PB02_02, input, X), " & + " 316 (BC_1, PB02_02, output3, X, 315, 0, Z)," & + " 315 (BC_1, *, controlr, 0)," & + " 314 (BC_1, PB02_03, input, X), " & + " 313 (BC_1, PB02_03, output3, X, 312, 0, Z)," & + " 312 (BC_1, *, controlr, 0)," & + " 311 (BC_1, PB02_04, input, X), " & + " 310 (BC_1, PB02_04, output3, X, 309, 0, Z)," & + " 309 (BC_1, *, controlr, 0)," & + " 308 (BC_1, PB02_05, input, X), " & + " 307 (BC_1, PB02_05, output3, X, 306, 0, Z)," & + " 306 (BC_1, *, controlr, 0)," & + " 305 (BC_1, PB02_06, input, X), " & + " 304 (BC_1, PB02_06, output3, X, 303, 0, Z)," & + " 303 (BC_1, *, controlr, 0)," & + " 302 (BC_1, PB02_07, input, X), " & + " 301 (BC_1, PB02_07, output3, X, 300, 0, Z)," & + " 300 (BC_1, *, controlr, 0)," & + " 299 (BC_1, PB02_08, input, X), " & + " 298 (BC_1, PB02_08, output3, X, 297, 0, Z)," & + " 297 (BC_1, *, controlr, 0)," & + " 296 (BC_1, PB02_09, input, X), " & + " 295 (BC_1, PB02_09, output3, X, 294, 0, Z)," & + " 294 (BC_1, *, controlr, 0)," & + " 293 (BC_1, PB02_10, input, X), " & + " 292 (BC_1, PB02_10, output3, X, 291, 0, Z)," & + " 291 (BC_1, *, controlr, 0)," & + " 290 (BC_1, PB02_11, input, X), " & + " 289 (BC_1, PB02_11, output3, X, 288, 0, Z)," & + " 288 (BC_1, *, controlr, 0)," & + " 287 (BC_1, PB02_12, input, X), " & + " 286 (BC_1, PB02_12, output3, X, 285, 0, Z)," & + " 285 (BC_1, *, controlr, 0)," & + " 284 (BC_1, PB02_13, input, X), " & + " 283 (BC_1, PB02_13, output3, X, 282, 0, Z)," & + " 282 (BC_1, *, controlr, 0)," & + " 281 (BC_1, PB02_14, input, X), " & + " 280 (BC_1, PB02_14, output3, X, 279, 0, Z)," & + " 279 (BC_1, *, controlr, 0)," & + " 278 (BC_1, PB02_15, input, X), " & + " 277 (BC_1, PB02_15, output3, X, 276, 0, Z)," & + " 276 (BC_1, *, controlr, 0)," & + " 275 (BC_1, PB02_16, input, X), " & + " 274 (BC_1, PB02_16, output3, X, 273, 0, Z)," & + " 273 (BC_1, *, controlr, 0)," & + " 272 (BC_1, *, internal, X)," & + " 271 (BC_1, *, internal, X)," & + " 270 (BC_1, *, internal, X)," & + " 269 (BC_1, PB03_00, input, X), " & + " 268 (BC_1, PB03_00, output3, X, 267, 0, Z)," & + " 267 (BC_1, *, controlr, 0)," & + " 266 (BC_1, PB03_01, input, X), " & + " 265 (BC_1, PB03_01, output3, X, 264, 0, Z)," & + " 264 (BC_1, *, controlr, 0)," & + " 263 (BC_1, PB03_02, input, X), " & + " 262 (BC_1, PB03_02, output3, X, 261, 0, Z)," & + " 261 (BC_1, *, controlr, 0)," & + " 260 (BC_1, PB03_03, input, X), " & + " 259 (BC_1, PB03_03, output3, X, 258, 0, Z)," & + " 258 (BC_1, *, controlr, 0)," & + " 257 (BC_1, PB03_04, input, X), " & + " 256 (BC_1, PB03_04, output3, X, 255, 0, Z)," & + " 255 (BC_1, *, controlr, 0)," & + " 254 (BC_1, PB03_05, input, X), " & + " 253 (BC_1, PB03_05, output3, X, 252, 0, Z)," & + " 252 (BC_1, *, controlr, 0)," & + " 251 (BC_1, PB03_06, input, X), " & + " 250 (BC_1, PB03_06, output3, X, 249, 0, Z)," & + " 249 (BC_1, *, controlr, 0)," & + " 248 (BC_1, PB03_07, input, X), " & + " 247 (BC_1, PB03_07, output3, X, 246, 0, Z)," & + " 246 (BC_1, *, controlr, 0)," & + " 245 (BC_1, PB03_08, input, X), " & + " 244 (BC_1, PB03_08, output3, X, 243, 0, Z)," & + " 243 (BC_1, *, controlr, 0)," & + " 242 (BC_1, PB03_09, input, X), " & + " 241 (BC_1, PB03_09, output3, X, 240, 0, Z)," & + " 240 (BC_1, *, controlr, 0)," & + " 239 (BC_1, PB03_10, input, X), " & + " 238 (BC_1, PB03_10, output3, X, 237, 0, Z)," & + " 237 (BC_1, *, controlr, 0)," & + " 236 (BC_1, PB03_11, input, X), " & + " 235 (BC_1, PB03_11, output3, X, 234, 0, Z)," & + " 234 (BC_1, *, controlr, 0)," & + " 233 (BC_1, PB03_12, input, X), " & + " 232 (BC_1, PB03_12, output3, X, 231, 0, Z)," & + " 231 (BC_1, *, controlr, 0)," & + " 230 (BC_1, PB03_13, input, X), " & + " 229 (BC_1, PB03_13, output3, X, 228, 0, Z)," & + " 228 (BC_1, *, controlr, 0)," & + " 227 (BC_1, PB03_14, input, X), " & + " 226 (BC_1, PB03_14, output3, X, 225, 0, Z)," & + " 225 (BC_1, *, controlr, 0)," & + " 224 (BC_1, PB03_15, input, X), " & + " 223 (BC_1, PB03_15, output3, X, 222, 0, Z)," & + " 222 (BC_1, *, controlr, 0)," & + " 221 (BC_1, PB03_16, input, X), " & + " 220 (BC_1, PB03_16, output3, X, 219, 0, Z)," & + " 219 (BC_1, *, controlr, 0)," & + " 218 (BC_1, *, internal, X)," & + " 217 (BC_1, *, internal, X)," & + " 216 (BC_1, *, internal, X)," & + " 215 (BC_1, PB04_00, input, X), " & + " 214 (BC_1, PB04_00, output3, X, 213, 0, Z)," & + " 213 (BC_1, *, controlr, 0)," & + " 212 (BC_1, PB04_01, input, X), " & + " 211 (BC_1, PB04_01, output3, X, 210, 0, Z)," & + " 210 (BC_1, *, controlr, 0)," & + " 209 (BC_1, PB04_02, input, X), " & + " 208 (BC_1, PB04_02, output3, X, 207, 0, Z)," & + " 207 (BC_1, *, controlr, 0)," & + " 206 (BC_1, PB04_03, input, X), " & + " 205 (BC_1, PB04_03, output3, X, 204, 0, Z)," & + " 204 (BC_1, *, controlr, 0)," & + " 203 (BC_1, PB04_04, input, X), " & + " 202 (BC_1, PB04_04, output3, X, 201, 0, Z)," & + " 201 (BC_1, *, controlr, 0)," & + " 200 (BC_1, PB04_05, input, X), " & + " 199 (BC_1, PB04_05, output3, X, 198, 0, Z)," & + " 198 (BC_1, *, controlr, 0)," & + " 197 (BC_1, PB04_06, input, X), " & + " 196 (BC_1, PB04_06, output3, X, 195, 0, Z)," & + " 195 (BC_1, *, controlr, 0)," & + " 194 (BC_1, PB04_07, input, X), " & + " 193 (BC_1, PB04_07, output3, X, 192, 0, Z)," & + " 192 (BC_1, *, controlr, 0)," & + " 191 (BC_1, PB04_08, input, X), " & + " 190 (BC_1, PB04_08, output3, X, 189, 0, Z)," & + " 189 (BC_1, *, controlr, 0)," & + " 188 (BC_1, PB04_09, input, X), " & + " 187 (BC_1, PB04_09, output3, X, 186, 0, Z)," & + " 186 (BC_1, *, controlr, 0)," & + " 185 (BC_1, PB04_10, input, X), " & + " 184 (BC_1, PB04_10, output3, X, 183, 0, Z)," & + " 183 (BC_1, *, controlr, 0)," & + " 182 (BC_1, PB04_11, input, X), " & + " 181 (BC_1, PB04_11, output3, X, 180, 0, Z)," & + " 180 (BC_1, *, controlr, 0)," & + " 179 (BC_1, PB04_12, input, X), " & + " 178 (BC_1, PB04_12, output3, X, 177, 0, Z)," & + " 177 (BC_1, *, controlr, 0)," & + " 176 (BC_1, PB04_13, input, X), " & + " 175 (BC_1, PB04_13, output3, X, 174, 0, Z)," & + " 174 (BC_1, *, controlr, 0)," & + " 173 (BC_1, PB04_14, input, X), " & + " 172 (BC_1, PB04_14, output3, X, 171, 0, Z)," & + " 171 (BC_1, *, controlr, 0)," & + " 170 (BC_1, PB04_15, input, X), " & + " 169 (BC_1, PB04_15, output3, X, 168, 0, Z)," & + " 168 (BC_1, *, controlr, 0)," & + " 167 (BC_1, PB04_16, input, X), " & + " 166 (BC_1, PB04_16, output3, X, 165, 0, Z)," & + " 165 (BC_1, *, controlr, 0)," & + " 164 (BC_1, *, internal, X)," & + " 163 (BC_1, *, internal, X)," & + " 162 (BC_1, *, internal, X)," & + " 161 (BC_1, *, internal, X)," & + " 160 (BC_1, *, internal, X)," & + " 159 (BC_1, *, internal, X)," & + " 158 (BC_1, PB05_01, input, X), " & + " 157 (BC_1, PB05_01, output3, X, 156, 0, Z)," & + " 156 (BC_1, *, controlr, 0)," & + " 155 (BC_1, PB05_02, input, X), " & + " 154 (BC_1, PB05_02, output3, X, 153, 0, Z)," & + " 153 (BC_1, *, controlr, 0)," & + " 152 (BC_1, PB05_03, input, X), " & + " 151 (BC_1, PB05_03, output3, X, 150, 0, Z)," & + " 150 (BC_1, *, controlr, 0)," & + " 149 (BC_1, PB05_04, input, X), " & + " 148 (BC_1, PB05_04, output3, X, 147, 0, Z)," & + " 147 (BC_1, *, controlr, 0)," & + " 146 (BC_1, PB05_05, input, X), " & + " 145 (BC_1, PB05_05, output3, X, 144, 0, Z)," & + " 144 (BC_1, *, controlr, 0)," & + " 143 (BC_1, PB05_06, input, X), " & + " 142 (BC_1, PB05_06, output3, X, 141, 0, Z)," & + " 141 (BC_1, *, controlr, 0)," & + " 140 (BC_1, PB05_07, input, X), " & + " 139 (BC_1, PB05_07, output3, X, 138, 0, Z)," & + " 138 (BC_1, *, controlr, 0)," & + " 137 (BC_1, PB05_08, input, X), " & + " 136 (BC_1, PB05_08, output3, X, 135, 0, Z)," & + " 135 (BC_1, *, controlr, 0)," & + " 134 (BC_1, PB05_09, input, X), " & + " 133 (BC_1, PB05_09, output3, X, 132, 0, Z)," & + " 132 (BC_1, *, controlr, 0)," & + " 131 (BC_1, PB05_10, input, X), " & + " 130 (BC_1, PB05_10, output3, X, 129, 0, Z)," & + " 129 (BC_1, *, controlr, 0)," & + " 128 (BC_1, PB05_11, input, X), " & + " 127 (BC_1, PB05_11, output3, X, 126, 0, Z)," & + " 126 (BC_1, *, controlr, 0)," & + " 125 (BC_1, PB05_12, input, X), " & + " 124 (BC_1, PB05_12, output3, X, 123, 0, Z)," & + " 123 (BC_1, *, controlr, 0)," & + " 122 (BC_1, PB05_13, input, X), " & + " 121 (BC_1, PB05_13, output3, X, 120, 0, Z)," & + " 120 (BC_1, *, controlr, 0)," & + " 119 (BC_1, PB05_14, input, X), " & + " 118 (BC_1, PB05_14, output3, X, 117, 0, Z)," & + " 117 (BC_1, *, controlr, 0)," & + " 116 (BC_1, PB05_15, input, X), " & + " 115 (BC_1, PB05_15, output3, X, 114, 0, Z)," & + " 114 (BC_1, *, controlr, 0)," & + " 113 (BC_1, PB05_16, input, X), " & + " 112 (BC_1, PB05_16, output3, X, 111, 0, Z)," & + " 111 (BC_1, *, controlr, 0)," & + " 110 (BC_1, *, internal, X)," & + " 109 (BC_1, *, internal, X)," & + " 108 (BC_1, *, internal, X)," & + " 107 (BC_1, *, internal, X)," & + " 106 (BC_1, *, internal, X)," & + " 105 (BC_1, *, internal, X)," & + " 104 (BC_1, PB06_01, input, X), " & + " 103 (BC_1, PB06_01, output3, X, 102, 0, Z)," & + " 102 (BC_1, *, controlr, 0)," & + " 101 (BC_1, PB06_02, input, X), " & + " 100 (BC_1, PB06_02, output3, X, 99, 0, Z)," & + " 99 (BC_1, *, controlr, 0)," & + " 98 (BC_1, PB06_03, input, X), " & + " 97 (BC_1, PB06_03, output3, X, 96, 0, Z)," & + " 96 (BC_1, *, controlr, 0)," & + " 95 (BC_1, PB06_04, input, X), " & + " 94 (BC_1, PB06_04, output3, X, 93, 0, Z)," & + " 93 (BC_1, *, controlr, 0)," & + " 92 (BC_1, PB06_05, input, X), " & + " 91 (BC_1, PB06_05, output3, X, 90, 0, Z)," & + " 90 (BC_1, *, controlr, 0)," & + " 89 (BC_1, PB06_06, input, X), " & + " 88 (BC_1, PB06_06, output3, X, 87, 0, Z)," & + " 87 (BC_1, *, controlr, 0)," & + " 86 (BC_1, PB06_07, input, X), " & + " 85 (BC_1, PB06_07, output3, X, 84, 0, Z)," & + " 84 (BC_1, *, controlr, 0)," & + " 83 (BC_1, PB06_08, input, X), " & + " 82 (BC_1, PB06_08, output3, X, 81, 0, Z)," & + " 81 (BC_1, *, controlr, 0)," & + " 80 (BC_1, PB06_09, input, X), " & + " 79 (BC_1, PB06_09, output3, X, 78, 0, Z)," & + " 78 (BC_1, *, controlr, 0)," & + " 77 (BC_1, PB06_10, input, X), " & + " 76 (BC_1, PB06_10, output3, X, 75, 0, Z)," & + " 75 (BC_1, *, controlr, 0)," & + " 74 (BC_1, PB06_11, input, X), " & + " 73 (BC_1, PB06_11, output3, X, 72, 0, Z)," & + " 72 (BC_1, *, controlr, 0)," & + " 71 (BC_1, PB06_12, input, X), " & + " 70 (BC_1, PB06_12, output3, X, 69, 0, Z)," & + " 69 (BC_1, *, controlr, 0)," & + " 68 (BC_1, PB06_13, input, X), " & + " 67 (BC_1, PB06_13, output3, X, 66, 0, Z)," & + " 66 (BC_1, *, controlr, 0)," & + " 65 (BC_1, PB06_14, input, X), " & + " 64 (BC_1, PB06_14, output3, X, 63, 0, Z)," & + " 63 (BC_1, *, controlr, 0)," & + " 62 (BC_1, PB06_15, input, X), " & + " 61 (BC_1, PB06_15, output3, X, 60, 0, Z)," & + " 60 (BC_1, *, controlr, 0)," & + " 59 (BC_1, PB06_16, input, X), " & + " 58 (BC_1, PB06_16, output3, X, 57, 0, Z)," & + " 57 (BC_1, *, controlr, 0)," & + " 56 (BC_1, *, internal, X)," & + " 55 (BC_1, *, internal, X)," & + " 54 (BC_1, *, internal, X)," & + " 53 (BC_1, *, internal, X)," & + " 52 (BC_1, *, internal, X)," & + " 51 (BC_1, *, internal, X)," & + " 50 (BC_1, PB07_01, input, X), " & + " 49 (BC_1, PB07_01, output3, X, 48, 0, Z)," & + " 48 (BC_1, *, controlr, 0)," & + " 47 (BC_1, PB07_02, input, X), " & + " 46 (BC_1, PB07_02, output3, X, 45, 0, Z)," & + " 45 (BC_1, *, controlr, 0)," & + " 44 (BC_1, PB07_03, input, X), " & + " 43 (BC_1, PB07_03, output3, X, 42, 0, Z)," & + " 42 (BC_1, *, controlr, 0)," & + " 41 (BC_1, PB07_04, input, X), " & + " 40 (BC_1, PB07_04, output3, X, 39, 0, Z)," & + " 39 (BC_1, *, controlr, 0)," & + " 38 (BC_1, PB07_05, input, X), " & + " 37 (BC_1, PB07_05, output3, X, 36, 0, Z)," & + " 36 (BC_1, *, controlr, 0)," & + " 35 (BC_1, PB07_06, input, X), " & + " 34 (BC_1, PB07_06, output3, X, 33, 0, Z)," & + " 33 (BC_1, *, controlr, 0)," & + " 32 (BC_1, PB07_07, input, X), " & + " 31 (BC_1, PB07_07, output3, X, 30, 0, Z)," & + " 30 (BC_1, *, controlr, 0)," & + " 29 (BC_1, PB07_08, input, X), " & + " 28 (BC_1, PB07_08, output3, X, 27, 0, Z)," & + " 27 (BC_1, *, controlr, 0)," & + " 26 (BC_1, PB07_09, input, X), " & + " 25 (BC_1, PB07_09, output3, X, 24, 0, Z)," & + " 24 (BC_1, *, controlr, 0)," & + " 23 (BC_1, PB07_10, input, X), " & + " 22 (BC_1, PB07_10, output3, X, 21, 0, Z)," & + " 21 (BC_1, *, controlr, 0)," & + " 20 (BC_1, PB07_11, input, X), " & + " 19 (BC_1, PB07_11, output3, X, 18, 0, Z)," & + " 18 (BC_1, *, controlr, 0)," & + " 17 (BC_1, PB07_12, input, X), " & + " 16 (BC_1, PB07_12, output3, X, 15, 0, Z)," & + " 15 (BC_1, *, controlr, 0)," & + " 14 (BC_1, PB07_13, input, X), " & + " 13 (BC_1, PB07_13, output3, X, 12, 0, Z)," & + " 12 (BC_1, *, controlr, 0)," & + " 11 (BC_1, PB07_14, input, X), " & + " 10 (BC_1, PB07_14, output3, X, 9, 0, Z)," & + " 9 (BC_1, *, controlr, 0)," & + " 8 (BC_1, PB07_15, input, X), " & + " 7 (BC_1, PB07_15, output3, X, 6, 0, Z)," & + " 6 (BC_1, *, controlr, 0)," & + " 5 (BC_1, PB07_16, input, X), " & + " 4 (BC_1, PB07_16, output3, X, 3, 0, Z)," & + " 3 (BC_1, *, controlr, 0)," & + " 2 (BC_1, *, internal, X)," & + " 1 (BC_1, *, internal, X)," & + " 0 (BC_1, *, internal, X)"; + +end xc95144xl; -- 2.39.5