From e9d6a20034788258bc5008dc2665aabe9ce28b1c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: [PATCH] arm: socfpga: reset: Add EMAC reset functions Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 17 +++++++++++++++++ .../include/asm/arch-socfpga/reset_manager.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 5d7aba467f..badc569582 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void) { writel(0, &reset_manager_base->per_mod_reset); } + +/* Change the reset state for EMAC 0 and EMAC 1 */ +void socfpga_emac_reset(int enable) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + if (enable) { + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + } else { +#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); +#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); +#endif + } +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 18506e69fd..3c5ab401e1 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); struct socfpga_reset_manager { @@ -29,6 +30,8 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 #endif /* _RESET_MANAGER_H_ */ -- 2.39.5