From f0f1de75c9355aa78c18a1531ad757dcde1fb70e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 31 May 2018 19:25:41 +0200 Subject: [PATCH] clk: renesas: Add PLL1 and PLL3 dividers Add and use the PLL1 and PLL3 dividers. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/clk-rcar-gen3.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 834cd5ac58..f2550598a4 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -200,9 +200,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk) case CLK_TYPE_GEN3_PLL1: rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; - debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n", + rate /= pll_config->pll1_div; + debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, - core->parent, pll_config->pll1_mult, rate); + core->parent, pll_config->pll1_mult, + pll_config->pll1_div, rate); return rate; case CLK_TYPE_GEN3_PLL2: @@ -215,9 +217,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk) case CLK_TYPE_GEN3_PLL3: rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; - debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n", + rate /= pll_config->pll3_div; + debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n", __func__, __LINE__, - core->parent, pll_config->pll3_mult, rate); + core->parent, pll_config->pll3_mult, + pll_config->pll3_div, rate); return rate; case CLK_TYPE_GEN3_PLL4: -- 2.39.5