From f202e1f8d8212686671fd8f1d8d7b6246a0cb33b Mon Sep 17 00:00:00 2001 From: rtel Date: Tue, 22 Sep 2015 08:45:15 +0000 Subject: [PATCH] Baseline new GCC and Renesas compiler projects for RX71M and RX113 before adding IAR projects. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2379 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../.HardwareDebuglinker | 124 + .../Demo/RX113-RSK_GCC_e2studio_IAR/.cproject | 119 + .../Demo/RX113-RSK_GCC_e2studio_IAR/.info | 7 + .../Demo/RX113-RSK_GCC_e2studio_IAR/.project | 232 + .../CodeGenerator/cgprojectDatas.datas | 0 .../Dependency_Scan_Preferences.prefs | 4 + .../Project_Generation_Prefrences.prefs | 22 + .../.settings/language.settings.xml | 13 + .../RTOSDemo HardwareDebug.launch | 101 + .../RX113-RSK_GCC_e2studio_IAR/custom.bat | 0 .../RX113-RSK_GCC_e2studio_IAR/makefile.init | 5 + .../src/Blinky_Demo/main_blinky.c | 235 + .../src/FreeRTOSConfig.h | 161 + .../src/Full_Demo/IntQueueTimer.c | 172 + .../src/Full_Demo/IntQueueTimer.h | 78 + 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create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/iodefine.h create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/rskrx71mdef.h diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.HardwareDebuglinker b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.HardwareDebuglinker new file mode 100644 index 000000000..8f67047ba --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.HardwareDebuglinker @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject new file mode 100644 index 000000000..017cce7d2 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.info b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.info new file mode 100644 index 000000000..209c49b60 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.info @@ -0,0 +1,7 @@ +TOOL_CHAIN=KPIT GNURX-ELF Toolchain +VERSION=v15.01 +TC_INSTALL=C:\Program Files (x86)\KPIT\GNURXv15.01-ELF\rx-elf\rx-elf\ +GCC_STRING=4.8-GNURX_v15.01 +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project new file mode 100644 index 000000000..40109d0cb --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442848178229 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442848203356 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442848203370 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1442849604975 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442849604980 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442849604984 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442849604987 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442849604991 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442849604996 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442849605000 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442849605004 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442849605009 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442849605013 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442849605017 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442849605021 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442849605026 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442849605030 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442849605033 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442848249924 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX100 + + + + 1442848216333 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgprojectDatas.datas b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgprojectDatas.datas new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..5911fae11 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,22 @@ +Library\ Generator\ Command=rx-elf-libgen +com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src"; +com.renesas.cdt.core.Compiler.option.includeFileDir.1240948637="${TCINSTALL}/rx-elf/optlibinc"; +com.renesas.cdt.core.LibraryGenerator.option.ctype=false +com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built +com.renesas.cdt.core.LibraryGenerator.option.math=false +com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized +com.renesas.cdt.core.LibraryGenerator.option.stdio=true +com.renesas.cdt.core.LibraryGenerator.option.stdlib=true +com.renesas.cdt.core.LibraryGenerator.option.string=true +com.renesas.cdt.core.Linker.option.userDefinedOptions=; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType=RX100 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.294362431=RX100 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian=Little-endian data +com.renesas.cdt.rx.HardwareDebug.Compiler.option.disableFPUInstructions=true +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.macroDefines=__RX_LITTLE_ENDIAN__\=1; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=false +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.721512424="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}/no-fpu-libs"; +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml new file mode 100644 index 000000000..9db58ebe7 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..c236cb0a1 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/custom.bat b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/makefile.init b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/makefile.init new file mode 100644 index 000000000..0835091e2 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/makefile.init @@ -0,0 +1,5 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..9ad0a7a61 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,235 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h new file mode 100644 index 000000000..cca782733 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Hardware specifics. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */ +#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 125 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 + +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros +allow the application writer to add additional code before and after the MCU is +placed into the low power state respectively. The implementations provided in +this demo can be extended to save even more power - for example the analog +input used by the low power demo could be switched off in the pre-sleep macro +and back on again in the post sleep macro. */ +void vPreSleepProcessing( unsigned long xExpectedIdleTime ); +void vPostSleepProcessing( unsigned long xExpectedIdleTime ); +#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime ); +#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime ); + +/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral +that generates the tick interrupt. */ +#define configTICK_VECTOR VECT_CMT0_CMI0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..e6f42a206 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,172 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +void vIntQTimerISR0( void ) __attribute__ ((interrupt)); +void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2111UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* On vector 128. */ +void vIntQTimerISR0( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +/* On vector 129. */ +void vIntQTimerISR1( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S new file mode 100644 index 000000000..0d8d1e4cf --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S @@ -0,0 +1,235 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error + + .END diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c new file mode 100644 index 000000000..bae60b1d3 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c @@ -0,0 +1,505 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +void vRegTest1Implementation( void ); +void vRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); +//_RB_ vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + +#ifdef _RB_ + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } +#endif + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c new file mode 100644 index 000000000..68d4ab84f --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c @@ -0,0 +1,418 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.c */ +/* DESCRIPTION : Interrupt Handler */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version: V1.1A */ +/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */ +/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */ +/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */ +/* Date Generated: 25/05/2015 */ +/************************************************************************/ + +#include "interrupt_handlers.h" + +// INT_Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void){/* brk(){ } */} + +// INT_Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void){/* brk(){ } */} + +// NMI +void INT_NonMaskableInterrupt(void){/* brk(){ } */} + +// Dummy +void INT_Dummy(void){/* brk(){ } */} + +// BRK +void INT_Excep_BRK(void){/* wait();*/ } + +// BSC BUSERR +void INT_Excep_BSC_BUSERR(void){ } + +// FCU FRDYI +void INT_Excep_FCU_FRDYI(void){ } + +// ICU SWINT +void INT_Excep_ICU_SWINT(void){ } + +// CMT0 CMI0 +void INT_Excep_CMT0_CMI0(void){ } + +// CMT1 CMI1 +void INT_Excep_CMT1_CMI1(void){ } + +// CMT2 CMI2 +void INT_Excep_CMT2_CMI2(void){ } + +// CMT3 CMI3 +void INT_Excep_CMT3_CMI3(void){ } + +// CAC FERRF +void INT_Excep_CAC_FERRF(void){ } + +// CAC MENDF +void INT_Excep_CAC_MENDF(void){ } + +// CAC OVFF +void INT_Excep_CAC_OVFF(void){ } + +// USB0 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void){ } + +// USB0 D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void){ } + +// USB0 USBI0 +void INT_Excep_USB0_USBI0(void){ } + +// RSPI0 SPEI0 +void INT_Excep_RSPI0_SPEI0(void){ } + +// RSPI0 SPRI0 +void INT_Excep_RSPI0_SPRI0(void){ } + +// RSPI0 SPTI0 +void INT_Excep_RSPI0_SPTI0(void){ } + +// RSPI0 SPII0 +void INT_Excep_RSPI0_SPII0(void){ } + +// DOC DOPCF +void INT_Excep_DOC_DOPCF(void){ } + +// CMPB CMPB0 +void INT_Excep_CMPB_CMPB0(void){ } + +// CMPB CMPB1 +void INT_Excep_CMPB_CMPB1(void){ } + +// CTSU CTSUWR +void INT_Excep_CTSU_CTSUWR(void){ } + +// CTSU CTSURD +void INT_Excep_CTSU_CTSURD(void){ } + +// CTSU CTSUFN +void INT_Excep_CTSU_CTSUFN(void){ } + +// RTC CUP +void INT_Excep_RTC_CUP(void){ } + +// ICU IRQ0 +void INT_Excep_ICU_IRQ0(void){ } + +// ICU IRQ1 +void INT_Excep_ICU_IRQ1(void){ } + +// ICU IRQ2 +void INT_Excep_ICU_IRQ2(void){ } + +// ICU IRQ3 +void INT_Excep_ICU_IRQ3(void){ } + +// ICU IRQ4 +void INT_Excep_ICU_IRQ4(void){ } + +// ICU IRQ5 +void INT_Excep_ICU_IRQ5(void){ } + +// ICU IRQ6 +void INT_Excep_ICU_IRQ6(void){ } + +// ICU IRQ7 +void INT_Excep_ICU_IRQ7(void){ } + +// ELC ELSR8I +void INT_Excep_ELC_ELSR8I(void){ } + +// LVD LVD1 +void INT_Excep_LVD_LVD1(void){ } + +// LVD LVD2 +void INT_Excep_LVD_LVD2(void){ } + +// USB0 USBR0 +void INT_Excep_USB0_USBR0(void){ } + +// RTC ALM +void INT_Excep_RTC_ALM(void){ } + +// RTC PRD +void INT_Excep_RTC_PRD(void){ } + +// S12AD S12ADI0 +void INT_Excep_S12AD_S12ADI0(void){ } + +// S12AD GBADI +void INT_Excep_S12AD_GBADI(void){ } + +// ELC ELSR18I +void INT_Excep_ELC_ELSR18I(void){ } + +// SSI0 SSIF0 +void INT_Excep_SSI0_SSIF0(void){ } + +// SSI0 SSIRXI0 +void INT_Excep_SSI0_SSIRXI0(void){ } + +// SSI0 SSITXI0 +void INT_Excep_SSI0_SSITXI0(void){ } + +// MTU0 TGIA0 +void INT_Excep_MTU0_TGIA0(void){ } + +// MTU0 TGIB0 +void INT_Excep_MTU0_TGIB0(void){ } + +// MTU0 TGIC0 +void INT_Excep_MTU0_TGIC0(void){ } + +// MTU0 TGID0 +void INT_Excep_MTU0_TGID0(void){ } + +// MTU0 TCIV0 +void INT_Excep_MTU0_TCIV0(void){ } + +// MTU0 TGIE0 +void INT_Excep_MTU0_TGIE0(void){ } + +// MTU0 TGIF0 +void INT_Excep_MTU0_TGIF0(void){ } + +// MTU1 TGIA1 +void INT_Excep_MTU1_TGIA1(void){ } + +// MTU1 TGIB1 +void INT_Excep_MTU1_TGIB1(void){ } + +// MTU1 TCIV1 +void INT_Excep_MTU1_TCIV1(void){ } + +// MTU1 TCIU1 +void INT_Excep_MTU1_TCIU1(void){ } + +// MTU2 TGIA2 +void INT_Excep_MTU2_TGIA2(void){ } + +// MTU2 TGIB2 +void INT_Excep_MTU2_TGIB2(void){ } + +// MTU2 TCIV2 +void INT_Excep_MTU2_TCIV2(void){ } + +// MTU2 TCIU2 +void INT_Excep_MTU2_TCIU2(void){ } + +// MTU3 TGIA3 +void INT_Excep_MTU3_TGIA3(void){ } + +// MTU3 TGIB3 +void INT_Excep_MTU3_TGIB3(void){ } + +// MTU3 TGIC3 +void INT_Excep_MTU3_TGIC3(void){ } + +// MTU3 TGID3 +void INT_Excep_MTU3_TGID3(void){ } + +// MTU3 TCIV3 +void INT_Excep_MTU3_TCIV3(void){ } + +// MTU4 TGIA4 +void INT_Excep_MTU4_TGIA4(void){ } + +// MTU4 TGIB4 +void INT_Excep_MTU4_TGIB4(void){ } + +// MTU4 TGIC4 +void INT_Excep_MTU4_TGIC4(void){ } + +// MTU4 TGID4 +void INT_Excep_MTU4_TGID4(void){ } + +// MTU4 TCIV4 +void INT_Excep_MTU4_TCIV4(void){ } + +// MTU5 TGIU5 +void INT_Excep_MTU5_TGIU5(void){ } + +// MTU5 TGIV5 +void INT_Excep_MTU5_TGIV5(void){ } + +// MTU5 TGIW5 +void INT_Excep_MTU5_TGIW5(void){ } + +// POE OEI1 +void INT_Excep_POE_OEI1(void){ } + +// POE OEI2 +void INT_Excep_POE_OEI2(void){ } + +// TMR0 CMIA0 +void INT_Excep_TMR0_CMIA0(void){ } + +// TMR0 CMIB0 +void INT_Excep_TMR0_CMIB0(void){ } + +// TMR0 OVI0 +void INT_Excep_TMR0_OVI0(void){ } + +// TMR1 CMIA1 +void INT_Excep_TMR1_CMIA1(void){ } + +// TMR1 CMIB1 +void INT_Excep_TMR1_CMIB1(void){ } + +// TMR1 OVI1 +void INT_Excep_TMR1_OVI1(void){ } + +// TMR2 CMIA2 +void INT_Excep_TMR2_CMIA2(void){ } + +// TMR2 CMIB2 +void INT_Excep_TMR2_CMIB2(void){ } + +// TMR2 OVI2 +void INT_Excep_TMR2_OVI2(void){ } + +// TMR3 CMIA3 +void INT_Excep_TMR3_CMIA3(void){ } + +// TMR3 CMIB3 +void INT_Excep_TMR3_CMIB3(void){ } + +// TMR3 OVI3 +void INT_Excep_TMR3_OVI3(void){ } + +// SCI2 ERI2 +void INT_Excep_SCI2_ERI2(void){ } + +// SCI2 RXI2 +void INT_Excep_SCI2_RXI2(void){ } + +// SCI2 TXI2 +void INT_Excep_SCI2_TXI2(void){ } + +// SCI2 TEI2 +void INT_Excep_SCI2_TEI2(void){ } + +// SCI0 ERI0 +void INT_Excep_SCI0_ERI0(void){ } + +// SCI0 RXI0 +void INT_Excep_SCI0_RXI0(void){ } + +// SCI0 TXI0 +void INT_Excep_SCI0_TXI0(void){ } + +// SCI0 TEI0 +void INT_Excep_SCI0_TEI0(void){ } + +// SCI1 ERI1 +void INT_Excep_SCI1_ERI1(void){ } + +// SCI1 RXI1 +void INT_Excep_SCI1_RXI1(void){ } + +// SCI1 TXI1 +void INT_Excep_SCI1_TXI1(void){ } + +// SCI1 TEI1 +void INT_Excep_SCI1_TEI1(void){ } + +// SCI5 ERI5 +void INT_Excep_SCI5_ERI5(void){ } + +// SCI5 RXI5 +void INT_Excep_SCI5_RXI5(void){ } + +// SCI5 TXI5 +void INT_Excep_SCI5_TXI5(void){ } + +// SCI5 TEI5 +void INT_Excep_SCI5_TEI5(void){ } + +// SCI6 ERI6 +void INT_Excep_SCI6_ERI6(void){ } + +// SCI6 RXI6 +void INT_Excep_SCI6_RXI6(void){ } + +// SCI6 TXI6 +void INT_Excep_SCI6_TXI6(void){ } + +// SCI6 TEI6 +void INT_Excep_SCI6_TEI6(void){ } + +// SCI8 ERI8 +void INT_Excep_SCI8_ERI8(void){ } + +// SCI8 RXI8 +void INT_Excep_SCI8_RXI8(void){ } + +// SCI8 TXI8 +void INT_Excep_SCI8_TXI8(void){ } + +// SCI8 TEI8 +void INT_Excep_SCI8_TEI8(void){ } + +// SCI9 ERI9 +void INT_Excep_SCI9_ERI9(void){ } + +// SCI9 RXI9 +void INT_Excep_SCI9_RXI9(void){ } + +// SCI9 TXI9 +void INT_Excep_SCI9_TXI9(void){ } + +// SCI9 TEI9 +void INT_Excep_SCI9_TEI9(void){ } + +// SCI12 ERI12 +void INT_Excep_SCI12_ERI12(void){ } + +// SCI12 RXI12 +void INT_Excep_SCI12_RXI12(void){ } + +// SCI12 TXI12 +void INT_Excep_SCI12_TXI12(void){ } + +// SCI12 TEI12 +void INT_Excep_SCI12_TEI12(void){ } + +// SCI12 SCIX0 +void INT_Excep_SCI12_SCIX0(void){ } + +// SCI12 SCIX1 +void INT_Excep_SCI12_SCIX1(void){ } + +// SCI12 SCIX2 +void INT_Excep_SCI12_SCIX2(void){ } + +// SCI12 SCIX3 +void INT_Excep_SCI12_SCIX3(void){ } + +// RIIC0 EEI0 +void INT_Excep_RIIC0_EEI0(void){ } + +// RIIC0 RXI0 +void INT_Excep_RIIC0_RXI0(void){ } + +// RIIC0 TXI0 +void INT_Excep_RIIC0_TXI0(void){ } + +// RIIC0 TEI0 +void INT_Excep_RIIC0_TEI0(void){ } + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h new file mode 100644 index 000000000..92cbbbc4a --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h @@ -0,0 +1,442 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.h */ +/* DESCRIPTION : Interrupt Handler Declarations */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************ +* +* Device : RX/RX100/RX113 +* +* File Name : vect.h +* +* Abstract : Definition of Vector. +* +* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] +* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] +* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation. +* +********************************************************************+++*/ +/************************************************************************/ +/* File Version: V1.1A */ +/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */ +/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */ +/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */ +/* Date Generated: 25/05/2015 */ +/************************************************************************/ + +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +// INT_Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); + +// NMI +void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); + +// Dummy +void INT_Dummy(void) __attribute__ ((interrupt)); + +// BRK +void INT_Excep_BRK(void) __attribute__ ((interrupt)); + +// BSC BUSERR +void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt)); + +// FCU FRDYI +void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); + +// ICU SWINT +void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt)); + +// CMT0 CMI0 +void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt)); + +// CMT1 CMI1 +void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt)); + +// CMT2 CMI2 +void INT_Excep_CMT2_CMI2(void) __attribute__ ((interrupt)); + +// CMT3 CMI3 +void INT_Excep_CMT3_CMI3(void) __attribute__ ((interrupt)); + +// CAC FERRF +void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt)); + +// CAC MENDF +void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt)); + +// CAC OVFF +void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt)); + +// USB0 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt)); + +// USB0 D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt)); + +// USB0 USBI0 +void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPEI0 +void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPRI0 +void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPTI0 +void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPII0 +void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt)); + +// DOC DOPCF +void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt)); + +// CMPB CMPB0 +void INT_Excep_CMPB_CMPB0(void) __attribute__ ((interrupt)); + +// CMPB CMPB1 +void INT_Excep_CMPB_CMPB1(void) __attribute__ ((interrupt)); + +// CTSU CTSUWR +void INT_Excep_CTSU_CTSUWR(void) __attribute__ ((interrupt)); + +// CTSU CTSURD +void INT_Excep_CTSU_CTSURD(void) __attribute__ ((interrupt)); + +// CTSU CTSUFN +void INT_Excep_CTSU_CTSUFN(void) __attribute__ ((interrupt)); + +// RTC CUP +void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt)); + +// ICU IRQ0 +void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt)); + +// ICU IRQ1 +void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt)); + +// ICU IRQ2 +void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt)); + +// ICU IRQ3 +void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt)); + +// ICU IRQ4 +void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt)); + +// ICU IRQ5 +void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt)); + +// ICU IRQ6 +void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt)); + +// ICU IRQ7 +void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt)); + +// ELC ELSR8I +void INT_Excep_ELC_ELSR8I(void) __attribute__ ((interrupt)); + +// LVD LVD1 +void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt)); + +// LVD LVD2 +void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt)); + +// USB0 USBR0 +void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt)); + +// RTC ALM +void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt)); + +// RTC PRD +void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt)); + +// S12AD S12ADI0 +void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt)); + +// S12AD GBADI +void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt)); + +// ELC ELSR18I +void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt)); + +// SSI0 SSIF0 +void INT_Excep_SSI0_SSIF0(void) __attribute__ ((interrupt)); + +// SSI0 SSIRXI0 +void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt)); + +// SSI0 SSITXI0 +void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt)); + +// MTU0 TGIA0 +void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt)); + +// MTU0 TGIB0 +void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt)); + +// MTU0 TGIC0 +void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt)); + +// MTU0 TGID0 +void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt)); + +// MTU0 TCIV0 +void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt)); + +// MTU0 TGIE0 +void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt)); + +// MTU0 TGIF0 +void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt)); + +// MTU1 TGIA1 +void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt)); + +// MTU1 TGIB1 +void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt)); + +// MTU1 TCIV1 +void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt)); + +// MTU1 TCIU1 +void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt)); + +// MTU2 TGIA2 +void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt)); + +// MTU2 TGIB2 +void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt)); + +// MTU2 TCIV2 +void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt)); + +// MTU2 TCIU2 +void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt)); + +// MTU3 TGIA3 +void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt)); + +// MTU3 TGIB3 +void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt)); + +// MTU3 TGIC3 +void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt)); + +// MTU3 TGID3 +void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt)); + +// MTU3 TCIV3 +void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt)); + +// MTU4 TGIA4 +void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt)); + +// MTU4 TGIB4 +void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt)); + +// MTU4 TGIC4 +void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt)); + +// MTU4 TGID4 +void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt)); + +// MTU4 TCIV4 +void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt)); + +// MTU5 TGIU5 +void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt)); + +// MTU5 TGIV5 +void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt)); + +// MTU5 TGIW5 +void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt)); + +// POE OEI1 +void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt)); + +// POE OEI2 +void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt)); + +// TMR0 CMIA0 +void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt)); + +// TMR0 CMIB0 +void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt)); + +// TMR0 OVI0 +void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt)); + +// TMR1 CMIA1 +void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt)); + +// TMR1 CMIB1 +void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt)); + +// TMR1 OVI1 +void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt)); + +// TMR2 CMIA2 +void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt)); + +// TMR2 CMIB2 +void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt)); + +// TMR2 OVI2 +void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt)); + +// TMR3 CMIA3 +void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt)); + +// TMR3 CMIB3 +void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt)); + +// TMR3 OVI3 +void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt)); + +// SCI2 ERI2 +void INT_Excep_SCI2_ERI2(void) __attribute__ ((interrupt)); + +// SCI2 RXI2 +void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt)); + +// SCI2 TXI2 +void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt)); + +// SCI2 TEI2 +void INT_Excep_SCI2_TEI2(void) __attribute__ ((interrupt)); + +// SCI0 ERI0 +void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt)); + +// SCI0 RXI0 +void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); + +// SCI0 TXI0 +void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); + +// SCI0 TEI0 +void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt)); + +// SCI1 ERI1 +void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt)); + +// SCI1 RXI1 +void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); + +// SCI1 TXI1 +void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); + +// SCI1 TEI1 +void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt)); + +// SCI5 ERI5 +void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt)); + +// SCI5 RXI5 +void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); + +// SCI5 TXI5 +void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); + +// SCI5 TEI5 +void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt)); + +// SCI6 ERI6 +void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt)); + +// SCI6 RXI6 +void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); + +// SCI6 TXI6 +void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); + +// SCI6 TEI6 +void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt)); + +// SCI8 ERI8 +void INT_Excep_SCI8_ERI8(void) __attribute__ ((interrupt)); + +// SCI8 RXI8 +void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt)); + +// SCI8 TXI8 +void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt)); + +// SCI8 TEI8 +void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt)); + +// SCI9 ERI9 +void INT_Excep_SCI9_ERI9(void) __attribute__ ((interrupt)); + +// SCI9 RXI9 +void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt)); + +// SCI9 TXI9 +void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt)); + +// SCI9 TEI9 +void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt)); + +// SCI12 ERI12 +void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt)); + +// SCI12 RXI12 +void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt)); + +// SCI12 TXI12 +void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt)); + +// SCI12 TEI12 +void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt)); + +// SCI12 SCIX0 +void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt)); + +// SCI12 SCIX1 +void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt)); + +// SCI12 SCIX2 +void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt)); + +// SCI12 SCIX3 +void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt)); + +// RIIC0 EEI0 +void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt)); + +// RIIC0 RXI0 +void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TXI0 +void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TEI0 +void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt)); + +// ;<> +// ;Power On Reset PC +extern void PowerON_Reset_PC(void) __attribute__ ((interrupt)); +// ;<> + +#endif diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.c new file mode 100644 index 000000000..f553edea2 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.c @@ -0,0 +1,112 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + *******************************************************************************/ +/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */ +/******************************************************************************* + * File Name : r_rsk_async.c + * Version : 1.00 + * Device(s) : R5F51138AxFP + * Tool-Chain : CCRX + * H/W Platform : RSKRX113 + * Description : Functions used to send data via the SCI in asynchronous mode + *******************************************************************************/ +/******************************************************************************* + * History : 26.08.2014 Ver. 1.00 First Release + *******************************************************************************/ + +/******************************************************************************* + System Includes + *******************************************************************************/ +/* Following header file provides string type definitions. */ +#include + +/******************************************************************************* + User Includes (Project Level Includes) + *******************************************************************************/ +/* Defines port registers */ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +#include "r_rsk_async.h" + +/******************************************************************************* + User Defines + *******************************************************************************/ + +/******************************************************************************* + * Global Variables + *******************************************************************************/ + +/* Declaration of the command string to clear the terminal screen */ +static const char cmd_clr_scr[] = +{ 27, 91, 50, 74, 0, 27, 91, 72, 0 }; + +/******************************************************************************* + * Function Prototypes + *******************************************************************************/ + +/* text_write function prototype */ +static void text_write (const char * const msg_string); + +/******************************************************************************* + * Function Name: R_ASYNC_Init + * Description : This function initialises the SCI channel connected to the + * RS232 connector on the RSK. The channel is configured for + * transmission and reception, and instructions are sent to the + * terminal. + * Argument : none + * Return value : none + *******************************************************************************/ +void R_ASYNC_Init (void) +{ + + /* Set up SCI1 receive buffer */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* Enable SCI1 operations */ + R_SCI1_Start(); + + /* Clear the text on terminal window */ + text_write(cmd_clr_scr); + + /* Display splash screen on terminal window */ + text_write("Renesas RSKRX113 Async Serial \r\n"); + + /* Inform user on how to stop transmission */ + text_write("Press 'z' to stop and any key to resume\r\n\n"); +} +/******************************************************************************* + * End of function R_ASYNC_Init + *******************************************************************************/ + +/******************************************************************************* + * Function Name : text_write + * Description : Transmits null-terminated string. + * Argument : (char*) msg_string - null terminated string + * Return value : None + *******************************************************************************/ +static void text_write (const char * const msg_string) +{ + R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string)); +} +/******************************************************************************* + * End of function text_write + *******************************************************************************/ + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.h new file mode 100644 index 000000000..ffcadfe36 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/r_rsk_async.h @@ -0,0 +1,50 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + *******************************************************************************/ +/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */ +/******************************************************************************* + * File Name : r_rsk_async.h + * Version : 1.00 + * Device(s) : R5F51138AxFP + * Tool-Chain : CCRX + * H/W Platform : RSKRX113 + * Description : Functions used to send data via the SCI in asynchronous mode + ******************************************************************************/ +/******************************************************************************* + * History : 26.08.2014 Ver. 1.00 First Release + *******************************************************************************/ + +/******************************************************************************* + * Macro Definitions + *******************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RSK_ASYNC_H +#define R_RSK_ASYNC_H + +/******************************************************************************* + * Global Function Prototypes + *******************************************************************************/ +/* initialise asynchronous transmission*/ +void R_ASYNC_Init (void); + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/reset_program.asm b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/reset_program.asm new file mode 100644 index 000000000..0dabe6f85 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/reset_program.asm @@ -0,0 +1,206 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : reset_program.asm */ +/* DESCRIPTION : Reset Program */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.01 */ +/* Date Generated: 04/03/2015 */ +/************************************************************************/ + + /*reset_program.asm*/ + + .list + .section .text + .global _PowerON_Reset /*global Start routine */ + + .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/ + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _main + .extern _ustack + .extern _istack + .extern _rvectors + .extern _exit + +_PowerON_Reset : +/* initialise user stack pointer */ + mvtc #_ustack,USP + +/* initialise interrupt stack pointer */ + mvtc #_istack,ISP + +#ifdef __RXv2__ +/* setup exception vector */ + mvtc #_ExceptVectors, extb /* EXCEPTION VECTOR ADDRESS */ +#endif + +/* setup intb */ + mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */ + +/* setup FPSW */ + mvtc #100h, fpsw + +/* load data section from ROM to RAM */ + + mov #_mdata,r2 /* src ROM address of data section in R2 */ + mov #_data,r1 /* dest start RAM address of data section in R1 */ + mov #_edata,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ +#ifdef __RX_ALLOW_STRING_INSNS__ + smovf /* block copy R3 bytes from R2 to R1 */ +#else + cmp #0, r3 + beq 2f + +1: mov.b [r2+], r5 + mov.b r5, [r1+] + sub #1, r3 + bne 1b +2: +#endif + + +/* bss initialisation : zero out bss */ + + mov #00h,r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b +/* call the hardware initialiser */ + mov #_HardwareSetup,r7 + jsr r7 + nop + +/* setup PSW */ + mvtc #10000h, psw /* Set Ubit & Ibit for PSW */ + +/* change PSW PM to user-mode */ + MVFC PSW,R1 +//DO NOT SWITCH TO USER MODE OR #00100000h,R1 + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +#ifdef CPPAPP + mov #__rx_init,r7 + jsr r7 +#endif +/* start user program */ + mov #_main,r7 + jsr r7 + mov #_exit,r7 + jsr r7 + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + /* fall through */ + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + mov #next_inilist,r7 + jsr r7 +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + mov #_rx_run_fini_array,r7 + jsr r7 + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + mov #_rx_run_preinit_array,r7 + jsr r7 + mov #_rx_run_init_array,r7 + jsr r7 + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +/* call to exit*/ +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h new file mode 100644 index 000000000..a86382ea4 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h @@ -0,0 +1,28 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 08/07/2013 */ +/************************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c new file mode 100644 index 000000000..937a79efd --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c @@ -0,0 +1,620 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vector_table.c */ +/* DESCRIPTION : Vector Table */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 20/08/2014 */ +/************************************************************************/ + +#include "interrupt_handlers.h" + +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); +extern void vPortSoftwareInterruptISR( void ); +extern void vPortTickISR( void ); +extern void vIntQTimerISR0( void ); +extern void vIntQTimerISR1( void ); + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) + +const void *HardwareVectors[] FVECT_SECT = { +//;0xffffff80 MDES Endian Select Register +#ifdef __RX_LITTLE_ENDIAN__ +(fp)0xffffffff, +#endif +#ifdef __RX_BIG_ENDIAN__ +(fp)0xfffffff8, +#endif +//;0xffffff84 Reserved + (fp)0, +//;0xffffff88 OFS1 + (fp)0xFFFFFFFF, +//;0xffffff8C OFS0 + (fp)0xFFFFFFFF, +//;0xffffff90 Reserved + (fp)0, +//;0xffffff94 Reserved + (fp)0, +//;0xffffff98 Reserved + (fp)0, +//;0xffffff9C Reserved + (fp)0, +//;0xffffffA0 Reserved + (fp)0, + //;0xffffffA4 Reserved + (fp)0, +//;0xffffffA8 Reserved + (fp)0, +//;0xffffffAC Reserved + (fp)0, +//;0xffffffB0 Reserved + (fp)0, +//;0xffffffB4 Reserved + (fp)0, +//;0xffffffB8 Reserved + (fp)0, +//;0xffffffBC Reserved + (fp)0, +//;0xffffffC0 Reserved + (fp)0, +//;0xffffffC4 Reserved + (fp)0, +//;0xffffffC8 Reserved + (fp)0, +//;0xffffffCC Reserved + (fp)0, +//;0xffffffd0 Exception(Supervisor Instruction) + INT_Excep_SuperVisorInst, +//;0xffffffd4 Reserved + (fp)0, +//;0xffffffd8 Reserved + (fp)0, +//;0xffffffdc Exception(Undefined Instruction) + INT_Excep_UndefinedInst, +//;0xffffffe0 Reserved + (fp)0, +//;0xffffffe4 Reserved + (fp)0, +//;0xffffffe8 Reserved + (fp)0, +//;0xffffffec Reserved + (fp)0, +//;0xfffffff0 Reserved + (fp)0, +//;0xfffffff4 Reserved + (fp)0, +//;0xfffffff8 NMI + INT_NonMaskableInterrupt, +//;0xfffffffc RESET +//;<> +//;Power On Reset PC + PowerON_Reset +//;<> +}; +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { +//;0x0000 BRK + (fp)INT_Excep_BRK, +//;0x0004 Reserved + (fp)0, +//;0x0008 Reserved + (fp)0, +//;0x000C Reserved + (fp)0, +//;0x0010 Reserved + (fp)0, +//;0x0014 Reserved + (fp)0, +//;0x0018 Reserved + (fp)0, +//;0x001C Reserved + (fp)0, +//;0x0020 Reserved + (fp)0, +//;0x0024 Reserved + (fp)0, +//;0x0028 Reserved + (fp)0, +//;0x002C Reserved + (fp)0, +//;0x0030 Reserved + (fp)0, +//;0x0034 Reserved + (fp)0, +//;0x0038 Reserved + (fp)0, +//;0x003C Reserved + (fp)0, +//;0x0040 BSC_BUSERR + (fp)INT_Excep_BSC_BUSERR, +//;0x0044 Reserved + (fp)0, +//;0x0048 Reserved + (fp)0, +//;0x004C Reserved + (fp)0, +//;0x0050 Reserved + (fp)0, +//;0x0054 FCUERR + (fp)0, +//;0x0058 Reserved + (fp)0, +//;0x005C FRDYI + (fp)INT_Excep_FCU_FRDYI, +//;0x0060 Reserved + (fp)0, +//;0x0064 Reserved + (fp)0, +//;0x0068 Reserved + (fp)0, +//;0x006C ICU_SWINT + (fp)vPortSoftwareInterruptISR, +//;0x0070 CMT0_CMI0 + (fp)vPortTickISR, +//;0x0074 CMT1_CMI1 + (fp)INT_Excep_CMT1_CMI1, +//;0x0078 CMT2_CMI2 + (fp)INT_Excep_CMT2_CMI2, +//;0x007C CMT3_CMI3 + (fp)INT_Excep_CMT3_CMI3, +//;0x0080 CAC_FERRF + (fp)INT_Excep_CAC_FERRF, +//;0x0084 CAC_MENDF + (fp)INT_Excep_CAC_MENDF, +//;0x0088 CAC_OVFF + (fp)INT_Excep_CAC_OVFF, +//;0x008C Reserved + (fp)0, +//;0x0090 USB0_D0FIFO0 + (fp)INT_Excep_USB0_D0FIFO0, +//;0x0094 USB0_D1FIFO0 + (fp)INT_Excep_USB0_D1FIFO0, +//;0x0098 USB0_USBI0 + (fp)INT_Excep_USB0_USBI0, +//;0x009C Reserved + (fp)0, +//;0x00A0 Reserved + (fp)0, +//;0x00A4 Reserved + (fp)0, +//;0x00A8 Reserved + (fp)0, +//;0x00AC Reserved + (fp)0, +//;0x00B0 RSPI0_SPEI0 + (fp)INT_Excep_RSPI0_SPEI0, +//;0x00B4 RSPI0_SPRI0 + (fp)INT_Excep_RSPI0_SPRI0, +//;0x00B8 RSPI0_SPTI0 + (fp)INT_Excep_RSPI0_SPTI0, +//;0x00BC RSPI0_SPII0 + (fp)INT_Excep_RSPI0_SPII0, +//;0x00C0 Reserved + (fp)0, +//;0x00C4 Reserved + (fp)0, +//;0x00C8 Reserved + (fp)0, +//;0x00CC Reserved + (fp)0, +//;0x00D0 Reserved + (fp)0, +//;0x00D4 Reserved + (fp)0, +//;0x00D8 Reserved + (fp)0, +//;0x00DC Reserved + (fp)0, +//;0x00E0 Reserved + (fp)0, +//;0x00E4 DOC_DOPCF + (fp)INT_Excep_DOC_DOPCF, +//;0x00E8 CMPB_CMPB0 + (fp)INT_Excep_CMPB_CMPB0, +//;0x00EC CMPB_CMPB1 + (fp)INT_Excep_CMPB_CMPB1, +//;0x00F0 CTSU_CTSUWR + (fp)INT_Excep_CTSU_CTSUWR, +//;0x00F4 CTSU_CTSURD + (fp)INT_Excep_CTSU_CTSURD, +//;0x00F8 CTSU_CTSUFN + (fp)INT_Excep_CTSU_CTSUFN, +//;0x00FC Excep_RTC_CUP + (fp)INT_Excep_RTC_CUP, +//;0x0100 IRQ0 + (fp)INT_Excep_ICU_IRQ0, +//;0x0104 IRQ1 + (fp)INT_Excep_ICU_IRQ1, +//;0x0108 IRQ2 + (fp)INT_Excep_ICU_IRQ2, +//;0x010C IRQ3 + (fp)INT_Excep_ICU_IRQ3, +//;0x0110 IRQ4 + (fp)INT_Excep_ICU_IRQ4, +//;0x0114 IRQ5 + (fp)INT_Excep_ICU_IRQ5, +//;0x0118 IRQ6 + (fp)INT_Excep_ICU_IRQ6, +//;0x011C IRQ7 + (fp)INT_Excep_ICU_IRQ7, +//;0x0120 Reserved + (fp)0, +//;0x0124 Reserved + (fp)0, +//;0x0128 Reserved + (fp)0, +//;0x012C Reserved + (fp)0, +//;0x0130 Reserved + (fp)0, +//;0x0134 Reserved + (fp)0, +//;0x0138 Reserved + (fp)0, +//;0x013C Reserved + (fp)0, +//;0x0140 ELC ELSR8I + (fp)INT_Excep_ELC_ELSR8I, +//;0x0144 Reserved + (fp)0, +//;0x0148 Reserved + (fp)0, +//;0x014C Reserved + (fp)0, +//;0x0150 Reserved + (fp)0, +//;0x0154 Reserved + (fp)0, +//;0x0158 Reserved + (fp)0, +//;0x015C Reserved + (fp)0, +//;0x0160 LVD_LVD1 + (fp)INT_Excep_LVD_LVD1, +//;0x0164 LVD_LVD2 + (fp)INT_Excep_LVD_LVD2, +//;0x0168 USB0_USBR0 + (fp)INT_Excep_USB0_USBR0, +//;0x016C Reserved + (fp)0, +//;0x0170 RTC_ALM + (fp)INT_Excep_RTC_ALM, +//;0x0174 RTC_PRD + (fp)INT_Excep_RTC_PRD, +//;0x0178 Reserved + (fp)0, +//;0x017C Reserved + (fp)0, +//;0x0180 Reserved + (fp)0, +//;0x0184 Reserved + (fp)0, +//;0x0188 Reserved + (fp)0, +//;0x018C Reserved + (fp)0, +//;0x0190 Reserved + (fp)0, +//;0x0194 Reserved + (fp)0, +//;0x0198 S12AD_S12ADI0 + (fp)INT_Excep_S12AD_S12ADI0, +//;0x019C S12AD_GBADI + (fp)INT_Excep_S12AD_GBADI, +//104;0x01A0 Reserved + (fp)0, +//105;0x01A4 Reserved + (fp)0, +//;0x01A8 ELC_ELSR18I + (fp)INT_Excep_ELC_ELSR18I, +//;0x01AC Reserved + (fp)0, +//;0x01B0 SSI0_SSIF0 + (fp)INT_Excep_SSI0_SSIF0, +//;0x01B4 SSI0_SSIRXI0 + (fp)INT_Excep_SSI0_SSIRXI0, +//;0x01B8 SSI0_SSITXI0 + (fp)INT_Excep_SSI0_SSITXI0, +//;0x01BC Reserved + (fp)0, +//;0x01C0 Reserved + (fp)0, +//;0x01C4 Reserved + (fp)0, +//;0x01C8 MTU0_TGIA0 + (fp)INT_Excep_MTU0_TGIA0, +//;0x01CC MTU0_TGIB0 + (fp)INT_Excep_MTU0_TGIB0, +//;0x01D0 MTU0_TGIC0 + (fp)INT_Excep_MTU0_TGIC0, +//;0x01D4 MTU0_TGID0 + (fp)INT_Excep_MTU0_TGID0, +//;0x01D8 MTU0_TCIV0 + (fp)INT_Excep_MTU0_TCIV0, +//;0x01DC MTU0_TGIE0 + (fp)INT_Excep_MTU0_TGIE0, +//;0x01E0 MTU0_TGIF0 + (fp)INT_Excep_MTU0_TGIF0, +//;0x01E4 MTU1_TGIA1 + (fp)INT_Excep_MTU1_TGIA1, +//;0x01E8 MTU1_TGIB1 + (fp)INT_Excep_MTU1_TGIB1, +//;0x01EC MTU1_TCIV1 + (fp)INT_Excep_MTU1_TCIV1, +//;0x01F0 MTU1_TCIU1 + (fp)INT_Excep_MTU1_TCIU1, +//;0x01F4 MTU2_TGIA2 + (fp)INT_Excep_MTU2_TGIA2, +//;0x01F8 MTU2_TGIB2 + (fp)INT_Excep_MTU2_TGIB2, +//;0x01FC MTU2_TCIV2 + (fp)INT_Excep_MTU2_TCIV2, +//;0x0200 MTU2_TCIU2 + (fp)INT_Excep_MTU2_TCIU2, +//;0x0204 MTU3_TGIA3 + (fp)INT_Excep_MTU3_TGIA3, +//;0x0208 MTU3_TGIB3 + (fp)INT_Excep_MTU3_TGIB3, +//;0x020C MTU3_TGIC3 + (fp)INT_Excep_MTU3_TGIC3, +//;0x0210 MTU3_TGID3 + (fp)INT_Excep_MTU3_TGID3, +//;0x0214 MTU3_TCIV3 + (fp)INT_Excep_MTU3_TCIV3, +//;0x0218 MTU4_TGIA4 + (fp)INT_Excep_MTU4_TGIA4, +//;0x021C MTU4_TGIB4 + (fp)INT_Excep_MTU4_TGIB4, +//;0x0220 MTU4_TGIC4 + (fp)INT_Excep_MTU4_TGIC4, +//;0x0224 MTU4_TGID4 + (fp)INT_Excep_MTU4_TGID4, +//;0x0228 MTU4_TCIV4 + (fp)INT_Excep_MTU4_TCIV4, +//;0x022C MTU5_TGIU5 + (fp)INT_Excep_MTU5_TGIU5, +//;0x0230 MTU5_TGIV5 + (fp)INT_Excep_MTU5_TGIV5, +//;0x0234 MTU5_TGIW5 + (fp)INT_Excep_MTU5_TGIW5, +//;0x0238 Reserved + (fp)0, +//;0x023C Reserved + (fp)0, +//;0x0240 Reserved + (fp)0, +//;0x0244 Reserved + (fp)0, +//;0x0248 Reserved + (fp)0, +//;0x024C Reserved + (fp)0, +//;0x0250 Reserved + (fp)0, +//;0x0254 Reserved + (fp)0, +//;0x0258 Reserved + (fp)0, +//;0x025C Reserved + (fp)0, +//;0x0260 Reserved + (fp)0, +//;0x0264 Reserved + (fp)0, +//;0x0268 Reserved + (fp)0, +//;0x026C Reserved + (fp)0, +//;0x0270 Reserved + (fp)0, +//;0x0274 Reserved + (fp)0, +//;0x0278 Reserved + (fp)0, +//;0x027C Reserved + (fp)0, +//;0x0280 Reserved + (fp)0, +//;0x0284 Reserved + (fp)0, +//;0x0288 Reserved + (fp)0, +//;0x028C Reserved + (fp)0, +//;0x0290 Reserved + (fp)0, +//;0x0294 Reserved + (fp)0, +//;0x0298 Reserved + (fp)0, +//;0x029C Reserved + (fp)0, +//;0x02A0 Reserved + (fp)0, +//;0x02A4 Reserved + (fp)0, +//;0x02A8 POE_OEI1 + (fp)INT_Excep_POE_OEI1, +//;0x02AC POE_OEI2 + (fp)INT_Excep_POE_OEI2, +//;0x02B0 Reserved + (fp)0, +//;0x02B4 Reserved + (fp)0, +//;0x02B8 TMR0_CMIA0 + (fp)vIntQTimerISR0, +//;0x02BC TMR0_CMIB0 + (fp)INT_Excep_TMR0_CMIB0, +//;0x02C0 TMR0_OVI0 + (fp)INT_Excep_TMR0_OVI0, +//;0x02C4 TMR1_CMIA1 + (fp)INT_Excep_TMR1_CMIA1, +//;0x02C8 TMR1_CMIB1 + (fp)INT_Excep_TMR1_CMIB1, +//;0x02CC TMR1_OVI1 + (fp)INT_Excep_TMR1_OVI1, +//;0x02D0 TMR2_CMIA2 + (fp)vIntQTimerISR1, +//;0x02D4 TMR2_CMIB2 + (fp)INT_Excep_TMR2_CMIB2, +//;0x02D8 TMR2_OVI2 + (fp)INT_Excep_TMR2_OVI2, +//;0x02DC TMR3_CMIA3 + (fp)INT_Excep_TMR3_CMIA3, +//;0x02E0 TMR3_CMIB3 + (fp)INT_Excep_TMR3_CMIB3, +//;0x02E4 TMR3_OVI3 + (fp)INT_Excep_TMR3_OVI3, +//;0x02E8 SCI2_ERI2 + (fp)INT_Excep_SCI2_ERI2, +//;0x02EC SCI2_RXI2 + (fp)INT_Excep_SCI2_RXI2, +//;0x02F0 SCI2_TXI2 + (fp)INT_Excep_SCI2_TXI2, +//;0x02F4 SCI2_TEI2 + (fp)INT_Excep_SCI2_TEI2, +//;0x02F8 Reserved + (fp)0, +//;0x02FC Reserved + (fp)0, +//;0x0300 Reserved + (fp)0, +//;0x0304 Reserved + (fp)0, +//;0x0308 Reserved + (fp)0, +//;0x030C Reserved + (fp)0, +//;0x0310 Reserved + (fp)0, +//;0x0314 Reserved + (fp)0, +//;0x0318 Reserved + (fp)0, +//;0x031C Reserved + (fp)0, +//;0x0320 Reserved + (fp)0, +//;0x0324 Reserved + (fp)0, +//;0x0328 Reserved + (fp)0, +//;0x032C Reserved + (fp)0, +//;0x0330 Reserved + (fp)0, +//;0x0334 Reserved + (fp)0, +//;0x0338 Reserved + (fp)0, +//;0x033C Reserved + (fp)0, +//;0x0340 Reserved + (fp)0, +//;0x0344 Reserved + (fp)0, +//;0x0348 Reserved + (fp)0, +//;0x034C Reserved + (fp)0, +//;0x0350 Reserved + (fp)0, +//;0x0354 Reserved + (fp)0, +//;0x0358 SCI0_ERI0 + (fp)INT_Excep_SCI0_ERI0, +//;0x035C SCI0_RXI0 + (fp)INT_Excep_SCI0_RXI0, +//;0x0360 SCI0_TXI0 + (fp)INT_Excep_SCI0_TXI0, +//;0x0364 SCI0_TEI0 + (fp)INT_Excep_SCI0_TEI0, +//;0x0368 SCI1_ERI1 + (fp)INT_Excep_SCI1_ERI1, +//;0x036C SCI1_RXI1 + (fp)INT_Excep_SCI1_RXI1, +//;0x0370 SCI1_TXI1 + (fp)INT_Excep_SCI1_TXI1, +//;0x0374 SCI1_TEI1 + (fp)INT_Excep_SCI1_TEI1, +//;0x0378 SCI5_ERI5 + (fp)INT_Excep_SCI5_ERI5, +//;0x037C SCI5_RXI5 + (fp)INT_Excep_SCI5_RXI5, +//;0x0380 SCI5_TXI5 + (fp)INT_Excep_SCI5_TXI5, +//;0x0384 SCI5_TEI5 + (fp)INT_Excep_SCI5_TEI5, +//;0x0388 SCI6_ERI6 + (fp)INT_Excep_SCI6_ERI6, +//;0x038C SCI6_RXI6 + (fp)INT_Excep_SCI6_RXI6, +//;0x0390 SCI6_TXI6 + (fp)INT_Excep_SCI6_TXI6, +//;0x0394 SCI6_TEI6 + (fp)INT_Excep_SCI6_TEI6, +//;0x0398 SCI8_ERI8 + (fp)INT_Excep_SCI8_ERI8, +//;0x039C SCI8_RXI8 + (fp)INT_Excep_SCI8_RXI8, +//;0x03A0 SCI8_TXI8 + (fp)INT_Excep_SCI8_TXI8, +//;0x03A4 SCI8_TEI8 + (fp)INT_Excep_SCI8_TEI8, +//;0x03A8 SCI9_ERI9 + (fp)INT_Excep_SCI9_ERI9, +//;0x03AC SCI9_RXI9 + (fp)INT_Excep_SCI9_RXI9, +//;0x03B0 SCI9_TXI9 + (fp)INT_Excep_SCI9_TXI9, +//;0x03B4 SCI9_TEI9 + (fp)INT_Excep_SCI9_TEI9, +//;0x03B8 SCI12_ERI12 + (fp)INT_Excep_SCI12_ERI12, +//;0x03BC SCI12_RXI12 + (fp)INT_Excep_SCI12_RXI12, +//;0x03C0 SCI12_TXI12 + (fp)INT_Excep_SCI12_TXI12, +//;0x03C4 SCI12_TEI12 + (fp)INT_Excep_SCI12_TEI12, +//;0x03C8 SCI12_SCIX0 + (fp)INT_Excep_SCI12_SCIX0, +//;0x03CC SCI12_SCIX1 + (fp)INT_Excep_SCI12_SCIX1, +//;0x03D0 SCI12_SCIX2 + (fp)INT_Excep_SCI12_SCIX2, +//;0x03D4 SCI12_SCIX3 + (fp)INT_Excep_SCI12_SCIX3, +//;0x03D8 RIIC0_EEI0 + (fp)INT_Excep_RIIC0_EEI0, +//;0x03DC RIIC0_RXI0 + (fp)INT_Excep_RIIC0_RXI0, +//;0x03E0 RIIC0_TXI0 + (fp)INT_Excep_RIIC0_TXI0, +//;0x03E4 RIIC0_TEI0 + (fp)INT_Excep_RIIC0_TEI0, +//;0x03E8 Reserved + (fp)0, +//;0x03EC Reserved + (fp)0, +//;0x03F0 Reserved + (fp)0, +//;0x03F4 Reserved + (fp)0, +//;0x03F8 Reserved + (fp)0, +//;0x03FC Reserved + (fp)0, +}; diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..a59c3f126 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c @@ -0,0 +1,131 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + uint32_t w_count; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | + _00000000_CGC_FCLK_DIV_1; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Stop sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Stop sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Wait for 5 sub-clock cycles */ + for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++) + { + __asm volatile( "NOP" ); + } + + /* Set sub-clock drive capacity */ + RTC.RCR3.BIT.RTCDV = 1U; + + /* Wait for the register modification to complete */ + while (1U != RTC.RCR3.BIT.RTCDV); + + /* Set sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 0U; + + /* Wait for the register modification to complete */ + while (0U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Wait for sub-clock to be stable */ + for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++) + { + __asm volatile( "NOP" ); + } + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..6a32749c4 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */ + +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + HOCO Wait Control Register (HOCOWTCR) +*/ +/* HOCO Wait Time (HOCOWTCR) */ +#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */ +#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + LCD Source Clock Control Register (LCDSCLKCR) +*/ +/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */ +#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */ +#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */ +#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */ +#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */ +#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */ +#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..da709aa9b --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..90e9f5265 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,101 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Initialize non-existent pins */ + PORT0.PDR.BYTE = 0x6BU; + PORT3.PDR.BYTE = 0xD8U; + PORT4.PDR.BYTE = 0xA0U; + PORT5.PDR.BYTE = 0x80U; + PORT9.PDR.BYTE = 0xF8U; + PORTD.PDR.BYTE = 0xE0U; + PORTF.PDR.BYTE = 0x3FU; + PORTJ.PDR.BYTE = 0x32U; + + /* Set peripheral settings */ + R_CGC_Create(); + R_PORT_Create(); + R_SCI1_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..370d54947 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +//_RB_#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +/* BRK handler command options */ +typedef enum { + BRK_NO_COMMAND, + BRK_ALL_MODULE_CLOCK_STOP, + BRK_SLEEP, + BRK_DEEP_SLEEP, + BRK_STANDBY, + BRK_LOAD_FINTV_REGISTER +} brk_commands; +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #ifndef __int8_t_defined + #define __int8_t_defined + #endif + typedef signed char int8_t; + typedef signed short int16_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c new file mode 100644 index 000000000..4a893345a --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c @@ -0,0 +1,65 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | + _00_Pm7_MODE_INPUT; + PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT; + PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h new file mode 100644 index 000000000..f331d6cf8 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Direction Register (PDR) +*/ +/* Pmn Direction Control (B7 - B0) */ +#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */ +#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */ +#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */ +#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */ +#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */ +#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */ +#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */ +#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */ +#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */ +#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */ +#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */ +#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */ +#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */ +#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */ +#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */ +#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */ +#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */ +#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */ +#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */ +#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */ +#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */ +#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */ +#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */ +#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */ + +/* + Port Output Data Register (PODR) +*/ +/* Pmn Output Data Store (B7 - B0) */ +#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */ +#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */ +#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */ +#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */ +#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */ +#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */ +#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */ +#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */ +#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */ +#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */ +#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */ +#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */ +#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */ +#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */ +#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */ +#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */ + +/* + Open Drain Control Register 0 (ODR0) +*/ +/* Pmn Output Type Select (Pm0 to Pm3) */ +#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */ +#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */ +#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */ +#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */ +#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */ +#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */ +#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */ +#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */ + +/* + Open Drain Control Register 1 (ODR1) +*/ +/* Pmn Output Type Select (Pm4 to Pm7) */ +#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */ +#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */ +#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */ +#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */ +#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */ +#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */ +#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */ +#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */ + +/* + Pull-Up Control Register (PCR) +*/ +/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */ +#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */ +#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */ +#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */ +#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */ +#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */ +#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */ +#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */ +#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */ +#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */ +#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */ +#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */ +#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */ +#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */ +#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */ +#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */ +#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */ + +/* + Port Switching Register A (PSRA) +*/ +/* PB6/PC0 Switching (PSEL6) */ +#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */ +#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */ +/* PB7/PC1 Switching (PSEL7) */ +#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */ +#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */ +#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */ +#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */ +#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */ +#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */ +#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */ +#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */ +#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c new file mode 100644 index 000000000..0239dde20 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..823d383ec --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..9840cd1ba --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c new file mode 100644 index 000000000..761f53ca5 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */ +uint16_t g_sci1_tx_count; /* SCI1 transmit data number */ +uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */ +uint16_t g_sci1_rx_count; /* SCI1 receive data number */ +uint16_t g_sci1_rx_length; /* SCI1 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_SCI1_Create +* Description : This function initializes the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Create(void) +{ + /* Cancel SCI1 module stop state */ + MSTP(SCI1) = 0U; + + /* Set interrupt priority */ + IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15; + + /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */ + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.RIE = 0U; + SCI1.SCR.BIT.TE = 0U; + SCI1.SCR.BIT.RE = 0U; + SCI1.SCR.BIT.TEIE = 0U; + + /* Set RXD1 pin */ + MPC.P15PFS.BYTE = 0x0AU; + PORT1.PMR.BYTE |= 0x20U; + /* Set TXD1 pin */ + MPC.P16PFS.BYTE = 0x0AU; + PORT1.PODR.BYTE |= 0x40U; + PORT1.PDR.BYTE |= 0x40U; + PORT1.PMR.BYTE |= 0x40U; + + /* Set clock enable */ + SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + + /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */ + SCI1.SIMR1.BIT.IICM = 0U; + SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; + + /* Set control registers */ + SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; + SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT; + + /* Set SEMR, SNFR */ + SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK; + + /* Set bitrate */ + SCI1.BRR = 0x19U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Start +* Description : This function starts the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Start(void) +{ + IR(SCI1,TXI1) = 0U; + IR(SCI1,TEI1) = 0U; + IR(SCI1,RXI1) = 0U; + IR(SCI1,ERI1) = 0U; + IEN(SCI1,TXI1) = 1U; + IEN(SCI1,TEI1) = 1U; + IEN(SCI1,RXI1) = 1U; + IEN(SCI1,ERI1) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Stop +* Description : This function stops the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Stop(void) +{ + /* Set TXD1 pin */ + PORT1.PMR.BYTE &= 0xBFU; + + SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */ + SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */ + SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */ + IR(SCI1,TXI1) = 0U; + IEN(SCI1,TXI1) = 0U; + IR(SCI1,TEI1) = 0U; + IEN(SCI1,TEI1) = 0U; + IR(SCI1,RXI1) = 0U; + IEN(SCI1,RXI1) = 0U; + IR(SCI1,ERI1) = 0U; + IEN(SCI1,ERI1) = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Serial_Receive +* Description : This function receives SCI1 data. +* Arguments : rx_buf - +* receive buffer pointer (Not used when receive data handled by DTC) +* rx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + MD_STATUS status = MD_OK; + + if (rx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + g_sci1_rx_count = 0U; + g_sci1_rx_length = rx_num; + gp_sci1_rx_address = rx_buf; + SCI1.SCR.BIT.RIE = 1U; + SCI1.SCR.BIT.RE = 1U; + } + + return (status); +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Serial_Send +* Description : This function transmits SCI1 data. +* Arguments : tx_buf - +* transfer buffer pointer (Not used when transmit data handled by DTC) +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (tx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + gp_sci1_tx_address = tx_buf; + g_sci1_tx_count = tx_num; + /* Set TXD1 pin */ + PORT1.PMR.BYTE |= 0x40U; + SCI1.SCR.BIT.TIE = 1U; + SCI1.SCR.BIT.TE = 1U; + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h new file mode 100644 index 000000000..e71ca6b83 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h @@ -0,0 +1,307 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef SCI_H +#define SCI_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* + Serial mode register (SMR) +*/ +/* Clock select (CKS) */ +#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */ +#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */ +#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */ +#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */ +/* Multi-processor Mode (MP) */ +#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */ +#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */ +/* Stop bit length (STOP) */ +#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */ +#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */ +/* Parity mode (PM) */ +#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */ +#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */ +/* Parity enable (PE) */ +#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */ +#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */ +/* Character length (CHR) */ +#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */ +#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */ +/* Communications mode (CM) */ +#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */ +#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */ +/* Base clock pulse (BCP) */ +#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */ +#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */ +#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */ +#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */ +/* Block transfer mode (BLK) */ +#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */ +#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */ +/* GSM mode (GSM) */ +#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */ +#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */ + +/* + Serial control register (SCR) +*/ +/* Clock enable (CKE) */ +#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */ +#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */ +#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */ +#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */ +/* Transmit end interrupt enable (TEIE) */ +#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */ +#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */ +/* Multi-processor interrupt enable (MPIE) */ +#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */ +#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */ +/* Receive enable (RE) */ +#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */ +#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */ +/* Transmit enable (TE) */ +#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */ +#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */ +/* Receive interrupt enable (RIE) */ +#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */ +#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */ +/* Transmit interrupt enable (TIE) */ +#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */ +#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */ + +/* + Serial status register (SSR) +*/ +/* Multi-Processor bit transfer (MPBT) */ +#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */ +#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */ +/* Multi-Processor (MPB) */ +#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */ +#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */ +/* Transmit end flag (TEND) */ +#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */ +#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */ +/* Parity error flag (PER) */ +#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */ +/* Framing error flag (FER) */ +#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */ +/* Overrun error flag (ORER) */ +#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */ + +/* + Smart card mode register (SCMR) +*/ +/* Smart card interface mode select (SMIF) */ +#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */ +#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */ +/* Transmitted / received data invert (SINV) */ +#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */ +#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */ +/* Transmitted / received data transfer direction (SDIR) */ +#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */ +#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */ +/* Base clock pulse 2 (BCP2) */ +#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */ +#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */ +#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */ + +/* + Serial extended mode register (SEMR) +*/ +/* Asynchronous Mode Clock Source Select (ACS0) */ +#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */ +#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */ +/* Asynchronous mode base clock select (ABCS) */ +#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */ +#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ +/* Digital noise filter function enable (NFEN) */ +#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */ +#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */ +/* Asynchronous start bit edge detections select (RXDESEL) */ +#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */ +#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */ + +/* + Noise filter setting register (SNFR) +*/ +/* Noise filter clock select (NFCS) */ +#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */ +#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */ +#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */ +#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */ +#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */ + +/* + I2C mode register 1 (SIMR1) +*/ +/* Simple IIC mode select (IICM) */ +#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */ +#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */ + +/* + I2C mode register 2 (SIMR2) +*/ +/* IIC interrupt mode select (IICINTM) */ +#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */ +#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */ +/* Clock synchronization (IICCSC) */ +#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */ +#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */ +/* ACK transmission data (IICACKT) */ +#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */ +#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */ + +/* + I2C mode register 3 (SIMR3) +*/ +/* Start condition generation (IICSTAREQ) */ +#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */ +#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */ +/* Restart condition generation (IICRSTAREQ) */ +#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */ +#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */ +/* Stop condition generation (IICSTPREQ) */ +#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */ +#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */ +/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */ +#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */ +#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */ +/* SSDA output select (IICSDAS) */ +#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */ +#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */ +#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */ +#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */ +/* SSCL output select (IICSCLS) */ +#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */ +#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */ +#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */ +#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */ + +/* + I2C status register (SISR) +*/ +/* ACK reception data flag (IICACKR) */ +#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */ +#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */ + +/* + SPI mode register (SPMR) +*/ +/* SS pin function enable (SSE) */ +#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */ +#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */ +/* CTS enable (CTSE) */ +#define _00_SCI_RTS (0x00U) /* RTS function is enabled */ +#define _02_SCI_CTS (0x02U) /* CTS function is disabled */ +/* Master slave select (MSS) */ +#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */ +#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */ +/* Mode fault flag (MFF) */ +#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */ +#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */ +/* Clock polarity select (CKPOL) */ +#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */ +#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */ +/* Clock phase select (CKPH) */ +#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */ +#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Transfer status control value +*/ +/* Simple IIC Transmit Receive Flag */ +#define _80_SCI_IIC_TRANSMISSION (0x80U) +#define _00_SCI_IIC_RECEPTION (0x00U) +/* Simple IIC Start Stop Flag */ +#define _80_SCI_IIC_START_CYCLE (0x80U) +#define _00_SCI_IIC_STOP_CYCLE (0x00U) +/* Multiprocessor Asynchronous Communication Flag */ +#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U) +#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U) + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_SCI1_Create(void); +void R_SCI1_Start(void); +void R_SCI1_Stop(void); +MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num); +MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num); +static void r_sci1_callback_transmitend(void); +static void r_sci1_callback_receiveend(void); +static void r_sci1_callback_receiveerror(void); + +/* Start user code for function. Do not edit comment generated here */ + +/* Some of the code in this file is generated using "Code Generator" for e2 studio. + * Warnings exist in this module. */ + +/* Exported functions used to transmit a number of bytes and wait for completion */ +MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num); + +/* Character is used to receive key presses from PC terminal */ +extern uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +extern volatile uint8_t g_tx_flag; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c new file mode 100644 index 000000000..aec0de101 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +#include "rskrx113def.h" +//_RB_#include "r_cg_cmt.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */ +extern uint16_t g_sci1_tx_count; /* SCI1 send data number */ +extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */ +extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */ +extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */ +/* Start user code for global. Do not edit comment generated here */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci1_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci1_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1 +#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint) +#else +#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1)) +#endif +static void r_sci1_transmit_interrupt(void) +{ + if (g_sci1_tx_count > 0U) + { + SCI1.TDR = *gp_sci1_tx_address; + gp_sci1_tx_address++; + g_sci1_tx_count--; + } + else + { + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.TEIE = 1U; + } +} +/*********************************************************************************************************************** +* Function Name: r_sci1_transmitend_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1 +#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint) +#else +#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1)) +#endif +static void r_sci1_transmitend_interrupt(void) +{ + /* Set TXD1 pin */ + PORT1.PMR.BYTE &= 0xBFU; + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.TE = 0U; + SCI1.SCR.BIT.TEIE = 0U; + + r_sci1_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci1_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1 +#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint) +#else +#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1)) +#endif +static void r_sci1_receive_interrupt(void) +{ + if (g_sci1_rx_length > g_sci1_rx_count) + { + *gp_sci1_rx_address = SCI1.RDR; + gp_sci1_rx_address++; + g_sci1_rx_count++; + + if (g_sci1_rx_length == g_sci1_rx_count) + { + r_sci1_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci1_receiveerror_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1 +#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint) +#else +#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1)) +#endif +static void r_sci1_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci1_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI1.SSR.BYTE; + SCI1.SSR.BYTE = err_type & 0xC7U; +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_transmitend +* Description : This function is a callback function when SCI1 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci1_txdone = TRUE; + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_receiveend +* Description : This function is a callback function when SCI1 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if ('z' == g_rx_char) + { + /* Stop the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT0_Stop(); + + /* Turn off LED0 and turn on LED1 to indicate serial transmission + inactive */ + LED0 = LED_OFF; + LED1 = LED_ON; + } + else + { + /* Start the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT0_Start(); + + /* Turn on LED0 and turn off LED1 to indicate serial transmission + active */ + LED0 = LED_ON; + LED1 = LED_OFF; + } + + /* Set up SCI1 receive buffer again */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_receiveerror +* Description : This function is a callback function when SCI1 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/*********************************************************************************************************************** + * Function Name: R_SCI1_AsyncTransmit + * Description : This function sends SCI1 data and waits for the transmit end flag. + * Arguments : tx_buf - + * transfer buffer pointer + * tx_num - + * buffer size + * Return Value : status - + * MD_OK or MD_ARGERROR + ***********************************************************************************************************************/ +MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci1_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI1_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci1_txdone) + { + /* Wait */ + } + return (status); +} +/*********************************************************************************************************************** + * End of function R_SCI1_AsyncTransmit + ***********************************************************************************************************************/ + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..d5e1b6ab8 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,40 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +#define TRUE (1) +#define FALSE (0) +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/iodefine.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/iodefine.h new file mode 100644 index 000000000..9597b68ec --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/iodefine.h @@ -0,0 +1,11809 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : Definition of I/O Registers */ +/* CPU SERIES : RX100 */ +/* CPU TYPE : RX113 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************************* +* +* Device : RX/RX100/RX113 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40] +* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50] +* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00] +* : 1.0A (2015-04-20) [Hardware Manual Revision : 1.02 + TU] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX113 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX113IODEFINE_HEADER__ +#define __RX113IODEFINE_HEADER__ + +#pragma pack(4) + +struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short : 2; + unsigned short BPFB : 2; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short BPFB : 2; + unsigned short : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INI : 1; + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; + unsigned char CPB0INI : 1; +#endif + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0WCP : 1; + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; + unsigned char CPB0WCP : 1; +#endif + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; + unsigned char CPB1OUT : 1; +#else + unsigned char CPB1OUT : 1; + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INTEN : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTPL : 1; + unsigned char : 1; + unsigned char CPB1INTEN : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB1INTPL : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTEN : 1; + unsigned char : 1; + unsigned char CPB0INTPL : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTEN : 1; +#endif + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0FEN : 1; + unsigned char : 1; + unsigned char CPB0F : 2; + unsigned char CPB1FEN : 1; + unsigned char : 1; + unsigned char CPB1F : 2; +#else + unsigned char CPB1F : 2; + unsigned char : 1; + unsigned char CPB1FEN : 1; + unsigned char CPB0F : 2; + unsigned char : 1; + unsigned char CPB0FEN : 1; +#endif + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPBSPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPBSPDMD : 1; +#endif + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0VRF : 1; + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; + unsigned char CPB0VRF : 1; +#endif + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0OE : 1; + unsigned char CPB0OP : 1; + unsigned char : 2; + unsigned char CPB1OE : 1; + unsigned char CPB1OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB1OP : 1; + unsigned char CPB1OE : 1; + unsigned char : 2; + unsigned char CPB0OP : 1; + unsigned char CPB0OE : 1; +#endif + } BIT; + } CPBOCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTRT : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSNZ : 1; + unsigned char : 1; + unsigned char CTSUINIT : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CTSUINIT : 1; + unsigned char : 1; + unsigned char CTSUSNZ : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSTRT : 1; +#endif + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPON : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUCLK : 2; + unsigned char CTSUMD : 2; +#else + unsigned char CTSUMD : 2; + unsigned char CTSUCLK : 2; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUPON : 1; +#endif + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPRRATIO : 4; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUSOFF : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CTSUSOFF : 1; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUPRRATIO : 4; +#endif + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSST : 8; +#else + unsigned char CTSUSST : 8; +#endif + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH0 : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUMCH0 : 4; +#endif + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH1 : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUMCH1 : 4; +#endif + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC00 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC07 : 1; +#else + unsigned char CTSUCHAC07 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC00 : 1; +#endif + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC10 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC10 : 1; +#endif + } BIT; + } CTSUCHAC1; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC00 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC07 : 1; +#else + unsigned char CTSUCHTRC07 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC00 : 1; +#endif + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC10 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC10 : 1; +#endif + } BIT; + } CTSUCHTRC1; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSSMOD : 2; + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; + unsigned char CTSUSSMOD : 2; +#endif + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTC : 3; + unsigned char : 1; + unsigned char CTSUDTSR : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUPS : 1; +#else + unsigned char CTSUPS : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUDTSR : 1; + unsigned char : 1; + unsigned char CTSUSTC : 3; +#endif + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CTSUSSDIV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CTSUSSDIV : 4; + unsigned short : 8; +#endif + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSO : 10; + unsigned short CTSUSNUM : 6; +#else + unsigned short CTSUSNUM : 6; + unsigned short CTSUSO : 10; +#endif + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURICOA : 8; + unsigned short CTSUSDPA : 5; + unsigned short CTSUICOG : 2; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CTSUICOG : 2; + unsigned short CTSUSDPA : 5; + unsigned short CTSURICOA : 8; +#endif + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSC : 16; +#else + unsigned short CTSUSC : 16; +#endif + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURC : 16; +#else + unsigned short CTSURC : 16; +#endif + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short CTSUICOMP : 1; +#else + unsigned short CTSUICOMP : 1; + unsigned short : 15; +#endif + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char : 6; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char REF : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char REF : 3; +#endif + } BIT; + } DAVREFCR; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR[26]; + char wk0[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char MTU1MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DFLEN : 1; +#endif + } BIT; + } DFLCTL; + char wk0[31]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short SASMF : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short SASMF : 1; + unsigned short : 8; +#endif + } BIT; + } FSCMR; + unsigned short FAWSMR; + unsigned short FAWEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PCKA : 5; + unsigned char : 1; + unsigned char SAS : 2; +#else + unsigned char SAS : 2; + unsigned char : 1; + unsigned char PCKA : 5; +#endif + } BIT; + } FISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 3; + unsigned char : 4; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char : 4; + unsigned char CMD : 3; +#endif + } BIT; + } FEXCR; + unsigned short FEAML; +// char wk1[1]; + unsigned char FEAMH; + char wk2[5]; + unsigned char FPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PERR : 1; +#endif + } BIT; + } FPSR; + unsigned short FRBL; + unsigned short FRBH; + char wk3[16058]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; + unsigned char RPDIS : 1; + unsigned char FMS1 : 1; + unsigned char : 1; + unsigned char LVPE : 1; + unsigned char FMS2 : 1; +#else + unsigned char FMS2 : 1; + unsigned char LVPE : 1; + unsigned char : 1; + unsigned char FMS1 : 1; + unsigned char RPDIS : 1; + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; +#endif + } BIT; + } FPMCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXS : 1; +#endif + } BIT; + } FASR; + unsigned short FSARL; +// char wk4[1]; + unsigned char FSARH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 4; + unsigned char DRC : 1; + unsigned char : 1; + unsigned char STOP : 1; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char STOP : 1; + unsigned char : 1; + unsigned char DRC : 1; + unsigned char CMD : 4; +#endif + } BIT; + } FCR; + unsigned short FEARL; + unsigned char FEARH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRESET : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRESET : 1; +#endif + } BIT; + } FRESETR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ERERR : 1; + unsigned char PRGERR : 1; + unsigned char : 1; + unsigned char BCERR : 1; + unsigned char ILGLERR : 1; + unsigned char EILGLERR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char EILGLERR : 1; + unsigned char ILGLERR : 1; + unsigned char BCERR : 1; + unsigned char : 1; + unsigned char PRGERR : 1; + unsigned char ERERR : 1; +#endif + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char DRRDY : 1; + unsigned char : 4; + unsigned char FRDY : 1; + unsigned char EXRDY : 1; +#else + unsigned char EXRDY : 1; + unsigned char FRDY : 1; + unsigned char : 4; + unsigned char DRRDY : 1; + unsigned char : 1; +#endif + } BIT; + } FSTATR1; + unsigned short FWBL; + unsigned short FWBH; + char wk5[34]; + union { + unsigned short WORD; +// struct { +// unsigned short FEKEY:8; +// unsigned short FENTRYD:1; +// unsigned short :6; +// unsigned short FENTRY0:1; +// } BIT; + } FENTRYR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[250]; + char wk0[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[249]; + char wk1[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[250]; + char wk5[262]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[8]; + char wk6[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + char wk7[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + char wk8[106]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk9[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk10[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRRXINV : 1; + unsigned char IRTXINV : 1; + unsigned char IRCKS : 3; + unsigned char IRE : 1; +#else + unsigned char IRE : 1; + unsigned char IRCKS : 3; + unsigned char IRTXINV : 1; + unsigned char IRRXINV : 1; + unsigned char : 2; +#endif + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +}; + +struct st_lcdc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LBAS : 2; + unsigned char LDTY : 3; + unsigned char LWAVE : 1; + unsigned char MDSET : 2; +#else + unsigned char MDSET : 2; + unsigned char LWAVE : 1; + unsigned char LDTY : 3; + unsigned char LBAS : 2; +#endif + } BIT; + } LCDM0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCDVLM : 1; + unsigned char : 2; + unsigned char LCDSEL : 1; + unsigned char BLON : 1; + unsigned char VLCON : 1; + unsigned char SCOC : 1; + unsigned char LCDON : 1; +#else + unsigned char LCDON : 1; + unsigned char SCOC : 1; + unsigned char VLCON : 1; + unsigned char BLON : 1; + unsigned char LCDSEL : 1; + unsigned char : 2; + unsigned char LCDVLM : 1; +#endif + } BIT; + } LCDM1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCDC0 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LCDC0 : 6; +#endif + } BIT; + } LCDC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VLCD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char VLCD : 5; +#endif + } BIT; + } VLCD; + char wk0[60]; + unsigned char SEG00; + unsigned char SEG01; + unsigned char SEG02; + unsigned char SEG03; + unsigned char SEG04; + unsigned char SEG05; + unsigned char SEG06; + unsigned char SEG07; + unsigned char SEG08; + unsigned char SEG09; + unsigned char SEG10; + unsigned char SEG11; + unsigned char SEG12; + unsigned char SEG13; + unsigned char SEG14; + unsigned char SEG15; + unsigned char SEG16; + unsigned char SEG17; + unsigned char SEG18; + unsigned char SEG19; + unsigned char SEG20; + unsigned char SEG21; + unsigned char SEG22; + unsigned char SEG23; + unsigned char SEG24; + unsigned char SEG25; + unsigned char SEG26; + unsigned char SEG27; + unsigned char SEG28; + unsigned char SEG29; + unsigned char SEG30; + unsigned char SEG31; + unsigned char SEG32; + unsigned char SEG33; + unsigned char SEG34; + unsigned char SEG35; + unsigned char SEG36; + unsigned char SEG37; + unsigned char SEG38; + unsigned char SEG39; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTPSSEL : 3; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCNTPSSEL : 3; +#endif + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LPCNTSTP : 1; +#endif + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTEN : 1; + unsigned char LPCNTRST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LPCNTRST : 1; + unsigned char LPCNTEN : 1; +#endif + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCNTPRD : 16; +#else + unsigned short LPCNTPRD : 16; +#endif + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR0 : 16; +#else + unsigned short LPCMR0 : 16; +#endif + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short LPWKUPEN : 1; +#else + unsigned short LPWKUPEN : 1; + unsigned short : 15; +#endif + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk0[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P02PFS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P04PFS; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P32PFS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P35PFS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P56PFS; + char wk7[25]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P92PFS; + char wk8[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD4PFS; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE7PFS; + char wk10[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PF6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PF7PFS; + char wk11[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ0PFS; + char wk12[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ3PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ7PFS; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char : 6; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 6; + unsigned char WRE : 1; +#endif + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 3; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 3; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short POE1M : 2; + unsigned short POE2M : 2; + unsigned short POE3M : 2; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short POE1F : 1; + unsigned short POE2F : 1; + unsigned short POE3F : 1; +#else + unsigned short POE3F : 1; + unsigned short POE2F : 1; + unsigned short POE1F : 1; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE3M : 2; + unsigned short POE2M : 2; + unsigned short POE1M : 2; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CH34HIZ : 1; + unsigned char CH0HIZ : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CH0HIZ : 1; + unsigned char CH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PE0ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE3ZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PE3ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE0ZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char P3CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P1CZEA : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char P1CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P3CZEA : 1; + unsigned char : 4; +#endif + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 9; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 9; +#endif + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PSEL6 : 1; + unsigned char PSEL7 : 1; +#else + unsigned char PSEL7 : 1; + unsigned char PSEL6 : 1; + unsigned char : 6; +#endif + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 5; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 5; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PIDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PMR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char TMWE : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char TMWE : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + } TMOCNTL; + }; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + } TMOCNTU; + }; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + char wk12[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; +}; + +struct st_rtcb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + char wk3[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + char wk9[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short ADHSC : 1; + unsigned short : 1; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 1; + unsigned short ADHSC : 1; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; +// struct { +// unsigned short ANSA:16; +// } BIT; + } ADANSA; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ANSA1:1; +// } BIT; + } ADANSA1; + union { + unsigned short WORD; +// struct { +// unsigned short ADS:16; +// } BIT; + } ADADS; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ADS1:1; +// } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ADC : 2; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short : 9; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 9; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 4; + unsigned short : 4; + unsigned short TRSA : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short TRSA : 4; + unsigned short : 4; + unsigned short TRSB : 4; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSS : 1; + unsigned short OCS : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short OCS : 1; + unsigned short TSS : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; +// struct { +// unsigned short ANSB:16; +// } BIT; + } ADANSB; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ANSB1:1; +// } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + char wk2[2]; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + char wk3[10]; + unsigned short ADDR21; + char wk4[20]; + unsigned char ADSSTR0; + unsigned char ADSSTRL; + char wk5[14]; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + char wk6[1]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + char wk7[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HVREFDIS : 1; + unsigned char OCSVSEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char OCSVSEL : 1; + unsigned char HVREFDIS : 1; +#endif + } BIT; + } ADHVREFCNT; + char wk8[3]; + unsigned char ADSSTR21; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char : 3; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 3; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 3; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 3; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char : 3; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 3; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 3; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 3; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + char wk0[18]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char : 3; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 3; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REN : 1; + unsigned long TEN : 1; + unsigned long : 1; + unsigned long MUEN : 1; + unsigned long CKDV : 4; + unsigned long DEL : 1; + unsigned long PDTA : 1; + unsigned long SDTA : 1; + unsigned long SPDP : 1; + unsigned long SWSP : 1; + unsigned long SCKP : 1; + unsigned long SWSD : 1; + unsigned long SCKD : 1; + unsigned long SWL : 3; + unsigned long DWL : 3; + unsigned long CHNL : 2; + unsigned long : 1; + unsigned long IIEN : 1; + unsigned long ROIEN : 1; + unsigned long RUIEN : 1; + unsigned long TOIEN : 1; + unsigned long TUIEN : 1; + unsigned long CKS : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CKS : 1; + unsigned long TUIEN : 1; + unsigned long TOIEN : 1; + unsigned long RUIEN : 1; + unsigned long ROIEN : 1; + unsigned long IIEN : 1; + unsigned long : 1; + unsigned long CHNL : 2; + unsigned long DWL : 3; + unsigned long SWL : 3; + unsigned long SCKD : 1; + unsigned long SWSD : 1; + unsigned long SCKP : 1; + unsigned long SWSP : 1; + unsigned long SPDP : 1; + unsigned long SDTA : 1; + unsigned long PDTA : 1; + unsigned long DEL : 1; + unsigned long CKDV : 4; + unsigned long MUEN : 1; + unsigned long : 1; + unsigned long TEN : 1; + unsigned long REN : 1; +#endif + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IDST : 1; + unsigned long RSWNO : 1; + unsigned long RCHNO : 2; + unsigned long TSWNO : 1; + unsigned long TCHNO : 2; + unsigned long : 18; + unsigned long IIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long TUIRQ : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long IIRQ : 1; + unsigned long : 18; + unsigned long TCHNO : 2; + unsigned long TSWNO : 1; + unsigned long RCHNO : 2; + unsigned long RSWNO : 1; + unsigned long IDST : 1; +#endif + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFRST : 1; + unsigned long TFRST : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; + unsigned long RTRG : 2; + unsigned long TTRG : 2; + unsigned long : 8; + unsigned long SSIRST : 1; + unsigned long : 14; + unsigned long AUCKE : 1; +#else + unsigned long AUCKE : 1; + unsigned long : 14; + unsigned long SSIRST : 1; + unsigned long : 8; + unsigned long TTRG : 2; + unsigned long RTRG : 2; + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long TFRST : 1; + unsigned long RFRST : 1; +#endif + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDF : 1; + unsigned long : 7; + unsigned long RDC : 4; + unsigned long : 4; + unsigned long TDE : 1; + unsigned long : 7; + unsigned long TDC : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TDC : 4; + unsigned long : 7; + unsigned long TDE : 1; + unsigned long : 4; + unsigned long RDC : 4; + unsigned long : 7; + unsigned long RDF : 1; +#endif + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long CONT : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CONT : 1; + unsigned long : 8; +#endif + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short : 15; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 4; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA18 : 1; + unsigned long : 9; + unsigned long MSTPA28 : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long MSTPA28 : 1; + unsigned long : 9; + unsigned long MSTPA18 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long : 4; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 2; + unsigned long MSTPB29 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB29 : 1; + unsigned long : 2; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 18; + unsigned long MSTPC19 : 1; + unsigned long MSTPC20 : 1; + unsigned long : 5; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long : 3; + unsigned long DSLPE : 1; +#else + unsigned long DSLPE : 1; + unsigned long : 3; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 5; + unsigned long MSTPC20 : 1; + unsigned long MSTPC19 : 1; + unsigned long : 18; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long MSTPD10 : 1; + unsigned long MSTPD11 : 1; + unsigned long : 3; + unsigned long MSTPD15 : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MSTPD15 : 1; + unsigned long : 3; + unsigned long MSTPD11 : 1; + unsigned long MSTPD10 : 1; + unsigned long : 10; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long : 4; + unsigned long PCKB : 4; + unsigned long : 12; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long : 12; + unsigned long PCKB : 4; + unsigned long : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 6; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 6; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short UPLIDIV : 2; + unsigned short : 2; + unsigned short UCKUPLLSEL : 1; + unsigned short : 3; + unsigned short USTC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short USTC : 6; + unsigned short : 3; + unsigned short UCKUPLLSEL : 1; + unsigned short : 2; + unsigned short UPLIDIV : 2; +#endif + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UPLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char UPLLEN : 1; +#endif + } BIT; + } UPLLCR2; + char wk5[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + char wk6[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char : 1; + unsigned char UPLOVF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char UPLOVF : 1; + unsigned char : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 3; + unsigned short : 1; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short : 1; + unsigned short CKOSEL : 3; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk8[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCDSCLKSEL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LCDSCLKSEL : 3; +#endif + } BIT; + } LCDSCLKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCDSCLKSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCDSCLKSTP : 1; +#endif + } BIT; + } LCDSCLKCR2; + char wk9[78]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MSTS : 5; +#endif + } BIT; + } MOSCWTCR; + char wk10[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char HSTS : 5; +#endif + } BIT; + } HOCOWTCR; + char wk11[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOPCM : 1; + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; + unsigned char SOPCM : 1; +#endif + } BIT; + } SOPCCR; + char wk12[21]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk13[1]; + unsigned short SWRR; + char wk14[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk15[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short PRC2 : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short PRC2 : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk16[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk17[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char MODRV21 : 1; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV21 : 1; + unsigned char : 5; +#endif + } BIT; + } MOFCR; + char wk18[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char EXVCCINP2 : 1; + unsigned char : 1; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 1; + unsigned char EXVCCINP2 : 1; + unsigned char : 3; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2LVL : 2; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 3; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char : 3; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 3; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char : 3; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; +}; + +struct st_temps { + unsigned char TSCDRL; + unsigned char TSCDRH; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBE : 1; + unsigned short : 2; + unsigned short DMRPU : 1; + unsigned short DPRPU : 1; + unsigned short DRPD : 1; + unsigned short DCFM : 1; + unsigned short : 1; + unsigned short CNEN : 1; + unsigned short : 1; + unsigned short SCKE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SCKE : 1; + unsigned short : 1; + unsigned short CNEN : 1; + unsigned short : 1; + unsigned short DCFM : 1; + unsigned short DRPD : 1; + unsigned short DPRPU : 1; + unsigned short DMRPU : 1; + unsigned short : 2; + unsigned short USBE : 1; +#endif + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 3; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short : 3; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RHST : 3; + unsigned short : 1; + unsigned short UACT : 1; + unsigned short RESUME : 1; + unsigned short USBRST : 1; + unsigned short RWUPE : 1; + unsigned short WKUP : 1; + unsigned short VBUSEN : 1; + unsigned short EXICEN : 1; + unsigned short HNPBTOA : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short HNPBTOA : 1; + unsigned short EXICEN : 1; + unsigned short VBUSEN : 1; + unsigned short WKUP : 1; + unsigned short RWUPE : 1; + unsigned short USBRST : 1; + unsigned short RESUME : 1; + unsigned short UACT : 1; + unsigned short : 1; + unsigned short RHST : 3; +#endif + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 1; + unsigned short ISEL : 1; + unsigned short : 2; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 3; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short : 3; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 2; + unsigned short ISEL : 1; + unsigned short : 1; + unsigned short CURPIPE : 4; +#endif + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 4; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short DREQE : 1; + unsigned short DCLRM : 1; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short DCLRM : 1; + unsigned short DREQE : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 4; + unsigned short CURPIPE : 4; +#endif + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 4; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short DREQE : 1; + unsigned short DCLRM : 1; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short DCLRM : 1; + unsigned short DREQE : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 4; + unsigned short CURPIPE : 4; +#endif + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short BRDYE : 1; + unsigned short NRDYE : 1; + unsigned short BEMPE : 1; + unsigned short CTRE : 1; + unsigned short DVSE : 1; + unsigned short SOFE : 1; + unsigned short RSME : 1; + unsigned short VBSE : 1; +#else + unsigned short VBSE : 1; + unsigned short RSME : 1; + unsigned short SOFE : 1; + unsigned short DVSE : 1; + unsigned short CTRE : 1; + unsigned short BEMPE : 1; + unsigned short NRDYE : 1; + unsigned short BRDYE : 1; + unsigned short : 8; +#endif + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PDDETINTE0 : 1; + unsigned short : 3; + unsigned short SACKE : 1; + unsigned short SIGNE : 1; + unsigned short EOFERRE : 1; + unsigned short : 4; + unsigned short ATTCHE : 1; + unsigned short DTCHE : 1; + unsigned short : 1; + unsigned short BCHGE : 1; + unsigned short OVRCRE : 1; +#else + unsigned short OVRCRE : 1; + unsigned short BCHGE : 1; + unsigned short : 1; + unsigned short DTCHE : 1; + unsigned short ATTCHE : 1; + unsigned short : 4; + unsigned short EOFERRE : 1; + unsigned short SIGNE : 1; + unsigned short SACKE : 1; + unsigned short : 3; + unsigned short PDDETINTE0 : 1; +#endif + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short EDGESTS : 1; + unsigned short : 1; + unsigned short BRDYM : 1; + unsigned short : 1; + unsigned short TRNENSEL : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short TRNENSEL : 1; + unsigned short : 1; + unsigned short BRDYM : 1; + unsigned short : 1; + unsigned short EDGESTS : 1; + unsigned short : 4; +#endif + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSQ : 3; + unsigned short VALID : 1; + unsigned short DVSQ : 3; + unsigned short VBSTS : 1; + unsigned short BRDY : 1; + unsigned short NRDY : 1; + unsigned short BEMP : 1; + unsigned short CTRT : 1; + unsigned short DVST : 1; + unsigned short SOFR : 1; + unsigned short RESM : 1; + unsigned short VBINT : 1; +#else + unsigned short VBINT : 1; + unsigned short RESM : 1; + unsigned short SOFR : 1; + unsigned short DVST : 1; + unsigned short CTRT : 1; + unsigned short BEMP : 1; + unsigned short NRDY : 1; + unsigned short BRDY : 1; + unsigned short VBSTS : 1; + unsigned short DVSQ : 3; + unsigned short VALID : 1; + unsigned short CTSQ : 3; +#endif + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PDDETINT0 : 1; + unsigned short : 3; + unsigned short SACK : 1; + unsigned short SIGN : 1; + unsigned short EOFERR : 1; + unsigned short : 4; + unsigned short ATTCH : 1; + unsigned short DTCH : 1; + unsigned short : 1; + unsigned short BCHG : 1; + unsigned short OVRCR : 1; +#else + unsigned short OVRCR : 1; + unsigned short BCHG : 1; + unsigned short : 1; + unsigned short DTCH : 1; + unsigned short ATTCH : 1; + unsigned short : 4; + unsigned short EOFERR : 1; + unsigned short SIGN : 1; + unsigned short SACK : 1; + unsigned short : 3; + unsigned short PDDETINT0 : 1; +#endif + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDY : 1; + unsigned short PIPE1BRDY : 1; + unsigned short PIPE2BRDY : 1; + unsigned short PIPE3BRDY : 1; + unsigned short PIPE4BRDY : 1; + unsigned short PIPE5BRDY : 1; + unsigned short PIPE6BRDY : 1; + unsigned short PIPE7BRDY : 1; + unsigned short PIPE8BRDY : 1; + unsigned short PIPE9BRDY : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDY : 1; + unsigned short PIPE8BRDY : 1; + unsigned short PIPE7BRDY : 1; + unsigned short PIPE6BRDY : 1; + unsigned short PIPE5BRDY : 1; + unsigned short PIPE4BRDY : 1; + unsigned short PIPE3BRDY : 1; + unsigned short PIPE2BRDY : 1; + unsigned short PIPE1BRDY : 1; + unsigned short PIPE0BRDY : 1; +#endif + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDY : 1; + unsigned short PIPE1NRDY : 1; + unsigned short PIPE2NRDY : 1; + unsigned short PIPE3NRDY : 1; + unsigned short PIPE4NRDY : 1; + unsigned short PIPE5NRDY : 1; + unsigned short PIPE6NRDY : 1; + unsigned short PIPE7NRDY : 1; + unsigned short PIPE8NRDY : 1; + unsigned short PIPE9NRDY : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDY : 1; + unsigned short PIPE8NRDY : 1; + unsigned short PIPE7NRDY : 1; + unsigned short PIPE6NRDY : 1; + unsigned short PIPE5NRDY : 1; + unsigned short PIPE4NRDY : 1; + unsigned short PIPE3NRDY : 1; + unsigned short PIPE2NRDY : 1; + unsigned short PIPE1NRDY : 1; + unsigned short PIPE0NRDY : 1; +#endif + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMP : 1; + unsigned short PIPE1BEMP : 1; + unsigned short PIPE2BEMP : 1; + unsigned short PIPE3BEMP : 1; + unsigned short PIPE4BEMP : 1; + unsigned short PIPE5BEMP : 1; + unsigned short PIPE6BEMP : 1; + unsigned short PIPE7BEMP : 1; + unsigned short PIPE8BEMP : 1; + unsigned short PIPE9BEMP : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMP : 1; + unsigned short PIPE8BEMP : 1; + unsigned short PIPE7BEMP : 1; + unsigned short PIPE6BEMP : 1; + unsigned short PIPE5BEMP : 1; + unsigned short PIPE4BEMP : 1; + unsigned short PIPE3BEMP : 1; + unsigned short PIPE2BEMP : 1; + unsigned short PIPE1BEMP : 1; + unsigned short PIPE0BEMP : 1; +#endif + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FRNM : 11; + unsigned short : 3; + unsigned short CRCE : 1; + unsigned short OVRN : 1; +#else + unsigned short OVRN : 1; + unsigned short CRCE : 1; + unsigned short : 3; + unsigned short FRNM : 11; +#endif + } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short DIR : 1; + unsigned short : 2; + unsigned short SHTNAK : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SHTNAK : 1; + unsigned short : 2; + unsigned short DIR : 1; + unsigned short : 4; +#endif + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MXPS : 7; + unsigned short : 5; + unsigned short DEVSEL : 4; +#else + unsigned short DEVSEL : 4; + unsigned short : 5; + unsigned short MXPS : 7; +#endif + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short CCPL : 1; + unsigned short : 2; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short : 2; + unsigned short SUREQCLR : 1; + unsigned short : 2; + unsigned short SUREQ : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short SUREQ : 1; + unsigned short : 2; + unsigned short SUREQCLR : 1; + unsigned short : 2; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 2; + unsigned short CCPL : 1; + unsigned short PID : 2; +#endif + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPESEL : 4; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short PIPESEL : 4; +#endif + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EPNUM : 4; + unsigned short DIR : 1; + unsigned short : 2; + unsigned short SHTNAK : 1; + unsigned short : 1; + unsigned short DBLB : 1; + unsigned short BFRE : 1; + unsigned short : 3; + unsigned short TYPE : 2; +#else + unsigned short TYPE : 2; + unsigned short : 3; + unsigned short BFRE : 1; + unsigned short DBLB : 1; + unsigned short : 1; + unsigned short SHTNAK : 1; + unsigned short : 2; + unsigned short DIR : 1; + unsigned short EPNUM : 4; +#endif + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MXPS : 9; + unsigned short : 3; + unsigned short DEVSEL : 4; +#else + unsigned short DEVSEL : 4; + unsigned short : 3; + unsigned short MXPS : 9; +#endif + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IITV : 3; + unsigned short : 9; + unsigned short IFIS : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short IFIS : 1; + unsigned short : 9; + unsigned short IITV : 3; +#endif + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPDME0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDMSRCE0 : 1; + unsigned short : 1; + unsigned short BATCHGE0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short PDDETSTS0 : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PDDETSTS0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short BATCHGE0 : 1; + unsigned short : 1; + unsigned short VDMSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short RPDME0 : 1; +#endif + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VDDUSBE : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short VDDUSBE : 1; +#endif + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD5; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_DOC_DOPCF=57, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_ELC_ELSR18I=106, +IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_ELC_ELSR18I=106, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_ELC_ELSR18I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6, +IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_ELC_ELSR18I=106, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_SCI2_ERI2 IEN2 +#define IEN_SCI2_RXI2 IEN3 +#define IEN_SCI2_TXI2 IEN4 +#define IEN_SCI2_TEI2 IEN5 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_ELC_ELSR18I 106 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_SCI2_ERI2 186 +#define VECT_SCI2_RXI2 187 +#define VECT_SCI2_TXI2 188 +#define VECT_SCI2_TEI2 189 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CMPB (*(volatile struct st_cmpb *)0x8C580) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CRC (*(volatile struct st_crc *)0x88280) +#define CTSU (*(volatile struct st_ctsu *)0xA0900) +#define DA (*(volatile struct st_da *)0x88040) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x7FC090) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IRDA (*(volatile struct st_irda *)0x88410) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define LCDC (*(volatile struct st_lcdc *)0xA0800) +#define LPT (*(volatile struct st_lpt *)0x800B0) +#define MPC (*(volatile struct st_mpc *)0x8C11F) +#define MTU (*(volatile struct st_mtu *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 *)0x88690) +#define MTU1 (*(volatile struct st_mtu1 *)0x88690) +#define MTU2 (*(volatile struct st_mtu2 *)0x88692) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88694) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT (*(volatile struct st_port *)0x8C121) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTH (*(volatile struct st_porth *)0x8C051) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define RTCB (*(volatile struct st_rtcb *)0x8C402) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 *)0x8A040) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SMCI0 (*(volatile struct st_smci *)0x8A000) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI2 (*(volatile struct st_smci *)0x8A040) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI8 (*(volatile struct st_smci *)0x8A100) +#define SMCI9 (*(volatile struct st_smci *)0x8A120) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SSI0 (*(volatile struct st_ssi *)0x8A500) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x7FC0AC) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) + +#pragma pack() +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c new file mode 100644 index 000000000..4e39c6d07 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c @@ -0,0 +1,258 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +#include "r_rsk_async.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set up SCI1 receive buffer */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* Enable SCI1 operations */ + R_SCI1_Start(); + + LED0 = LED_OFF; + LED1 = LED_OFF; + LED2 = LED_OFF; + LED3 = LED_OFF; +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/rskrx113def.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/rskrx113def.h new file mode 100644 index 000000000..cd001d24a --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/rskrx113def.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rskrx113def.h +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* H/W Platform : RSKRX113 +* Description : Defines macros relating to the RSK user LEDs and switches +* Creation Date: 26/08/2014 +*******************************************************************************/ + + +#ifndef RSKRX113_H +#define RSKRX113_H + +/******************************************************************************* +User Defines +*******************************************************************************/ +/* General Values */ +#define LED_ON (0) +#define LED_OFF (1) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Switches */ +#define SW1 (PORTJ.PIDR.BIT.B0) +#define SW2 (PORT3.PIDR.BIT.B2) +#define SW3 (PORT2.PIDR.BIT.B7) + +/* LED port settings */ +#define LED0 (PORT2.PODR.BIT.B2) +#define LED1 (PORT2.PODR.BIT.B3) +#define LED2 (PORT2.PODR.BIT.B4) +#define LED3 (PORT2.PODR.BIT.B5) + + +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.HardwareDebuglinker new file mode 100644 index 000000000..159f1e209 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.HardwareDebuglinker @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.Releaselinker b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.Releaselinker new file mode 100644 index 000000000..cbc3b44af --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.Releaselinker @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.cproject b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.cproject new file mode 100644 index 000000000..325ef5b13 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.cproject @@ -0,0 +1,194 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.info b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.info new file mode 100644 index 000000000..69656f398 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.info @@ -0,0 +1,6 @@ +TOOL_CHAIN=Renesas RXC Toolchain +VERSION=v2.03.00 +TC_INSTALL=C:\devtools\Renesas\RX\2_3_0\ +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.project b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.project new file mode 100644 index 000000000..648ae6b1f --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442828545389 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442828574901 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442828574911 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Renesas + + + + 1442838201321 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442838201326 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442838201332 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442838201337 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442838201342 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442838201347 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442838201353 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442838201358 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442838201363 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442838201367 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442838201373 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442838201377 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442838201382 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442838201387 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442838201391 + 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b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..e78951892 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo Release.launch b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo Release.launch new file mode 100644 index 000000000..7364a96f6 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/RTOSDemo Release.launch @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/custom.bat b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/makefile.init b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/makefile.init new file mode 100644 index 000000000..6e9134b91 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/makefile.init @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +export INC_RX=C:\devtools\Renesas\RX\2_3_0\include +export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin +export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin +PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..9ad0a7a61 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,235 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h new file mode 100644 index 000000000..94e4d45e0 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -0,0 +1,161 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Hardware specifics. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */ +#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 + +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros +allow the application writer to add additional code before and after the MCU is +placed into the low power state respectively. The implementations provided in +this demo can be extended to save even more power - for example the analog +input used by the low power demo could be switched off in the pre-sleep macro +and back on again in the post sleep macro. */ +void vPreSleepProcessing( unsigned long xExpectedIdleTime ); +void vPostSleepProcessing( unsigned long xExpectedIdleTime ); +#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime ); +#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime ); + +/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral +that generates the tick interrupt. */ +#define configTICK_VECTOR VECT_CMT0_CMI0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..e7dffe6e3 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,162 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2407UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0)) +void r_tmr_cmia0_interrupt( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2)) +void r_tmr_cmia2_interrupt( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c new file mode 100644 index 000000000..859a90cac --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -0,0 +1,665 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.c new file mode 100644 index 000000000..f553edea2 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.c @@ -0,0 +1,112 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + *******************************************************************************/ +/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */ +/******************************************************************************* + * File Name : r_rsk_async.c + * Version : 1.00 + * Device(s) : R5F51138AxFP + * Tool-Chain : CCRX + * H/W Platform : RSKRX113 + * Description : Functions used to send data via the SCI in asynchronous mode + *******************************************************************************/ +/******************************************************************************* + * History : 26.08.2014 Ver. 1.00 First Release + *******************************************************************************/ + +/******************************************************************************* + System Includes + *******************************************************************************/ +/* Following header file provides string type definitions. */ +#include + +/******************************************************************************* + User Includes (Project Level Includes) + *******************************************************************************/ +/* Defines port registers */ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +#include "r_rsk_async.h" + +/******************************************************************************* + User Defines + *******************************************************************************/ + +/******************************************************************************* + * Global Variables + *******************************************************************************/ + +/* Declaration of the command string to clear the terminal screen */ +static const char cmd_clr_scr[] = +{ 27, 91, 50, 74, 0, 27, 91, 72, 0 }; + +/******************************************************************************* + * Function Prototypes + *******************************************************************************/ + +/* text_write function prototype */ +static void text_write (const char * const msg_string); + +/******************************************************************************* + * Function Name: R_ASYNC_Init + * Description : This function initialises the SCI channel connected to the + * RS232 connector on the RSK. The channel is configured for + * transmission and reception, and instructions are sent to the + * terminal. + * Argument : none + * Return value : none + *******************************************************************************/ +void R_ASYNC_Init (void) +{ + + /* Set up SCI1 receive buffer */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* Enable SCI1 operations */ + R_SCI1_Start(); + + /* Clear the text on terminal window */ + text_write(cmd_clr_scr); + + /* Display splash screen on terminal window */ + text_write("Renesas RSKRX113 Async Serial \r\n"); + + /* Inform user on how to stop transmission */ + text_write("Press 'z' to stop and any key to resume\r\n\n"); +} +/******************************************************************************* + * End of function R_ASYNC_Init + *******************************************************************************/ + +/******************************************************************************* + * Function Name : text_write + * Description : Transmits null-terminated string. + * Argument : (char*) msg_string - null terminated string + * Return value : None + *******************************************************************************/ +static void text_write (const char * const msg_string) +{ + R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string)); +} +/******************************************************************************* + * End of function text_write + *******************************************************************************/ + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.h new file mode 100644 index 000000000..ffcadfe36 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/Renesas_Code/r_rsk_async.h @@ -0,0 +1,50 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + *******************************************************************************/ +/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */ +/******************************************************************************* + * File Name : r_rsk_async.h + * Version : 1.00 + * Device(s) : R5F51138AxFP + * Tool-Chain : CCRX + * H/W Platform : RSKRX113 + * Description : Functions used to send data via the SCI in asynchronous mode + ******************************************************************************/ +/******************************************************************************* + * History : 26.08.2014 Ver. 1.00 First Release + *******************************************************************************/ + +/******************************************************************************* + * Macro Definitions + *******************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RSK_ASYNC_H +#define R_RSK_ASYNC_H + +/******************************************************************************* + * Global Function Prototypes + *******************************************************************************/ +/* initialise asynchronous transmission*/ +void R_ASYNC_Init (void); + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..431e14071 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c @@ -0,0 +1,131 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + uint32_t w_count; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | + _00000000_CGC_FCLK_DIV_1; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Stop sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Stop sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Wait for 5 sub-clock cycles */ + for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++) + { + nop(); + } + + /* Set sub-clock drive capacity */ + RTC.RCR3.BIT.RTCDV = 1U; + + /* Wait for the register modification to complete */ + while (1U != RTC.RCR3.BIT.RTCDV); + + /* Set sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 0U; + + /* Wait for the register modification to complete */ + while (0U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Wait for sub-clock to be stable */ + for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++) + { + nop(); + } + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..6a32749c4 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */ + +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + HOCO Wait Control Register (HOCOWTCR) +*/ +/* HOCO Wait Time (HOCOWTCR) */ +#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */ +#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + LCD Source Clock Control Register (LCDSCLKCR) +*/ +/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */ +#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */ +#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */ +#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */ +#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */ +#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */ +#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..da709aa9b --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c new file mode 100644 index 000000000..7693dc35b --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_dbsct.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W"), + __sectop("L"), __sectop("SU"), + __sectop("C$DSEC"), __sectop("C$BSEC"), + __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT") +}; + +#pragma packoption + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..90e9f5265 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,101 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_port.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Initialize non-existent pins */ + PORT0.PDR.BYTE = 0x6BU; + PORT3.PDR.BYTE = 0xD8U; + PORT4.PDR.BYTE = 0xA0U; + PORT5.PDR.BYTE = 0x80U; + PORT9.PDR.BYTE = 0xF8U; + PORTD.PDR.BYTE = 0xE0U; + PORTF.PDR.BYTE = 0x3FU; + PORTJ.PDR.BYTE = 0x32U; + + /* Set peripheral settings */ + R_CGC_Create(); + R_PORT_Create(); + R_SCI1_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c new file mode 100644 index 000000000..0c6e5a7f3 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_intprg.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section IntPRG + +/* Undefined exceptions for supervisor instruction, undefined instruction and floating point exceptions */ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Reserved */ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* NMI */ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* BRK */ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..267da9802 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +/* BRK handler command options */ +typedef enum { + BRK_NO_COMMAND, + BRK_ALL_MODULE_CLOCK_STOP, + BRK_SLEEP, + BRK_DEEP_SLEEP, + BRK_STANDBY, + BRK_LOAD_FINTV_REGISTER +} brk_commands; +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #define __int8_t_defined + typedef signed char int8_t; + typedef signed short int16_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.c new file mode 100644 index 000000000..4a893345a --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.c @@ -0,0 +1,65 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | + _00_Pm7_MODE_INPUT; + PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT; + PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.h new file mode 100644 index 000000000..f331d6cf8 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Direction Register (PDR) +*/ +/* Pmn Direction Control (B7 - B0) */ +#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */ +#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */ +#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */ +#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */ +#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */ +#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */ +#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */ +#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */ +#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */ +#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */ +#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */ +#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */ +#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */ +#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */ +#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */ +#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */ +#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */ +#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */ +#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */ +#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */ +#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */ +#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */ +#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */ +#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */ + +/* + Port Output Data Register (PODR) +*/ +/* Pmn Output Data Store (B7 - B0) */ +#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */ +#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */ +#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */ +#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */ +#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */ +#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */ +#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */ +#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */ +#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */ +#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */ +#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */ +#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */ +#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */ +#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */ +#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */ +#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */ + +/* + Open Drain Control Register 0 (ODR0) +*/ +/* Pmn Output Type Select (Pm0 to Pm3) */ +#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */ +#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */ +#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */ +#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */ +#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */ +#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */ +#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */ +#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */ + +/* + Open Drain Control Register 1 (ODR1) +*/ +/* Pmn Output Type Select (Pm4 to Pm7) */ +#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */ +#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */ +#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */ +#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */ +#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */ +#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */ +#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */ +#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */ + +/* + Pull-Up Control Register (PCR) +*/ +/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */ +#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */ +#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */ +#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */ +#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */ +#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */ +#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */ +#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */ +#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */ +#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */ +#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */ +#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */ +#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */ +#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */ +#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */ +#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */ +#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */ + +/* + Port Switching Register A (PSRA) +*/ +/* PB6/PC0 Switching (PSEL6) */ +#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */ +#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */ +/* PB7/PC1 Switching (PSEL7) */ +#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */ +#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */ +#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */ +#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */ +#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */ +#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */ +#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */ +#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */ +#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c new file mode 100644 index 000000000..0239dde20 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c new file mode 100644 index 000000000..34c143eec --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_resetprg.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Reset program. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "r_cg_stacksct.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 /* PSW bit pattern */ +#define FPSW_init 0x00000000 /* FPSW bit base pattern */ + +#pragma section ResetPRG /* output PowerON_Reset to PResetPRG section */ + +#pragma entry PowerON_Reset + +void PowerON_Reset(void) +{ + set_intb(__sectop("C$VECT")); + + _INITSCT(); /* Initialize Sections */ + HardwareSetup(); /* Use Hardware Setup */ + nop(); + set_psw(PSW_init); /* Set Ubit & Ibit for PSW */ + main(); + brk(); +} +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..823d383ec --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..9840cd1ba --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c new file mode 100644 index 000000000..761f53ca5 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */ +uint16_t g_sci1_tx_count; /* SCI1 transmit data number */ +uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */ +uint16_t g_sci1_rx_count; /* SCI1 receive data number */ +uint16_t g_sci1_rx_length; /* SCI1 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_SCI1_Create +* Description : This function initializes the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Create(void) +{ + /* Cancel SCI1 module stop state */ + MSTP(SCI1) = 0U; + + /* Set interrupt priority */ + IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15; + + /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */ + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.RIE = 0U; + SCI1.SCR.BIT.TE = 0U; + SCI1.SCR.BIT.RE = 0U; + SCI1.SCR.BIT.TEIE = 0U; + + /* Set RXD1 pin */ + MPC.P15PFS.BYTE = 0x0AU; + PORT1.PMR.BYTE |= 0x20U; + /* Set TXD1 pin */ + MPC.P16PFS.BYTE = 0x0AU; + PORT1.PODR.BYTE |= 0x40U; + PORT1.PDR.BYTE |= 0x40U; + PORT1.PMR.BYTE |= 0x40U; + + /* Set clock enable */ + SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + + /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */ + SCI1.SIMR1.BIT.IICM = 0U; + SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; + + /* Set control registers */ + SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; + SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT; + + /* Set SEMR, SNFR */ + SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK; + + /* Set bitrate */ + SCI1.BRR = 0x19U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Start +* Description : This function starts the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Start(void) +{ + IR(SCI1,TXI1) = 0U; + IR(SCI1,TEI1) = 0U; + IR(SCI1,RXI1) = 0U; + IR(SCI1,ERI1) = 0U; + IEN(SCI1,TXI1) = 1U; + IEN(SCI1,TEI1) = 1U; + IEN(SCI1,RXI1) = 1U; + IEN(SCI1,ERI1) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Stop +* Description : This function stops the SCI1. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI1_Stop(void) +{ + /* Set TXD1 pin */ + PORT1.PMR.BYTE &= 0xBFU; + + SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */ + SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */ + SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */ + IR(SCI1,TXI1) = 0U; + IEN(SCI1,TXI1) = 0U; + IR(SCI1,TEI1) = 0U; + IEN(SCI1,TEI1) = 0U; + IR(SCI1,RXI1) = 0U; + IEN(SCI1,RXI1) = 0U; + IR(SCI1,ERI1) = 0U; + IEN(SCI1,ERI1) = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Serial_Receive +* Description : This function receives SCI1 data. +* Arguments : rx_buf - +* receive buffer pointer (Not used when receive data handled by DTC) +* rx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + MD_STATUS status = MD_OK; + + if (rx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + g_sci1_rx_count = 0U; + g_sci1_rx_length = rx_num; + gp_sci1_rx_address = rx_buf; + SCI1.SCR.BIT.RIE = 1U; + SCI1.SCR.BIT.RE = 1U; + } + + return (status); +} +/*********************************************************************************************************************** +* Function Name: R_SCI1_Serial_Send +* Description : This function transmits SCI1 data. +* Arguments : tx_buf - +* transfer buffer pointer (Not used when transmit data handled by DTC) +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (tx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + gp_sci1_tx_address = tx_buf; + g_sci1_tx_count = tx_num; + /* Set TXD1 pin */ + PORT1.PMR.BYTE |= 0x40U; + SCI1.SCR.BIT.TIE = 1U; + SCI1.SCR.BIT.TE = 1U; + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h new file mode 100644 index 000000000..e71ca6b83 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h @@ -0,0 +1,307 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef SCI_H +#define SCI_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* + Serial mode register (SMR) +*/ +/* Clock select (CKS) */ +#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */ +#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */ +#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */ +#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */ +/* Multi-processor Mode (MP) */ +#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */ +#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */ +/* Stop bit length (STOP) */ +#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */ +#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */ +/* Parity mode (PM) */ +#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */ +#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */ +/* Parity enable (PE) */ +#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */ +#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */ +/* Character length (CHR) */ +#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */ +#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */ +/* Communications mode (CM) */ +#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */ +#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */ +/* Base clock pulse (BCP) */ +#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */ +#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */ +#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */ +#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */ +/* Block transfer mode (BLK) */ +#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */ +#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */ +/* GSM mode (GSM) */ +#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */ +#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */ + +/* + Serial control register (SCR) +*/ +/* Clock enable (CKE) */ +#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */ +#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */ +#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */ +#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */ +/* Transmit end interrupt enable (TEIE) */ +#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */ +#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */ +/* Multi-processor interrupt enable (MPIE) */ +#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */ +#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */ +/* Receive enable (RE) */ +#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */ +#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */ +/* Transmit enable (TE) */ +#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */ +#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */ +/* Receive interrupt enable (RIE) */ +#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */ +#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */ +/* Transmit interrupt enable (TIE) */ +#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */ +#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */ + +/* + Serial status register (SSR) +*/ +/* Multi-Processor bit transfer (MPBT) */ +#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */ +#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */ +/* Multi-Processor (MPB) */ +#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */ +#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */ +/* Transmit end flag (TEND) */ +#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */ +#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */ +/* Parity error flag (PER) */ +#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */ +/* Framing error flag (FER) */ +#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */ +/* Overrun error flag (ORER) */ +#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */ + +/* + Smart card mode register (SCMR) +*/ +/* Smart card interface mode select (SMIF) */ +#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */ +#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */ +/* Transmitted / received data invert (SINV) */ +#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */ +#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */ +/* Transmitted / received data transfer direction (SDIR) */ +#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */ +#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */ +/* Base clock pulse 2 (BCP2) */ +#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */ +#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */ +#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */ + +/* + Serial extended mode register (SEMR) +*/ +/* Asynchronous Mode Clock Source Select (ACS0) */ +#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */ +#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */ +/* Asynchronous mode base clock select (ABCS) */ +#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */ +#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ +/* Digital noise filter function enable (NFEN) */ +#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */ +#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */ +/* Asynchronous start bit edge detections select (RXDESEL) */ +#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */ +#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */ + +/* + Noise filter setting register (SNFR) +*/ +/* Noise filter clock select (NFCS) */ +#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */ +#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */ +#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */ +#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */ +#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */ + +/* + I2C mode register 1 (SIMR1) +*/ +/* Simple IIC mode select (IICM) */ +#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */ +#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */ + +/* + I2C mode register 2 (SIMR2) +*/ +/* IIC interrupt mode select (IICINTM) */ +#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */ +#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */ +/* Clock synchronization (IICCSC) */ +#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */ +#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */ +/* ACK transmission data (IICACKT) */ +#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */ +#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */ + +/* + I2C mode register 3 (SIMR3) +*/ +/* Start condition generation (IICSTAREQ) */ +#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */ +#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */ +/* Restart condition generation (IICRSTAREQ) */ +#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */ +#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */ +/* Stop condition generation (IICSTPREQ) */ +#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */ +#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */ +/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */ +#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */ +#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */ +/* SSDA output select (IICSDAS) */ +#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */ +#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */ +#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */ +#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */ +/* SSCL output select (IICSCLS) */ +#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */ +#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */ +#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */ +#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */ + +/* + I2C status register (SISR) +*/ +/* ACK reception data flag (IICACKR) */ +#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */ +#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */ + +/* + SPI mode register (SPMR) +*/ +/* SS pin function enable (SSE) */ +#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */ +#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */ +/* CTS enable (CTSE) */ +#define _00_SCI_RTS (0x00U) /* RTS function is enabled */ +#define _02_SCI_CTS (0x02U) /* CTS function is disabled */ +/* Master slave select (MSS) */ +#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */ +#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */ +/* Mode fault flag (MFF) */ +#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */ +#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */ +/* Clock polarity select (CKPOL) */ +#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */ +#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */ +/* Clock phase select (CKPH) */ +#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */ +#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Transfer status control value +*/ +/* Simple IIC Transmit Receive Flag */ +#define _80_SCI_IIC_TRANSMISSION (0x80U) +#define _00_SCI_IIC_RECEPTION (0x00U) +/* Simple IIC Start Stop Flag */ +#define _80_SCI_IIC_START_CYCLE (0x80U) +#define _00_SCI_IIC_STOP_CYCLE (0x00U) +/* Multiprocessor Asynchronous Communication Flag */ +#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U) +#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U) + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_SCI1_Create(void); +void R_SCI1_Start(void); +void R_SCI1_Stop(void); +MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num); +MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num); +static void r_sci1_callback_transmitend(void); +static void r_sci1_callback_receiveend(void); +static void r_sci1_callback_receiveerror(void); + +/* Start user code for function. Do not edit comment generated here */ + +/* Some of the code in this file is generated using "Code Generator" for e2 studio. + * Warnings exist in this module. */ + +/* Exported functions used to transmit a number of bytes and wait for completion */ +MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num); + +/* Character is used to receive key presses from PC terminal */ +extern uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +extern volatile uint8_t g_tx_flag; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c new file mode 100644 index 000000000..aec0de101 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +#include "rskrx113def.h" +//_RB_#include "r_cg_cmt.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */ +extern uint16_t g_sci1_tx_count; /* SCI1 send data number */ +extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */ +extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */ +extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */ +/* Start user code for global. Do not edit comment generated here */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci1_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci1_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1 +#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint) +#else +#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1)) +#endif +static void r_sci1_transmit_interrupt(void) +{ + if (g_sci1_tx_count > 0U) + { + SCI1.TDR = *gp_sci1_tx_address; + gp_sci1_tx_address++; + g_sci1_tx_count--; + } + else + { + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.TEIE = 1U; + } +} +/*********************************************************************************************************************** +* Function Name: r_sci1_transmitend_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1 +#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint) +#else +#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1)) +#endif +static void r_sci1_transmitend_interrupt(void) +{ + /* Set TXD1 pin */ + PORT1.PMR.BYTE &= 0xBFU; + SCI1.SCR.BIT.TIE = 0U; + SCI1.SCR.BIT.TE = 0U; + SCI1.SCR.BIT.TEIE = 0U; + + r_sci1_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci1_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1 +#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint) +#else +#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1)) +#endif +static void r_sci1_receive_interrupt(void) +{ + if (g_sci1_rx_length > g_sci1_rx_count) + { + *gp_sci1_rx_address = SCI1.RDR; + gp_sci1_rx_address++; + g_sci1_rx_count++; + + if (g_sci1_rx_length == g_sci1_rx_count) + { + r_sci1_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci1_receiveerror_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1 +#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint) +#else +#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1)) +#endif +static void r_sci1_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci1_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI1.SSR.BYTE; + SCI1.SSR.BYTE = err_type & 0xC7U; +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_transmitend +* Description : This function is a callback function when SCI1 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci1_txdone = TRUE; + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_receiveend +* Description : This function is a callback function when SCI1 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if ('z' == g_rx_char) + { + /* Stop the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT0_Stop(); + + /* Turn off LED0 and turn on LED1 to indicate serial transmission + inactive */ + LED0 = LED_OFF; + LED1 = LED_ON; + } + else + { + /* Start the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT0_Start(); + + /* Turn on LED0 and turn off LED1 to indicate serial transmission + active */ + LED0 = LED_ON; + LED1 = LED_OFF; + } + + /* Set up SCI1 receive buffer again */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci1_callback_receiveerror +* Description : This function is a callback function when SCI1 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci1_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/*********************************************************************************************************************** + * Function Name: R_SCI1_AsyncTransmit + * Description : This function sends SCI1 data and waits for the transmit end flag. + * Arguments : tx_buf - + * transfer buffer pointer + * tx_num - + * buffer size + * Return Value : status - + * MD_OK or MD_ARGERROR + ***********************************************************************************************************************/ +MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci1_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI1_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci1_txdone) + { + /* Wait */ + } + return (status); +} +/*********************************************************************************************************************** + * End of function R_SCI1_AsyncTransmit + ***********************************************************************************************************************/ + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h new file mode 100644 index 000000000..6545c3fe9 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_stacksct.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : Setting of Stack area. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _STACKSCT_H +#define _STACKSCT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +#pragma stacksize su=0x100 +#pragma stacksize si=0x300 + + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..d5e1b6ab8 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,40 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +#define TRUE (1) +#define FALSE (0) +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h new file mode 100644 index 000000000..393a440d9 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vect.h +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file contains definition of vector. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ +#ifndef _VECT_H +#define _VECT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Undefined */ +#pragma interrupt (r_undefined_exception) +void r_undefined_exception(void); + +/* Reserved */ +#pragma interrupt (r_reserved_exception) +void r_reserved_exception(void); + +/* NMI */ +#pragma interrupt (r_nmi_exception) +void r_nmi_exception(void); + +/* BRK */ +#pragma interrupt (r_brk_exception(vect=0)) +void r_brk_exception(void); + +/*;<> */ +/*;Power On Reset PC */ +extern void PowerON_Reset(void); +/*;<> */ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c new file mode 100644 index 000000000..f8e065dc4 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c @@ -0,0 +1,104 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vecttbl.c +* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015] +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* Description : This file initializes the vector table. +* Creation Date: 21/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section C FIXEDVECT + +void (*const Fixed_Vectors[])(void) = { +/*;0xffffffd0 Exception(Supervisor Instruction) */ + r_undefined_exception, +/*;0xffffffd4 Reserved */ + r_undefined_exception, +/*;0xffffffd8 Reserved */ + r_reserved_exception, +/*;0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, +/*;0xffffffe0 Reserved */ + r_reserved_exception, +/*;0xffffffe4 Reserved */ + r_reserved_exception, +/*;0xffffffe8 Reserved */ + r_reserved_exception, +/*;0xffffffec Reserved */ + r_reserved_exception, +/*;0xfffffff0 Reserved */ + r_reserved_exception, +/*;0xfffffff4 Reserved */ + r_reserved_exception, +/*;0xfffffff8 NMI */ + r_nmi_exception, +/*;0xfffffffc RESET */ +/*;<> */ +/*;Power On Reset PC */ + /*(void*)*/ PowerON_Reset +/*;<> */ +}; + +/* MDE register (Single Chip Mode) */ +#pragma address _MDEreg=0xffffff80 +#ifdef __BIG + /* Big endian*/ + const unsigned long _MDEreg = 0xfffffff8; +#else + /* Little endian */ + const unsigned long _MDEreg = 0xffffffff; +#endif + +/* Set option bytes */ +#pragma address OFS0_location = 0xFFFFFF8CUL +#pragma address OFS1_location = 0xFFFFFF88UL +volatile const uint32_t OFS0_location = 0xFFFFFFFFUL; +volatile const uint32_t OFS1_location = 0xFFFFFFFFUL; + +/* Start user code for adding. Do not edit comment generated here */ +/* ID codes (Default) */ +#pragma address id_code=0xffffffa0 +const unsigned long id_code[4] = { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, +}; +/* End user code. Do not edit comment generated here */ + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/iodefine.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/iodefine.h new file mode 100644 index 000000000..e84e3c2a2 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/iodefine.h @@ -0,0 +1,6701 @@ + +/********************************************************************************* +* +* Device : RX/RX100/RX113 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40] +* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50] +* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2013 (2014) Renesas Electronics Corporation and +* Renesas Solutions Corp. All rights reserved. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX113 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX113IODEFINE_HEADER__ +#define __RX113IODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short BPFB:2; + unsigned short :2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1INI:1; + unsigned char :3; + unsigned char CPB0INI:1; + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1WCP:1; + unsigned char :3; + unsigned char CPB0WCP:1; + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + unsigned char CPB1OUT:1; + unsigned char :3; + unsigned char CPB0OUT:1; + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CPB1INTPL:1; + unsigned char CPB1INTEG:1; + unsigned char CPB1INTEN:1; + unsigned char :1; + unsigned char CPB0INTPL:1; + unsigned char CPB0INTEG:1; + unsigned char CPB0INTEN:1; + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + unsigned char CPB1F:2; + unsigned char :1; + unsigned char CPB1FEN:1; + unsigned char CPB0F:2; + unsigned char :1; + unsigned char CPB0FEN:1; + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CPBSPDMD:1; + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1VRF:1; + unsigned char :3; + unsigned char CPB0VRF:1; + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CPB1OP:1; + unsigned char CPB1OE:1; + unsigned char :2; + unsigned char CPB0OP:1; + unsigned char CPB0OE:1; + } BIT; + } CPBOCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CTSUINIT:1; + unsigned char CTSUIOC:1; + unsigned char CTSUSNZ:1; + unsigned char CTSUCAP:1; + unsigned char CTSUSTRT:1; + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUMD:2; + unsigned char CTSUCLK:2; + unsigned char CTSUATUNE1:1; + unsigned char CTSUATUNE0:1; + unsigned char CTSUCSW:1; + unsigned char CTSUPON:1; + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CTSUSOFF:1; + unsigned char CTSUPRMODE:2; + unsigned char CTSUPRRATIO:4; + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + unsigned char CTSUSST:8; + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUMCH0:4; + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUMCH1:4; + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC07:1; + unsigned char CTSUCHAC06:1; + unsigned char CTSUCHAC05:1; + unsigned char CTSUCHAC04:1; + unsigned char CTSUCHAC03:1; + unsigned char CTSUCHAC02:1; + unsigned char CTSUCHAC01:1; + unsigned char CTSUCHAC00:1; + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHAC13:1; + unsigned char CTSUCHAC12:1; + unsigned char CTSUCHAC11:1; + unsigned char CTSUCHAC10:1; + } BIT; + } CTSUCHAC1; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC07:1; + unsigned char CTSUCHTRC06:1; + unsigned char CTSUCHTRC05:1; + unsigned char CTSUCHTRC04:1; + unsigned char CTSUCHTRC03:1; + unsigned char CTSUCHTRC02:1; + unsigned char CTSUCHTRC01:1; + unsigned char CTSUCHTRC00:1; + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHTRC13:1; + unsigned char CTSUCHTRC12:1; + unsigned char CTSUCHTRC11:1; + unsigned char CTSUCHTRC10:1; + } BIT; + } CTSUCHTRC1; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUSSCNT:2; + unsigned char :2; + unsigned char CTSUSSMOD:2; + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + unsigned char CTSUPS:1; + unsigned char CTSUROVF:1; + unsigned char CTSUSOVF:1; + unsigned char CTSUDTSR:1; + unsigned char :1; + unsigned char CTSUSTC:3; + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short CTSUSSDIV:4; + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + unsigned short CTSUSNUM:6; + unsigned short CTSUSO:10; + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short CTSUICOG:2; + unsigned short CTSUSDPA:5; + unsigned short CTSURICOA:8; + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + unsigned short CTSUSC:16; + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + unsigned short CTSURC:16; + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + unsigned short CTSUICOMP:1; + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char REF:3; + } BIT; + } DAVREFCR; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR[26]; + char wk0[4]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char MTU2MD:2; + unsigned char MTU1MD:2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CMT1MD:2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TMR2MD:2; + unsigned char :2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DFLEN:1; + } BIT; + } DFLCTL; + char wk0[31]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short SASMF:1; + } BIT; + } FSCMR; + unsigned short FAWSMR; + unsigned short FAWEMR; + union { + unsigned char BYTE; + struct { + unsigned char SAS:2; + unsigned char :1; + unsigned char PCKA:5; + } BIT; + } FISR; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char :4; + unsigned char CMD:3; + } BIT; + } FEXCR; + unsigned short FEAML; +// char wk1[1]; + unsigned char FEAMH; + char wk2[5]; + unsigned char FPR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PERR:1; + } BIT; + } FPSR; + unsigned short FRBL; + unsigned short FRBH; + char wk3[16058]; + union { + unsigned char BYTE; + struct { + unsigned char FMS2:1; + unsigned char LVPE:1; + unsigned char :1; + unsigned char FMS1:1; + unsigned char RPDIS:1; + unsigned char :1; + unsigned char FMS0:1; + } BIT; + } FPMCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EXS:1; + } BIT; + } FASR; + unsigned short FSARL; +// char wk4[1]; + unsigned char FSARH; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char STOP:1; + unsigned char :1; + unsigned char DRC:1; + unsigned char CMD:4; + } BIT; + } FCR; + unsigned short FEARL; + unsigned char FEARH; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRESET:1; + } BIT; + } FRESETR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char EILGLERR:1; + unsigned char ILGLERR:1; + unsigned char BCERR:1; + unsigned char :1; + unsigned char PRGERR:1; + unsigned char ERERR:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char EXRDY:1; + unsigned char FRDY:1; + unsigned char :4; + unsigned char DRRDY:1; + } BIT; + } FSTATR1; + unsigned short FWBL; + unsigned short FWBH; + char wk5[34]; + union { + unsigned short WORD; +// struct { +// unsigned short FEKEY:8; +// unsigned short FENTRYD:1; +// unsigned short :6; +// unsigned short FENTRY0:1; +// } BIT; + } FENTRYR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[250]; + char wk0[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[249]; + char wk1[7]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[250]; + char wk5[262]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + } BIT; + } IRQCR[8]; + char wk6[8]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + char wk7[3]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + char wk8[106]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char :1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char :1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char :1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + } BIT; + } NMICR; + char wk9[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk10[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + unsigned char IRE:1; + unsigned char IRCKS:3; + unsigned char IRTXINV:1; + unsigned char IRRXINV:1; + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + } BIT; + } IWDTCSTPR; +}; + +struct st_lcdc { + union { + unsigned char BYTE; + struct { + unsigned char MDSET:2; + unsigned char LWAVE:1; + unsigned char LDTY:3; + unsigned char LBAS:2; + } BIT; + } LCDM0; + union { + unsigned char BYTE; + struct { + unsigned char LCDON:1; + unsigned char SCOC:1; + unsigned char VLCON:1; + unsigned char BLON:1; + unsigned char LCDSEL:1; + unsigned char :2; + unsigned char LCDVLM:1; + } BIT; + } LCDM1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LCDC0:6; + } BIT; + } LCDC0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char VLCD:5; + } BIT; + } VLCD; + char wk0[60]; + unsigned char SEG00; + unsigned char SEG01; + unsigned char SEG02; + unsigned char SEG03; + unsigned char SEG04; + unsigned char SEG05; + unsigned char SEG06; + unsigned char SEG07; + unsigned char SEG08; + unsigned char SEG09; + unsigned char SEG10; + unsigned char SEG11; + unsigned char SEG12; + unsigned char SEG13; + unsigned char SEG14; + unsigned char SEG15; + unsigned char SEG16; + unsigned char SEG17; + unsigned char SEG18; + unsigned char SEG19; + unsigned char SEG20; + unsigned char SEG21; + unsigned char SEG22; + unsigned char SEG23; + unsigned char SEG24; + unsigned char SEG25; + unsigned char SEG26; + unsigned char SEG27; + unsigned char SEG28; + unsigned char SEG29; + unsigned char SEG30; + unsigned char SEG31; + unsigned char SEG32; + unsigned char SEG33; + unsigned char SEG34; + unsigned char SEG35; + unsigned char SEG36; + unsigned char SEG37; + unsigned char SEG38; + unsigned char SEG39; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + } BIT; + } PWPR; + char wk0[34]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P02PFS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P04PFS; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P32PFS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + } BIT; + } P35PFS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P44PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P46PFS; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P56PFS; + char wk7[25]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } P92PFS; + char wk8[5]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD4PFS; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE7PFS; + char wk10[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PF6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PF7PFS; + char wk11[16]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } PJ0PFS; + char wk12[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } PJ2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PJ3PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } PJ6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + } BIT; + } PJ7PFS; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char POE3F:1; + unsigned char POE2F:1; + unsigned char POE1F:1; + unsigned char POE0F:1; + unsigned char :3; + unsigned char PIE1:1; + unsigned char POE3M:2; + unsigned char POE2M:2; + unsigned char POE1M:2; + unsigned char POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char OSF1:1; + unsigned char :5; + unsigned char OCE1:1; + unsigned char OIE1:1; + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char POE8F:1; + unsigned char :2; + unsigned char POE8E:1; + unsigned char PIE2:1; + unsigned char :6; + unsigned char POE8M:2; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char P1CZEA:1; + unsigned char P2CZEA:1; + unsigned char P3CZEA:1; + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char OSTSTF:1; + unsigned char :2; + unsigned char OSTSTE:1; + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + unsigned char PSEL7:1; + unsigned char PSEL6:1; + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :5; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :2; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + } BIT; + } PCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + } BIT; + } PIDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + } BIT; + } PMR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char TMWE:1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + } TMOCNTL; + }; + union { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + } TMOCNTU; + }; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + } BIT; + } RYRAREN; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; +}; + +struct st_rtcb { + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT0; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT3; + char wk3[7]; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT0AR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT1AR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT2AR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT3AR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT0AER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT1AER; + char wk9[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ENB:8; + } BIT; + } BCNT2AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT3AER; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :1; + unsigned short ADHSC:1; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; +// struct { +// unsigned short ANSA:16; +// } BIT; + } ADANSA; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ANSA1:1; +// } BIT; + } ADANSA1; + union { + unsigned short WORD; +// struct { +// unsigned short ADS:16; +// } BIT; + } ADADS; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ADS1:1; +// } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ADC:2; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :9; + unsigned short ACE:1; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short TRSA:4; + unsigned short :4; + unsigned short TRSB:4; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short OCS:1; + unsigned short TSS:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; +// struct { +// unsigned short ANSB:16; +// } BIT; + } ADANSB; + union { + unsigned short WORD; +// struct { +// unsigned short :10; +// unsigned short ANSB1:1; +// } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + char wk2[2]; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + char wk3[10]; + unsigned short ADDR21; + char wk4[20]; + unsigned char ADSSTR0; + unsigned char ADSSTRL; + char wk5[14]; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + char wk6[1]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + char wk7[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char OCSVSEL:1; + unsigned char HVREFDIS:1; + } BIT; + } ADHVREFCNT; + char wk8[3]; + unsigned char ADSSTR21; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char :1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char :1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + char wk0[18]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CKS:1; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long CHNL:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long SCKD:1; + unsigned long SWSD:1; + unsigned long SCKP:1; + unsigned long SWSP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :18; + unsigned long TCHNO:2; + unsigned long TSWNO:1; + unsigned long RCHNO:2; + unsigned long RSWNO:1; + unsigned long IDST:1; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :8; + unsigned long TTRG:2; + unsigned long RTRG:2; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TDC:4; + unsigned long :7; + unsigned long TDE:1; + unsigned long :4; + unsigned long RDC:4; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long CONT:1; + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long MSTPA28:1; + unsigned long :9; + unsigned long MSTPA18:1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long :4; + unsigned long MSTPA9:1; + unsigned long :3; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long :2; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long :6; + unsigned long MSTPB10:1; + unsigned long MSTPB9:1; + unsigned long :2; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long DSLPE:1; + unsigned long :3; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long :5; + unsigned long MSTPC20:1; + unsigned long MSTPC19:1; + unsigned long :18; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MSTPD15:1; + unsigned long :3; + unsigned long MSTPD11:1; + unsigned long MSTPD10:1; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long :12; + unsigned long PCKB:4; + unsigned long :4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :6; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short USTC:6; + unsigned short :3; + unsigned short UCKUPLLSEL:1; + unsigned short :2; + unsigned short UPLIDIV:2; + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char UPLLEN:1; + } BIT; + } UPLLCR2; + char wk5[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + char wk6[5]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char UPLOVF:1; + unsigned char :1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char :1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + unsigned short CKOSTP:1; + unsigned short CKODIV:3; + unsigned short :1; + unsigned short CKOSEL:3; + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk8[14]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LCDSCLKSEL:3; + } BIT; + } LCDSCLKCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCDSCLKSTP:1; + } BIT; + } LCDSCLKCR2; + char wk9[78]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MSTS:5; + } BIT; + } MOSCWTCR; + char wk10[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char HSTS:5; + } BIT; + } HOCOWTCR; + char wk11[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SOPCMTSF:1; + unsigned char :3; + unsigned char SOPCM:1; + } BIT; + } SOPCCR; + char wk12[21]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char :1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk13[1]; + unsigned short SWRR; + char wk14[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk15[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short PRC2:1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk16[48784]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char :1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk17[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV21:1; + } BIT; + } MOFCR; + char wk18[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + unsigned char :1; + unsigned char EXVCCINP2:1; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2LVL:2; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char :3; + unsigned char LVD1CMPE:1; + unsigned char :1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char :3; + unsigned char LVD2CMPE:1; + unsigned char :1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; +}; + +struct st_temps { + unsigned char TSCDRL; + unsigned char TSCDRH; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :1; + unsigned short CNEN:1; + unsigned short :1; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short DMRPU:1; + unsigned short :2; + unsigned short USBE:1; + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short :3; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :3; + unsigned short PDDETINTE0:1; + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :3; + unsigned short PDDETINT0:1; + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDY:1; + unsigned short PIPE8NRDY:1; + unsigned short PIPE7NRDY:1; + unsigned short PIPE6NRDY:1; + unsigned short PIPE5NRDY:1; + unsigned short PIPE4NRDY:1; + unsigned short PIPE3NRDY:1; + unsigned short PIPE2NRDY:1; + unsigned short PIPE1NRDY:1; + unsigned short PIPE0NRDY:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMP:1; + unsigned short PIPE8BEMP:1; + unsigned short PIPE7BEMP:1; + unsigned short PIPE6BEMP:1; + unsigned short PIPE5BEMP:1; + unsigned short PIPE4BEMP:1; + unsigned short PIPE3BEMP:1; + unsigned short PIPE2BEMP:1; + unsigned short PIPE1BEMP:1; + unsigned short PIPE0BEMP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short MXPS:9; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PDDETSTS0:1; + unsigned short CHGDETSTS0:1; + unsigned short BATCHGE0:1; + unsigned short :1; + unsigned short VDMSRCE0:1; + unsigned short IDPSINKE0:1; + unsigned short VDPSRCE0:1; + unsigned short IDMSINKE0:1; + unsigned short IDPSRCE0:1; + unsigned short RPDME0:1; + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short VDDUSBE:1; + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + } BIT; + } DEVADD5; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_DOC_DOPCF=57, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_ELC_ELSR18I=106, +IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_ELC_ELSR18I=106, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_ELC_ELSR18I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6, +IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_ELC_ELSR18I=106, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_SCI2_ERI2 IEN2 +#define IEN_SCI2_RXI2 IEN3 +#define IEN_SCI2_TXI2 IEN4 +#define IEN_SCI2_TEI2 IEN5 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_ELC_ELSR18I 106 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_SCI2_ERI2 186 +#define VECT_SCI2_RXI2 187 +#define VECT_SCI2_TXI2 188 +#define VECT_SCI2_TEI2 189 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000) +#define CMPB (*(volatile struct st_cmpb __evenaccess *)0x8C580) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define CTSU (*(volatile struct st_ctsu __evenaccess *)0xA0900) +#define DA (*(volatile struct st_da __evenaccess *)0x88040) +#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IRDA (*(volatile struct st_irda __evenaccess *)0x88410) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define LCDC (*(volatile struct st_lcdc __evenaccess *)0xA0800) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C11F) +#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694) +#define POE (*(volatile struct st_poe __evenaccess *)0x88900) +#define PORT (*(volatile struct st_port __evenaccess *)0x8C121) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F) +#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C051) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define RTCB (*(volatile struct st_rtcb __evenaccess *)0x8C402) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040) +#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0) +#define SMCI8 (*(volatile struct st_smci __evenaccess *)0x8A100) +#define SMCI9 (*(volatile struct st_smci __evenaccess *)0x8A120) +#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300) +#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPS (*(volatile struct st_temps __evenaccess *)0x7FC0AC) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#pragma bit_order +#pragma packoption +#endif diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/main.c new file mode 100644 index 000000000..4e39c6d07 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/main.c @@ -0,0 +1,258 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +/* Renesas includes. */ +#include +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +#include "r_rsk_async.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set up SCI1 receive buffer */ + R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1); + + /* Enable SCI1 operations */ + R_SCI1_Start(); + + LED0 = LED_OFF; + LED1 = LED_OFF; + LED2 = LED_OFF; + LED3 = LED_OFF; +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/rskrx113def.h b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/rskrx113def.h new file mode 100644 index 000000000..cd001d24a --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_Renesas_e2studio/src/rskrx113def.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rskrx113def.h +* Device(s) : R5F51138AxFP +* Tool-Chain : CCRX +* H/W Platform : RSKRX113 +* Description : Defines macros relating to the RSK user LEDs and switches +* Creation Date: 26/08/2014 +*******************************************************************************/ + + +#ifndef RSKRX113_H +#define RSKRX113_H + +/******************************************************************************* +User Defines +*******************************************************************************/ +/* General Values */ +#define LED_ON (0) +#define LED_OFF (1) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Switches */ +#define SW1 (PORTJ.PIDR.BIT.B0) +#define SW2 (PORT3.PIDR.BIT.B2) +#define SW3 (PORT2.PIDR.BIT.B7) + +/* LED port settings */ +#define LED0 (PORT2.PODR.BIT.B2) +#define LED1 (PORT2.PODR.BIT.B3) +#define LED2 (PORT2.PODR.BIT.B4) +#define LED3 (PORT2.PODR.BIT.B5) + + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.HardwareDebuglinker b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.HardwareDebuglinker new file mode 100644 index 000000000..d89b961f8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.HardwareDebuglinker @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject new file mode 100644 index 000000000..bc67806b2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject @@ -0,0 +1,138 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.info b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.info new file mode 100644 index 000000000..209c49b60 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.info @@ -0,0 +1,7 @@ +TOOL_CHAIN=KPIT GNURX-ELF Toolchain +VERSION=v15.01 +TC_INSTALL=C:\Program Files (x86)\KPIT\GNURXv15.01-ELF\rx-elf\rx-elf\ +GCC_STRING=4.8-GNURX_v15.01 +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project new file mode 100644 index 000000000..e1a619318 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442756186478 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442753620317 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442753620327 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1442773470090 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442773470090 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442773470100 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442773470100 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442773470110 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442773470110 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442773470120 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442773470120 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442773470130 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442773470130 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442773470140 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442773470140 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442773470150 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442773470150 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442773470160 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442753702822 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX600v2 + + + + 1442753633060 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgprojectDatas.datas b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgprojectDatas.datas new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..ffd77a7e6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,23 @@ +Library\ Generator\ Command=rx-elf-libgen +com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src"; +com.renesas.cdt.core.Compiler.option.includeFileDir.1486703917="${TCINSTALL}/rx-elf/optlibinc"; +com.renesas.cdt.core.LibraryGenerator.option.ctype=false +com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built +com.renesas.cdt.core.LibraryGenerator.option.math=false +com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized +com.renesas.cdt.core.LibraryGenerator.option.stdio=true +com.renesas.cdt.core.LibraryGenerator.option.stdlib=true +com.renesas.cdt.core.LibraryGenerator.option.string=true +com.renesas.cdt.core.Linker.option.userDefinedOptions=; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType=RX700 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.855519458=RX700 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian=Little-endian data +com.renesas.cdt.rx.HardwareDebug.Compiler.option.disableFPUInstructions=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX64M=true +com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.macroDefines=__RX_LITTLE_ENDIAN__\=1; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=true +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.883746544="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}"; +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml new file mode 100644 index 000000000..ec00737f5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..fbea6b475 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/custom.bat b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/makefile.init b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/makefile.init new file mode 100644 index 000000000..0835091e2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/makefile.init @@ -0,0 +1,5 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..dab3ec04d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,235 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h new file mode 100644 index 000000000..75141fdca --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 60000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..0da468ed3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,188 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define IPR_PERIB_INTB128 128 +#define IPR_PERIB_INTB129 129 +#define IER_PERIB_INTB128 0x10 +#define IER_PERIB_INTB129 0x10 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IR_PERIB_INTB128 128 +#define IR_PERIB_INTB129 129 + +void vIntQTimerISR0( void ) __attribute__ ((interrupt)); +void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set + priority above the kernel's priority, but below the max syscall + priority. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IEN( PERIB, INTB128 ) = 1; + + /* Ensure that the flag is set to 0, otherwise the interrupt will not be + accepted. */ + IR( PERIB, INTB128 ) = 0; + + /* Do the same for TMR2, but to vector 129. */ + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IEN( PERIB, INTB129 ) = 1; + IR( PERIB, INTB129 ) = 0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* On vector 128. */ +void vIntQTimerISR0( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +/* On vector 129. */ +void vIntQTimerISR1( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S new file mode 100644 index 000000000..310079738 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S @@ -0,0 +1,302 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #10, R1 + MVTACGU R1, A0 + MOV.L #20, R1 + MVTACGU R1, A1 + + ;/* Put a known value in each register. */ + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + ;/* Loop, checking each itteration that each register still contains the + ;expected value. */ +TestLoop1: + + ;/* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + ;/* Increment the loop counter to show this task is still getting CPU time. */ + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ;/* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #1, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #2, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #10, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #3, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #4, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #20, R15 + BNE RegTest1Error + + ;/* Restore the clobbered registers. */ + POPM R14-R15 + + ;/* Now compare each register to ensure it still contains the value that was + ;set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ;/* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop1 + +RegTest1Error: + ;/* A compare failed, just loop here so the loop counter stops incrementing + ;- causing the check task to indicate the error. */ + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #1H, R1 + MVTACGU R1, A0 + MOV.L #2H, R1 + MVTACGU R1, A1 + + ;/* Put a known value in each general purpose register. */ + MOV.L #10H, R1 + MOV.L #20H, R2 + MOV.L #30H, R3 + MOV.L #40H, R4 + MOV.L #50H, R5 + MOV.L #60H, R6 + MOV.L #70H, R7 + MOV.L #80H, R8 + MOV.L #90H, R9 + MOV.L #100H, R10 + MOV.L #110H, R11 + MOV.L #120H, R12 + MOV.L #130H, R13 + MOV.L #140H, R14 + MOV.L #150H, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + ;/* Loop, checking each itteration that each register still contains the + ;expected value. */ +TestLoop2: + + ;/* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + ;/* Increment the loop counter to show this task is still getting CPU time. */ + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #10H, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #20H, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #1H, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #30H, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #40H, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #2H, R15 + BNE RegTest1Error + + ;/* Restore the clobbered registers. */ + POPM R14-R15 + + ;/* Now compare each register to ensure it still contains the value that was + ;set before this loop was entered. */ + CMP #10H, R1 + BNE RegTest2Error + CMP #20H, R2 + BNE RegTest2Error + CMP #30H, R3 + BNE RegTest2Error + CMP #40H, R4 + BNE RegTest2Error + CMP #50H, R5 + BNE RegTest2Error + CMP #60H, R6 + BNE RegTest2Error + CMP #70H, R7 + BNE RegTest2Error + CMP #80H, R8 + BNE RegTest2Error + CMP #90H, R9 + BNE RegTest2Error + CMP #100H, R10 + BNE RegTest2Error + CMP #110H, R11 + BNE RegTest2Error + CMP #120H, R12 + BNE RegTest2Error + CMP #130H, R13 + BNE RegTest2Error + CMP #140H, R14 + BNE RegTest2Error + CMP #150H, R15 + BNE RegTest2Error + + ;/* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop2 + +RegTest2Error: + ;/* A compare failed, just loop here so the loop counter stops incrementing + ;- causing the check task to indicate the error. */ + BRA RegTest2Error + + + .END diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c new file mode 100644 index 000000000..e4edba2ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c @@ -0,0 +1,504 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +void vRegTest1Implementation( void ); +void vRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.c new file mode 100644 index 000000000..8505c6084 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.c @@ -0,0 +1,764 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.c */ +/* DESCRIPTION : Interrupt Handler */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 18/12/2014 */ +/************************************************************************/ +#include "interrupt_handlers.h" + +// Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void){/* brk(); */} + +// Exception(Access Instruction) +void INT_Excep_AccessInst(void){/* brk(); */} + +// Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void){/* brk(); */} + +// Exception(Floating Point) +void INT_Excep_FloatingPoint(void){/* brk(); */} + +// NMI +void INT_NonMaskableInterrupt(void){/* brk(); */} + +// Dummy +void Dummy(void){/* brk(); */} + +// BRK +void INT_Excep_BRK(void){ /*wait();*/ } +//;0x0000 Reserved + +//;0x0004 Reserved + +//;0x0008 Reserved + +//;0x000C Reserved + +//;0x0010 Reserved + +//;0x0014 Reserved + +//;0x0018 Reserved + +//;0x001C Reserved + +//;0x0020 Reserved + +//;0x0024 Reserved + +//;0x0028 Reserved + +//;0x002C Reserved + +//;0x0030 Reserved + +//;0x0034 Reserved + +//;0x0038 Reserved + +//;0x003C Reserved + +//;0x0040 BUSERR +void INT_Excep_BSC_BUSERR(void){ } +//;0x0044 Reserved + +//;0x0048 RAMERR +void INT_Excep_RAM_RAMERR(void){ } +//;0x004C Reserved + +//;0x0050 Reserved + +//;0x0054 FIFERR +void INT_Excep_FCU_FIFERR(void){ } +//;0x0058 Reserved + +//;0x005C FRDYI +void INT_Excep_FCU_FRDYI(void){ } +//;0x0060 Reserved + +//;0x0064 Reserved + +//;0x0068 SWINT2 +void INT_Excep_ICU_SWINT2(void){ } + +//;0x006C SWINT +void INT_Excep_ICU_SWINT(void){ } + +//;0x0070 CMI0 +void INT_Excep_CMT0_CMI0(void){ } + +//;0x0074 CMI1 +void INT_Excep_CMT1_CMI1(void){ } + +//;0x0078 CMWI0 +void INT_Excep_CMTW0_CMWI0(void){ } + +//;0x007C CMWI1 +void INT_Excep_CMTW1_CMWI1(void){ } + +//;0x0080 D0FIFO2 +void INT_Excep_USBA_D0FIFO2(void){ } + +//;0x0084 D1FIFO2 +void INT_Excep_USBA_D1FIFO2(void){ } + +//;0x0088 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void){ } + +//;0x008C D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void){ } +//;0x0090 Reserved + +//;0x0094 Reserved + +//;0x0098 SPRI0 +void INT_Excep_RSPI0_SPRI0(void){ } + +//;0x009C SPTI0 +void INT_Excep_RSPI0_SPTI0(void){ } + +//;0x00A0 SPRI1 +void INT_Excep_RSPI1_SPRI1(void){ } + +//;0x00A4 SPTI1 +void INT_Excep_RSPI1_SPTI1(void){ } + +//;0x00A8 SPRI +void INT_Excep_QSPI_SPRI(void){ } + +//;0x00AC SPTI +void INT_Excep_QSPI_SPTI(void){ } + +//;0x00B0 SBFAI +void INT_Excep_SDHI_SBFAI(void){ } + +//;0x00B4 MBFAI +void INT_Excep_MMCIF_MBFAI(void){ } + +//;0x00B8 SSITX0 +void INT_Excep_SSI0_SSITXI0(void){ } + +//;0x00BC SSIRX0 +void INT_Excep_SSI0_SSIRXI0(void){ } + +//;0x00C0 SSIRTI1 +void INT_Excep_SSI1_SSIRTI1(void){ } +//;0x00C4 Reserved + +//;0x00C8 IDEI +void INT_Excep_SRC_IDEI(void){ } + +//;0x00CC ODFI +void INT_Excep_SRC_ODFI(void){ } + +//;0x00D0 RXI0 +void INT_Excep_RIIC0_RXI0(void){ } + +//;0x00D4C TXI0 +void INT_Excep_RIIC0_TXI0(void){ } + +//;0x00D8 RXI2 +void INT_Excep_RIIC2_RXI2(void){ } + +//;0x00DC TXI2 +void INT_Excep_RIIC2_TXI2(void){ } +//;0x00E0 Reserved + +//;0x00E4 Reserved + +//;0x00E8 RXI0 +void INT_Excep_SCI0_RXI0(void){ } + +//;0x00EC TXI0 +void INT_Excep_SCI0_TXI0(void){ } + +//;0x00F0 RXI1 +void INT_Excep_SCI1_RXI1(void){ } + +//;0x00F4 TXI1 +void INT_Excep_SCI1_TXI1(void){ } + +//;0x00F8 RXI2 +void INT_Excep_SCI2_RXI2(void){ } + +//;0x00FC TXI2 +void INT_Excep_SCI2_TXI2(void){ } + +//;0x0100 IRQ0 +void INT_Excep_ICU_IRQ0(void){ } + +//;0x0104 IRQ1 +void INT_Excep_ICU_IRQ1(void){ } + +//;0x0108 IRQ2 +void INT_Excep_ICU_IRQ2(void){ } + +//;0x010C IRQ3 +void INT_Excep_ICU_IRQ3(void){ } + +//;0x0110 IRQ4 +void INT_Excep_ICU_IRQ4(void){ } + +//;0x0114 IRQ5 +void INT_Excep_ICU_IRQ5(void){ } + +//;0x0118 IRQ6 +void INT_Excep_ICU_IRQ6(void){ } + +//;0x011C IRQ7 +void INT_Excep_ICU_IRQ7(void){ } + +//;0x0120 IRQ8 +void INT_Excep_ICU_IRQ8(void){ } + +//;0x0124 IRQ9 +void INT_Excep_ICU_IRQ9(void){ } + +//;0x0128 IRQ10 +void INT_Excep_ICU_IRQ10(void){ } + +//;0x012C IRQ11 +void INT_Excep_ICU_IRQ11(void){ } + +//;0x0130 IRQ12 +void INT_Excep_ICU_IRQ12(void){ } + +//;0x0134 IRQ13 +void INT_Excep_ICU_IRQ13(void){ } + +//;0x0138 IRQ14 +void INT_Excep_ICU_IRQ14(void){ } + +//;0x013C IRQ15 +void INT_Excep_ICU_IRQ15(void){ } + +//;0x0140 RXI3 +void INT_Excep_SCI3_RXI3(void){ } + +//;0x0144 TXI3 +void INT_Excep_SCI3_TXI3(void){ } + +//;0x0148 RXI4 +void INT_Excep_SCI4_RXI4(void){ } + +//;0x014C TXI4 +void INT_Excep_SCI4_TXI4(void){ } + +//;0x0150 RXI5 +void INT_Excep_SCI5_RXI5(void){ } + +//;0x0154 TXI5 +void INT_Excep_SCI5_TXI5(void){ } + +//;0x0158 RXI6 +void INT_Excep_SCI6_RXI6(void){ } + +//;0x015C TXI6 +void INT_Excep_SCI6_TXI6(void){ } + +//;0x0160 COMPA1 +void INT_Excep_LVD1_LVD1(void){ } + +//;0x0164 COMPA2 +void INT_Excep_LVD2_LVD2(void){ } + +//;0x0168 USBR0 +void INT_Excep_USB0_USBR0(void){ } +//;0x016C Reserved + +//;0x0170 ALM +void INT_Excep_RTC_ALM(void){ } + +//;0x0174 PRD +void INT_Excep_RTC_PRD(void){ } + +//;0x0178 HSUSBR +void INT_Excep_USBA_USBAR(void){ } + +//;0x017C IWUNI +void INT_Excep_IWDT_IWUNI(void){ } + +//;0x0180 WUNI +void INT_Excep_WDT_WUNI(void){ } + +//;0x0184 PCDFI +void INT_Excep_PDC_PCDFI(void){ } + +//;0x0188 RXI7 +void INT_Excep_SCI7_RXI7(void){ } + +//;0x018C TXI7 +void INT_Excep_SCI7_TXI7(void){ } + +//;0x0190 RXIF8 +void INT_Excep_SCIFA8_RXIF8(void){ } + +//;0x0194 TXIF8 +void INT_Excep_SCIFA8_TXIF8(void){ } + +//;0x0198 RXIF9 +void INT_Excep_SCIFA9_RXIF9(void){ } + +//;0x019C TXIF9 +void INT_Excep_SCIFA9_TXIF9(void){ } + +//;0x01A0 RXIF10 +void INT_Excep_SCIFA10_RXIF10(void){ } + +//;0x01A4 TXIF10 +void INT_Excep_SCIFA10_TXIF10(void){ } + +//;0x01A8 GROUPBE0 +void INT_Excep_ICU_GROUPBE0(void){ } +//;0x01AC Reserved + +//;0x01B0 Reserved + +//;0x01B4 Reserved + +//;0x01B8 GROUPBL0 +void INT_Excep_ICU_GROUPBL0(void){ } + +//;0x01BC GROUPBL1 +void INT_Excep_ICU_GROUPBL1(void){ } + +//;0x01C0 GROUPAL0 +void INT_Excep_ICU_GROUPAL0(void){ } + +//;0x01C4 GROUPAL1 +void INT_Excep_ICU_GROUPAL1(void){ } + +//;0x01C8 RXIF11 +void INT_Excep_SCIFA11_RXIF11(void){ } + +//;0x01CC TXIF11 +void INT_Excep_SCIFA11_TXIF11(void){ } + +//;0x01D0 RXIF12 +void INT_Excep_SCI12_RXI12(void){ } + +//;0x01D4 TXIF12 +void INT_Excep_SCI12_TXI12(void){ } + +//;0x01D8 Reserved + +//;0x01DC Reserved + +//;0x01E0 DMAC0I +void INT_Excep_DMAC_DMAC0I(void){ } + +//;0x01E4 DMAC1I +void INT_Excep_DMAC_DMAC1I(void){ } + +//;0x01E8 DMAC2I +void INT_Excep_DMAC_DMAC2I(void){ } + +//;0x01EC DMAC3I +void INT_Excep_DMAC_DMAC3I(void){ } + +//;0x01F0 DMAC74I +void INT_Excep_DMAC_DMAC74I(void){ } + +//;0x01F4 OST +void INT_Excep_OST_OST(void){ } + +//;0x01F8 EXDMAC0I +void INT_Excep_EXDMAC_EXDMAC0I(void){ } + +//;0x01FC EXDMAC1I +void INT_Excep_EXDMAC_EXDMAC1I(void){ } + +//;0x0200 INTB128 +void INT_Excep_PERIB_INTB128(void){ } + +//;0x0204 INTB129 +void INT_Excep_PERIB_INTB129(void){ } + +//;0x0208 INTB130 +void INT_Excep_PERIB_INTB130(void){ } + +//;0x020C INTB131 +void INT_Excep_PERIB_INTB131(void){ } + +//;0x0210 INTB132 +void INT_Excep_PERIB_INTB132(void){ } + +//;0x0214 INTB133 +void INT_Excep_PERIB_INTB133(void){ } + +//;0x0218 INTB134 +void INT_Excep_PERIB_INTB134(void){ } + +//;0x021C INTB135 +void INT_Excep_PERIB_INTB135(void){ } + +//;0x0220 INTB136 +void INT_Excep_PERIB_INTB136(void){ } + +//;0x0224 INTB137 +void INT_Excep_PERIB_INTB137(void){ } + +//;0x0228 INTB138 +void INT_Excep_PERIB_INTB138(void){ } + +//;0x022C INTB139 +void INT_Excep_PERIB_INTB139(void){ } + +//;0x0230 INTB140 +void INT_Excep_PERIB_INTB140(void){ } + +//;0x0234 INTB141 +void INT_Excep_PERIB_INTB141(void){ } + +//;0x0238 INTB142 +void INT_Excep_PERIB_INTB142(void){ } + +//;0x023C INTB143 +void INT_Excep_PERIB_INTB143(void){ } + +//;0x0240 INTB144 +void INT_Excep_PERIB_INTB144(void){ } + +//;0x0244 INTB145 +void INT_Excep_PERIB_INTB145(void){ } + +//;0x0248 INTB146 +void INT_Excep_PERIB_INTB146(void){ } + +//;0x024C INTB147 +void INT_Excep_PERIB_INTB147(void){ } + +//;0x0250 INTB148 +void INT_Excep_PERIB_INTB148(void){ } + +//;0x02540 INTB149 +void INT_Excep_PERIB_INTB149(void){ } + +//;0x0258 INTB150 +void INT_Excep_PERIB_INTB150(void){ } + +//;0x025C INTB151 +void INT_Excep_PERIB_INTB151(void){ } + +//;0x0260 INTB152 +void INT_Excep_PERIB_INTB152(void){ } + +//;0x0264 INTB153 +void INT_Excep_PERIB_INTB153(void){ } + +//;0x0268 INTB154 +void INT_Excep_PERIB_INTB154(void){ } + +//;0x026C INTB155 +void INT_Excep_PERIB_INTB155(void){ } + +//;0x0270 INTB156 +void INT_Excep_PERIB_INTB156(void){ } + +//;0x0274 INTB157 +void INT_Excep_PERIB_INTB157(void){ } + +//;0x0278 INTB158 +void INT_Excep_PERIB_INTB158(void){ } + +//;0x027C INTB159 +void INT_Excep_PERIB_INTB159(void){ } + +//;0x0280 INTB160 +void INT_Excep_PERIB_INTB160(void){ } + +//;0x0284 INTB161 +void INT_Excep_PERIB_INTB161(void){ } + +//;0x0288 INTB162 +void INT_Excep_PERIB_INTB162(void){ } + +//;0x028C INTB163 +void INT_Excep_PERIB_INTB163(void){ } + +//;0x0290 INTB164 +void INT_Excep_PERIB_INTB164(void){ } + +//;0x0294 PERIB INTB165 +void INT_Excep_PERIB_INTB165(void){ } + +//;0x0298 PERIB INTB166 +void INT_Excep_PERIB_INTB166(void){ } + +//;0x029C PERIB INTB167 +void INT_Excep_PERIB_INTB167(void){ } + +//;0x02A0 PERIB INTB168 +void INT_Excep_PERIB_INTB168(void){ } + +//;0x02A4 PERIB INTB169 +void INT_Excep_PERIB_INTB169(void){ } + +//;0x02A8 PERIB INTB170 +void INT_Excep_PERIB_INTB170(void){ } + +//;0x02AC PERIB INTB171 +void INT_Excep_PERIB_INTB171(void){ } + +//;0x02B0 PERIB INTB172 +void INT_Excep_PERIB_INTB172(void){ } + +//;0x02B4 PERIB INTB173 +void INT_Excep_PERIB_INTB173(void){ } + +//;0x02B8 PERIB INTB174 +void INT_Excep_PERIB_INTB174(void){ } + +//;0x02BC PERIB INTB175 +void INT_Excep_PERIB_INTB175(void){ } + +//;0x02C0 PERIB INTB176 +void INT_Excep_PERIB_INTB176(void){ } + +//;0x02C4 PERIB INTB177 +void INT_Excep_PERIB_INTB177(void){ } + +//;0x02C8 PERIB INTB178 +void INT_Excep_PERIB_INTB178(void){ } + +//;0x02CC PERIB INTB179 +void INT_Excep_PERIB_INTB179(void){ } + +//;0x02D0 PERIB INTB180 +void INT_Excep_PERIB_INTB180(void){ } + +//;0x02D4 PERIB INTB181 +void INT_Excep_PERIB_INTB181(void){ } + +//;0x02D8 PERIB INTB182 +void INT_Excep_PERIB_INTB182(void){ } + +//;0x02DC PERIB INTB183 +void INT_Excep_PERIB_INTB183(void){ } + +//;0x02E0 PERIB INTB184 +void INT_Excep_PERIB_INTB184(void){ } + +//;0x02E4 PERIB INTB185 +void INT_Excep_PERIB_INTB185(void){ } + +//;0x02E8 PERIB INTB186 +void INT_Excep_PERIB_INTB186(void){ } + +//;0x02EC PERIB INTB187 +void INT_Excep_PERIB_INTB187(void){ } + +//;0x02F0 PERIB INTB188 +void INT_Excep_PERIB_INTB188(void){ } + +//;0x02F4 PERIB INTB189 +void INT_Excep_PERIB_INTB189(void){ } + +//;0x02F8 PERIB INTB190 +void INT_Excep_PERIB_INTB190(void){ } + +//;0x02FC PERIB INTB191 +void INT_Excep_PERIB_INTB191(void){ } + +//;0x0300 PERIB INTB192 +void INT_Excep_PERIB_INTB192(void){ } + +//;0x0304 PERIB INTB193 +void INT_Excep_PERIB_INTB193(void){ } + +//;0x0308 PERIB INTB194 +void INT_Excep_PERIB_INTB194(void){ } + +//;0x030C PERIB INTB195 +void INT_Excep_PERIB_INTB195(void){ } + +//;0x0310 PERIB INTB196 +void INT_Excep_PERIB_INTB196(void){ } + +//;0x0314 PERIB INTB197 +void INT_Excep_PERIB_INTB197(void){ } + +//;0x0318 PERIB INTB198 +void INT_Excep_PERIB_INTB198(void){ } + +//;0x031C PERIB INTB199 +void INT_Excep_PERIB_INTB199(void){ } + +//;0x0320 PERIB INTB200 +void INT_Excep_PERIB_INTB200(void){ } + +//;0x0324 PERIB INTB201 +void INT_Excep_PERIB_INTB201(void){ } + +//;0x0328 PERIB INTB202 +void INT_Excep_PERIB_INTB202(void){ } + +//;0x032C PERIB INTB203 +void INT_Excep_PERIB_INTB203(void){ } + +//;0x0320 PERIB INTB204 +void INT_Excep_PERIB_INTB204(void){ } + +//;0x0334 PERIB INTB205 +void INT_Excep_PERIB_INTB205(void){ } + +//;0x0338 PERIB INTB206 +void INT_Excep_PERIB_INTB206(void){ } + +//;0x033C PERIB INTB207 +void INT_Excep_PERIB_INTB207(void){ } + +//;0x0340 PERIA INTA208 +void INT_Excep_PERIA_INTA208(void){ } + +//;0x0344 PERIA INTA209 +void INT_Excep_PERIA_INTA209(void){ } + +//;0x0348 PERIA INTA210 +void INT_Excep_PERIA_INTA210(void){ } + +//;0x034C PERIA INTA211 +void INT_Excep_PERIA_INTA211(void){ } + +//;0x0350 PERIA INTA212 +void INT_Excep_PERIA_INTA212(void){ } + +//;0x0354 PERIA INTA213 +void INT_Excep_PERIA_INTA213(void){ } + +//;0x0358 PERIA INTA214 +void INT_Excep_PERIA_INTA214(void){ } + +//;0x035C PERIA INTA215 +void INT_Excep_PERIA_INTA215(void){ } + +//;0x0360 PERIA INTA216 +void INT_Excep_PERIA_INTA216(void){ } + +//;0x0364 PERIA INTA217 +void INT_Excep_PERIA_INTA217(void){ } + +//;0x0368 PERIA INTA218 +void INT_Excep_PERIA_INTA218(void){ } + +//;0x036C PERIA INTA219 +void INT_Excep_PERIA_INTA219(void){ } + +//;0x0370 PERIA INTA220 +void INT_Excep_PERIA_INTA220(void){ } + +//;0x0374 PERIA INTA221 +void INT_Excep_PERIA_INTA221(void){ } + +//;0x0378 PERIA INTA222 +void INT_Excep_PERIA_INTA222(void){ } + +//;0x037C PERIA INTA223 +void INT_Excep_PERIA_INTA223(void){ } + +//;0x0380 PERIA INTA224 +void INT_Excep_PERIA_INTA224(void){ } + +//;0x0384 PERIA INTA225 +void INT_Excep_PERIA_INTA225(void){ } + +//;0x0388 PERIA INTA226 +void INT_Excep_PERIA_INTA226(void){ } + +//;0x038C PERIA INTA227 +void INT_Excep_PERIA_INTA227(void){ } + +//;0x0390 PERIA INTA228 +void INT_Excep_PERIA_INTA228(void){ } + +//;0x0394 PERIA INTA229 +void INT_Excep_PERIA_INTA229(void){ } + +//;0x0398 PERIA INTA230 +void INT_Excep_PERIA_INTA230(void){ } + +//;0x039C PERIA INTA231 +void INT_Excep_PERIA_INTA231(void){ } + +//;0x03A0 PERIA INTA232 +void INT_Excep_PERIA_INTA232(void){ } + +//;0x03A4 PERIA INTA233 +void INT_Excep_PERIA_INTA233(void){ } + +//;0x03A8 PERIA INTA234 +void INT_Excep_PERIA_INTA234(void){ } + +//;0x03AC PERIA INTA235 +void INT_Excep_PERIA_INTA235(void){ } + +//;0x03B0 PERIA INTA236 +void INT_Excep_PERIA_INTA236(void){ } + +//;0x04B4 PERIA INTA237 +void INT_Excep_PERIA_INTA237(void){ } + +//;0x03B8 PERIA INTA238 +void INT_Excep_PERIA_INTA238(void){ } + +//;0x03BC PERIA INTA239 +void INT_Excep_PERIA_INTA239(void){ } + +//;0x03C0 PERIA INTA240 +void INT_Excep_PERIA_INTA240(void){ } + +//;0x03C4 PERIA INTA241 +void INT_Excep_PERIA_INTA241(void){ } + +//;0x03C8 PERIA INTA242 +void INT_Excep_PERIA_INTA242(void){ } + +//;0x03CC PERIA INTA243 +void INT_Excep_PERIA_INTA243(void){ } + +//;0x03D0 PERIA INTA244 +void INT_Excep_PERIA_INTA244(void){ } + +//;0x03D4 PERIA INTA245 +void INT_Excep_PERIA_INTA245(void){ } + +//;0x03D8 PERIA INTA246 +void INT_Excep_PERIA_INTA246(void){ } + +//;0x03DC PERIA INTA247 +void INT_Excep_PERIA_INTA247(void){ } + +//;0x03E0 PERIA INTA248 +void INT_Excep_PERIA_INTA248(void){ } + +//;0x03E4 PERIA INTA249 +void INT_Excep_PERIA_INTA249(void){ } + +//;0x03E8 PERIA INTA250 +void INT_Excep_PERIA_INTA250(void){ } + +//;0x03EC PERIA INTA251 +void INT_Excep_PERIA_INTA251(void){ } + +//;0x03F0 PERIA INTA252 +void INT_Excep_PERIA_INTA252(void){ } + +//;0x03F4 PERIA INTA253 +void INT_Excep_PERIA_INTA253(void){ } + +//;0x03F8 PERIA INTA254 +void INT_Excep_PERIA_INTA254(void){ } + +//;0x03FC PERIA INTA255 +void INT_Excep_PERIA_INTA255(void){ } diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.h new file mode 100644 index 000000000..295d9cb59 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.h @@ -0,0 +1,776 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.h */ +/* DESCRIPTION : Interrupt Handler Declarations */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Modified: 18/12/2014 */ +/************************************************************************/ + +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +// Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); + +// Exception(Access Instruction) +void INT_Excep_AccessInst(void) __attribute__ ((interrupt)); + +// Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); + +// Exception(Floating Point) +void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt)); + +// NMI +void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); + +// Dummy +void Dummy(void) __attribute__ ((interrupt)); + +// BRK +void INT_Excep_BRK(void) __attribute__ ((interrupt)); +//;0x0000 Reserved + +//;0x0004 Reserved + +//;0x0008 Reserved + +//;0x000C Reserved + +//;0x0010 Reserved + +//;0x0014 Reserved + +//;0x0018 Reserved + +//;0x001C Reserved + +//;0x0020 Reserved + +//;0x0024 Reserved + +//;0x0028 Reserved + +//;0x002C Reserved + +//;0x0030 Reserved + +//;0x0034 Reserved + +//;0x0038 Reserved + +//;0x003C Reserved + +//;0x0040 BUSERR +void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt)); +//;0x0044 Reserved + +//;0x0048 RAMERR +void INT_Excep_RAM_RAMERR(void) __attribute__ ((interrupt)); +//;0x004C Reserved + +//;0x0050 Reserved + +//;0x0054 FIFERR +void INT_Excep_FCU_FIFERR(void) __attribute__ ((interrupt)); +//;0x0058 Reserved + +//;0x005C FRDYI +void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); +//;0x0060 Reserved + +//;0x0064 Reserved + +//;0x0068 SWINT2 +void INT_Excep_ICU_SWINT2(void) __attribute__ ((interrupt)); + +//;0x006C SWINT +void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt)); + +//;0x0070 CMI0 +void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt)); + +//;0x0074 CMI1 +void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt)); + +//;0x0078 CMWI0 +void INT_Excep_CMTW0_CMWI0(void) __attribute__ ((interrupt)); + +//;0x007C CMWI1 +void INT_Excep_CMTW1_CMWI1(void) __attribute__ ((interrupt)); + +//;0x0080 D0FIFO2 +void INT_Excep_USBA_D0FIFO2(void) __attribute__ ((interrupt)); + +//;0x0084 D1FIFO2 +void INT_Excep_USBA_D1FIFO2(void) __attribute__ ((interrupt)); + +//;0x0088 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt)); + +//;0x008C D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt)); +//;0x0090 Reserved + +//;0x0094 Reserved + +//;0x0098 SPRI0 +void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt)); + +//;0x009C SPTI0 +void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt)); + + +//;0x00A0 SPRI1 +void INT_Excep_RSPI1_SPRI1(void) __attribute__ ((interrupt)); + + +//;0x00A4 SPTI1 +void INT_Excep_RSPI1_SPTI1(void) __attribute__ ((interrupt)); + + +//;0x00A8 SPRI +void INT_Excep_QSPI_SPRI(void) __attribute__ ((interrupt)); + +//;0x00AC SPTI +void INT_Excep_QSPI_SPTI(void) __attribute__ ((interrupt)); + +//;0x00B0 SBFAI +void INT_Excep_SDHI_SBFAI(void) __attribute__ ((interrupt)); + +//;0x00B4 MBFAI +void INT_Excep_MMCIF_MBFAI(void) __attribute__ ((interrupt)); + +//;0x00B8 SSITX0 +void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt)); + +//;0x00BC SSIRX0 +void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt)); + +//;0x00C0 SSIRTI1 +void INT_Excep_SSI1_SSIRTI1(void) __attribute__ ((interrupt)); +//;0x00C4 Reserved + +//;0x00C8 IDEI +void INT_Excep_SRC_IDEI(void) __attribute__ ((interrupt)); + +//;0x00CC ODFI +void INT_Excep_SRC_ODFI(void) __attribute__ ((interrupt)); + +//;0x00D0 RXI0 +void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); + +//;0x00D4C TXI0 +void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); + +//;0x00D8 RXI2 +void INT_Excep_RIIC2_RXI2(void) __attribute__ ((interrupt)); + +//;0x00DC TXI2 +void INT_Excep_RIIC2_TXI2(void) __attribute__ ((interrupt)); +//;0x00E0 Reserved + +//;0x00E4 Reserved + +//;0x00E8 RXI0 +void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); + +//;0x00EC TXI0 +void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); + +//;0x00F0 RXI1 +void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); + +//;0x00F4 TXI1 +void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); + +//;0x00F8 RXI2 +void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt)); + +//;0x00FC TXI2 +void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt)); + +//;0x0100 IRQ0 +void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt)); + +//;0x0104 IRQ1 +void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt)); + +//;0x0108 IRQ2 +void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt)); + +//;0x010C IRQ3 +void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt)); + +//;0x0110 IRQ4 +void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt)); + +//;0x0114 IRQ5 +void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt)); + +//;0x0118 IRQ6 +void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt)); + +//;0x011C IRQ7 +void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt)); + +//;0x0120 IRQ8 +void INT_Excep_ICU_IRQ8(void) __attribute__ ((interrupt)); + +//;0x0124 IRQ9 +void INT_Excep_ICU_IRQ9(void) __attribute__ ((interrupt)); + +//;0x0128 IRQ10 +void INT_Excep_ICU_IRQ10(void) __attribute__ ((interrupt)); + +//;0x012C IRQ11 +void INT_Excep_ICU_IRQ11(void) __attribute__ ((interrupt)); + +//;0x0130 IRQ12 +void INT_Excep_ICU_IRQ12(void) __attribute__ ((interrupt)); + +//;0x0134 IRQ13 +void INT_Excep_ICU_IRQ13(void) __attribute__ ((interrupt)); + +//;0x0138 IRQ14 +void INT_Excep_ICU_IRQ14(void) __attribute__ ((interrupt)); + +//;0x013C IRQ15 +void INT_Excep_ICU_IRQ15(void) __attribute__ ((interrupt)); + +//;0x0140 RXI3 +void INT_Excep_SCI3_RXI3(void) __attribute__ ((interrupt)); + +//;0x0144 TXI3 +void INT_Excep_SCI3_TXI3(void) __attribute__ ((interrupt)); + +//;0x0148 RXI4 +void INT_Excep_SCI4_RXI4(void) __attribute__ ((interrupt)); + +//;0x014C TXI4 +void INT_Excep_SCI4_TXI4(void) __attribute__ ((interrupt)); + +//;0x0150 RXI5 +void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); + +//;0x0154 TXI5 +void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); + +//;0x0158 RXI6 +void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); + +//;0x015C TXI6 +void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); + +//;0x0160 COMPA1 +void INT_Excep_LVD1_LVD1(void) __attribute__ ((interrupt)); + +//;0x0164 COMPA2 +void INT_Excep_LVD2_LVD2(void) __attribute__ ((interrupt)); + +//;0x0168 USBR0 +void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt)); +//;0x016C Reserved + +//;0x0170 ALM +void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt)); + +//;0x0174 PRD +void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt)); + +//;0x0178 HSUSBR +void INT_Excep_USBA_USBAR(void) __attribute__ ((interrupt)); + +//;0x017C IWUNI +void INT_Excep_IWDT_IWUNI(void) __attribute__ ((interrupt)); + +//;0x0180 WUNI +void INT_Excep_WDT_WUNI(void) __attribute__ ((interrupt)); + +//;0x0184 PCDFI +void INT_Excep_PDC_PCDFI(void) __attribute__ ((interrupt)); + +//;0x0188 RXI7 +void INT_Excep_SCI7_RXI7(void) __attribute__ ((interrupt)); + +//;0x018C TXI7 +void INT_Excep_SCI7_TXI7(void) __attribute__ ((interrupt)); + +//;0x0190 RXIF8 +void INT_Excep_SCIFA8_RXIF8(void) __attribute__ ((interrupt)); + +//;0x0194 TXIF8 +void INT_Excep_SCIFA8_TXIF8(void) __attribute__ ((interrupt)); + +//;0x0198 RXIF9 +void INT_Excep_SCIFA9_RXIF9(void) __attribute__ ((interrupt)); + +//;0x019C TXIF9 +void INT_Excep_SCIFA9_TXIF9(void) __attribute__ ((interrupt)); + +//;0x01A0 RXIF10 +void INT_Excep_SCIFA10_RXIF10(void) __attribute__ ((interrupt)); + +//;0x01A4 TXIF10 +void INT_Excep_SCIFA10_TXIF10(void) __attribute__ ((interrupt)); + +//;0x01A8 GROUPBE0 +void INT_Excep_ICU_GROUPBE0(void) __attribute__ ((interrupt)); +//;0x01AC Reserved + +//;0x01B0 Reserved + +//;0x01B4 Reserved + +//;0x01B8 GROUPBL0 +void INT_Excep_ICU_GROUPBL0(void) __attribute__ ((interrupt)); + +//;0x01BC GROUPBL1 +void INT_Excep_ICU_GROUPBL1(void) __attribute__ ((interrupt)); + +//;0x01C0 GROUPAL0 +void INT_Excep_ICU_GROUPAL0(void) __attribute__ ((interrupt)); + +//;0x01C4 GROUPAL1 +void INT_Excep_ICU_GROUPAL1(void) __attribute__ ((interrupt)); + +//;0x01C8 RXIF11 +void INT_Excep_SCIFA11_RXIF11(void) __attribute__ ((interrupt)); + +//;0x01CC TXIF11 +void INT_Excep_SCIFA11_TXIF11(void) __attribute__ ((interrupt)); + +//;0x01D0 RXIF12 +void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt)); + +//;0x01D4 TXIF12 +void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt)); + +//;0x01D8 Reserved + +//;0x01DC Reserved + +//;0x01E0 DMAC0I +void INT_Excep_DMAC_DMAC0I(void) __attribute__ ((interrupt)); + +//;0x01E4 DMAC1I +void INT_Excep_DMAC_DMAC1I(void) __attribute__ ((interrupt)); + +//;0x01E8 DMAC2I +void INT_Excep_DMAC_DMAC2I(void) __attribute__ ((interrupt)); + +//;0x01EC DMAC3I +void INT_Excep_DMAC_DMAC3I(void) __attribute__ ((interrupt)); + +//;0x01F0 DMAC74I +void INT_Excep_DMAC_DMAC74I(void) __attribute__ ((interrupt)); + +//;0x01F4 OST +void INT_Excep_OST_OST(void) __attribute__ ((interrupt)); + +//;0x01F8 EXDMAC0I +void INT_Excep_EXDMAC_EXDMAC0I(void) __attribute__ ((interrupt)); + +//;0x01FC EXDMAC1I +void INT_Excep_EXDMAC_EXDMAC1I(void) __attribute__ ((interrupt)); + +//;0x0200 INTB128 +void INT_Excep_PERIB_INTB128(void) __attribute__ ((interrupt)); + +//;0x0204 INTB129 +void INT_Excep_PERIB_INTB129(void) __attribute__ ((interrupt)); + +//;0x0208 INTB130 +void INT_Excep_PERIB_INTB130(void) __attribute__ ((interrupt)); + +//;0x020C INTB131 +void INT_Excep_PERIB_INTB131(void) __attribute__ ((interrupt)); + +//;0x0210 INTB132 +void INT_Excep_PERIB_INTB132(void) __attribute__ ((interrupt)); + +//;0x0214 INTB133 +void INT_Excep_PERIB_INTB133(void) __attribute__ ((interrupt)); + +//;0x0218 INTB134 +void INT_Excep_PERIB_INTB134(void) __attribute__ ((interrupt)); + +//;0x021C INTB135 +void INT_Excep_PERIB_INTB135(void) __attribute__ ((interrupt)); + +//;0x0220 INTB136 +void INT_Excep_PERIB_INTB136(void) __attribute__ ((interrupt)); + +//;0x0224 INTB137 +void INT_Excep_PERIB_INTB137(void) __attribute__ ((interrupt)); + +//;0x0228 INTB138 +void INT_Excep_PERIB_INTB138(void) __attribute__ ((interrupt)); + +//;0x022C INTB139 +void INT_Excep_PERIB_INTB139(void) __attribute__ ((interrupt)); + +//;0x0230 INTB140 +void INT_Excep_PERIB_INTB140(void) __attribute__ ((interrupt)); + +//;0x0234 INTB141 +void INT_Excep_PERIB_INTB141(void) __attribute__ ((interrupt)); + +//;0x0238 INTB142 +void INT_Excep_PERIB_INTB142(void) __attribute__ ((interrupt)); + +//;0x023C INTB143 +void INT_Excep_PERIB_INTB143(void) __attribute__ ((interrupt)); + +//;0x0240 INTB144 +void INT_Excep_PERIB_INTB144(void) __attribute__ ((interrupt)); + +//;0x0244 INTB145 +void INT_Excep_PERIB_INTB145(void) __attribute__ ((interrupt)); + +//;0x0248 INTB146 +void INT_Excep_PERIB_INTB146(void) __attribute__ ((interrupt)); + +//;0x024C INTB147 +void INT_Excep_PERIB_INTB147(void) __attribute__ ((interrupt)); + +//;0x0250 INTB148 +void INT_Excep_PERIB_INTB148(void) __attribute__ ((interrupt)); + +//;0x02540 INTB149 +void INT_Excep_PERIB_INTB149(void) __attribute__ ((interrupt)); + +//;0x0258 INTB150 +void INT_Excep_PERIB_INTB150(void) __attribute__ ((interrupt)); + +//;0x025C INTB151 +void INT_Excep_PERIB_INTB151(void) __attribute__ ((interrupt)); + +//;0x0260 INTB152 +void INT_Excep_PERIB_INTB152(void) __attribute__ ((interrupt)); + +//;0x0264 INTB153 +void INT_Excep_PERIB_INTB153(void) __attribute__ ((interrupt)); + +//;0x0268 INTB154 +void INT_Excep_PERIB_INTB154(void) __attribute__ ((interrupt)); + +//;0x026C INTB155 +void INT_Excep_PERIB_INTB155(void) __attribute__ ((interrupt)); + +//;0x0270 INTB156 +void INT_Excep_PERIB_INTB156(void) __attribute__ ((interrupt)); + +//;0x0274 INTB157 +void INT_Excep_PERIB_INTB157(void) __attribute__ ((interrupt)); + +//;0x0278 INTB158 +void INT_Excep_PERIB_INTB158(void) __attribute__ ((interrupt)); + +//;0x027C INTB159 +void INT_Excep_PERIB_INTB159(void) __attribute__ ((interrupt)); + +//;0x0280 INTB160 +void INT_Excep_PERIB_INTB160(void) __attribute__ ((interrupt)); + +//;0x0284 INTB161 +void INT_Excep_PERIB_INTB161(void) __attribute__ ((interrupt)); + +//;0x0288 INTB162 +void INT_Excep_PERIB_INTB162(void) __attribute__ ((interrupt)); + +//;0x028C INTB163 +void INT_Excep_PERIB_INTB163(void) __attribute__ ((interrupt)); + +//;0x0290 INTB164 +void INT_Excep_PERIB_INTB164(void) __attribute__ ((interrupt)); + +//;0x0294 PERIB INTB165 +void INT_Excep_PERIB_INTB165(void) __attribute__ ((interrupt)); + +//;0x0298 PERIB INTB166 +void INT_Excep_PERIB_INTB166(void) __attribute__ ((interrupt)); + +//;0x029C PERIB INTB167 +void INT_Excep_PERIB_INTB167(void) __attribute__ ((interrupt)); + +//;0x02A0 PERIB INTB168 +void INT_Excep_PERIB_INTB168(void) __attribute__ ((interrupt)); + +//;0x02A4 PERIB INTB169 +void INT_Excep_PERIB_INTB169(void) __attribute__ ((interrupt)); + +//;0x02A8 PERIB INTB170 +void INT_Excep_PERIB_INTB170(void) __attribute__ ((interrupt)); + +//;0x02AC PERIB INTB171 +void INT_Excep_PERIB_INTB171(void) __attribute__ ((interrupt)); + +//;0x02B0 PERIB INTB172 +void INT_Excep_PERIB_INTB172(void) __attribute__ ((interrupt)); + +//;0x02B4 PERIB INTB173 +void INT_Excep_PERIB_INTB173(void) __attribute__ ((interrupt)); + +//;0x02B8 PERIB INTB174 +void INT_Excep_PERIB_INTB174(void) __attribute__ ((interrupt)); + +//;0x02BC PERIB INTB175 +void INT_Excep_PERIB_INTB175(void) __attribute__ ((interrupt)); + +//;0x02C0 PERIB INTB176 +void INT_Excep_PERIB_INTB176(void) __attribute__ ((interrupt)); + +//;0x02C4 PERIB INTB177 +void INT_Excep_PERIB_INTB177(void) __attribute__ ((interrupt)); + +//;0x02C8 PERIB INTB178 +void INT_Excep_PERIB_INTB178(void) __attribute__ ((interrupt)); + +//;0x02CC PERIB INTB179 +void INT_Excep_PERIB_INTB179(void) __attribute__ ((interrupt)); + +//;0x02D0 PERIB INTB180 +void INT_Excep_PERIB_INTB180(void) __attribute__ ((interrupt)); + +//;0x02D4 PERIB INTB181 +void INT_Excep_PERIB_INTB181(void) __attribute__ ((interrupt)); + +//;0x02D8 PERIB INTB182 +void INT_Excep_PERIB_INTB182(void) __attribute__ ((interrupt)); + +//;0x02DC PERIB INTB183 +void INT_Excep_PERIB_INTB183(void) __attribute__ ((interrupt)); + +//;0x02E0 PERIB INTB184 +void INT_Excep_PERIB_INTB184(void) __attribute__ ((interrupt)); + +//;0x02E4 PERIB INTB185 +void INT_Excep_PERIB_INTB185(void) __attribute__ ((interrupt)); + +//;0x02E8 PERIB INTB186 +void INT_Excep_PERIB_INTB186(void) __attribute__ ((interrupt)); + +//;0x02EC PERIB INTB187 +void INT_Excep_PERIB_INTB187(void) __attribute__ ((interrupt)); + +//;0x02F0 PERIB INTB188 +void INT_Excep_PERIB_INTB188(void) __attribute__ ((interrupt)); + +//;0x02F4 PERIB INTB189 +void INT_Excep_PERIB_INTB189(void) __attribute__ ((interrupt)); + +//;0x02F8 PERIB INTB190 +void INT_Excep_PERIB_INTB190(void) __attribute__ ((interrupt)); + +//;0x02FC PERIB INTB191 +void INT_Excep_PERIB_INTB191(void) __attribute__ ((interrupt)); + +//;0x0300 PERIB INTB192 +void INT_Excep_PERIB_INTB192(void) __attribute__ ((interrupt)); + +//;0x0304 PERIB INTB193 +void INT_Excep_PERIB_INTB193(void) __attribute__ ((interrupt)); + +//;0x0308 PERIB INTB194 +void INT_Excep_PERIB_INTB194(void) __attribute__ ((interrupt)); + +//;0x030C PERIB INTB195 +void INT_Excep_PERIB_INTB195(void) __attribute__ ((interrupt)); + +//;0x0310 PERIB INTB196 +void INT_Excep_PERIB_INTB196(void) __attribute__ ((interrupt)); + +//;0x0314 PERIB INTB197 +void INT_Excep_PERIB_INTB197(void) __attribute__ ((interrupt)); + +//;0x0318 PERIB INTB198 +void INT_Excep_PERIB_INTB198(void) __attribute__ ((interrupt)); + +//;0x031C PERIB INTB199 +void INT_Excep_PERIB_INTB199(void) __attribute__ ((interrupt)); + +//;0x0320 PERIB INTB200 +void INT_Excep_PERIB_INTB200(void) __attribute__ ((interrupt)); + +//;0x0324 PERIB INTB201 +void INT_Excep_PERIB_INTB201(void) __attribute__ ((interrupt)); + +//;0x0328 PERIB INTB202 +void INT_Excep_PERIB_INTB202(void) __attribute__ ((interrupt)); + +//;0x032C PERIB INTB203 +void INT_Excep_PERIB_INTB203(void) __attribute__ ((interrupt)); + +//;0x0320 PERIB INTB204 +void INT_Excep_PERIB_INTB204(void) __attribute__ ((interrupt)); + +//;0x0334 PERIB INTB205 +void INT_Excep_PERIB_INTB205(void) __attribute__ ((interrupt)); + +//;0x0338 PERIB INTB206 +void INT_Excep_PERIB_INTB206(void) __attribute__ ((interrupt)); + +//;0x033C PERIB INTB207 +void INT_Excep_PERIB_INTB207(void) __attribute__ ((interrupt)); + +//;0x0340 PERIA INTA208 +void INT_Excep_PERIA_INTA208(void) __attribute__ ((interrupt)); + +//;0x0344 PERIA INTA209 +void INT_Excep_PERIA_INTA209(void) __attribute__ ((interrupt)); + +//;0x0348 PERIA INTA210 +void INT_Excep_PERIA_INTA210(void) __attribute__ ((interrupt)); + +//;0x034C PERIA INTA211 +void INT_Excep_PERIA_INTA211(void) __attribute__ ((interrupt)); + +//;0x0350 PERIA INTA212 +void INT_Excep_PERIA_INTA212(void) __attribute__ ((interrupt)); + +//;0x0354 PERIA INTA213 +void INT_Excep_PERIA_INTA213(void) __attribute__ ((interrupt)); + +//;0x0358 PERIA INTA214 +void INT_Excep_PERIA_INTA214(void) __attribute__ ((interrupt)); + +//;0x035C PERIA INTA215 +void INT_Excep_PERIA_INTA215(void) __attribute__ ((interrupt)); + +//;0x0360 PERIA INTA216 +void INT_Excep_PERIA_INTA216(void) __attribute__ ((interrupt)); + +//;0x0364 PERIA INTA217 +void INT_Excep_PERIA_INTA217(void) __attribute__ ((interrupt)); + +//;0x0368 PERIA INTA218 +void INT_Excep_PERIA_INTA218(void) __attribute__ ((interrupt)); + +//;0x036C PERIA INTA219 +void INT_Excep_PERIA_INTA219(void) __attribute__ ((interrupt)); + +//;0x0370 PERIA INTA220 +void INT_Excep_PERIA_INTA220(void) __attribute__ ((interrupt)); + +//;0x0374 PERIA INTA221 +void INT_Excep_PERIA_INTA221(void) __attribute__ ((interrupt)); + +//;0x0378 PERIA INTA222 +void INT_Excep_PERIA_INTA222(void) __attribute__ ((interrupt)); + +//;0x037C PERIA INTA223 +void INT_Excep_PERIA_INTA223(void) __attribute__ ((interrupt)); + +//;0x0380 PERIA INTA224 +void INT_Excep_PERIA_INTA224(void) __attribute__ ((interrupt)); + +//;0x0384 PERIA INTA225 +void INT_Excep_PERIA_INTA225(void) __attribute__ ((interrupt)); + +//;0x0388 PERIA INTA226 +void INT_Excep_PERIA_INTA226(void) __attribute__ ((interrupt)); + +//;0x038C PERIA INTA227 +void INT_Excep_PERIA_INTA227(void) __attribute__ ((interrupt)); + +//;0x0390 PERIA INTA228 +void INT_Excep_PERIA_INTA228(void) __attribute__ ((interrupt)); + +//;0x0394 PERIA INTA229 +void INT_Excep_PERIA_INTA229(void) __attribute__ ((interrupt)); + +//;0x0398 PERIA INTA230 +void INT_Excep_PERIA_INTA230(void) __attribute__ ((interrupt)); + +//;0x039C PERIA INTA231 +void INT_Excep_PERIA_INTA231(void) __attribute__ ((interrupt)); + +//;0x03A0 PERIA INTA232 +void INT_Excep_PERIA_INTA232(void) __attribute__ ((interrupt)); + +//;0x03A4 PERIA INTA233 +void INT_Excep_PERIA_INTA233(void) __attribute__ ((interrupt)); + +//;0x03A8 PERIA INTA234 +void INT_Excep_PERIA_INTA234(void) __attribute__ ((interrupt)); + +//;0x03AC PERIA INTA235 +void INT_Excep_PERIA_INTA235(void) __attribute__ ((interrupt)); + +//;0x03B0 PERIA INTA236 +void INT_Excep_PERIA_INTA236(void) __attribute__ ((interrupt)); + +//;0x04B4 PERIA INTA237 +void INT_Excep_PERIA_INTA237(void) __attribute__ ((interrupt)); + +//;0x03B8 PERIA INTA238 +void INT_Excep_PERIA_INTA238(void) __attribute__ ((interrupt)); + +//;0x03BC PERIA INTA239 +void INT_Excep_PERIA_INTA239(void) __attribute__ ((interrupt)); + +//;0x03C0 PERIA INTA240 +void INT_Excep_PERIA_INTA240(void) __attribute__ ((interrupt)); + +//;0x03C4 PERIA INTA241 +void INT_Excep_PERIA_INTA241(void) __attribute__ ((interrupt)); + +//;0x03C8 PERIA INTA242 +void INT_Excep_PERIA_INTA242(void) __attribute__ ((interrupt)); + +//;0x03CC PERIA INTA243 +void INT_Excep_PERIA_INTA243(void) __attribute__ ((interrupt)); + +//;0x03D0 PERIA INTA244 +void INT_Excep_PERIA_INTA244(void) __attribute__ ((interrupt)); + +//;0x03D4 PERIA INTA245 +void INT_Excep_PERIA_INTA245(void) __attribute__ ((interrupt)); + +//;0x03D8 PERIA INTA246 +void INT_Excep_PERIA_INTA246(void) __attribute__ ((interrupt)); + +//;0x03DC PERIA INTA247 +void INT_Excep_PERIA_INTA247(void) __attribute__ ((interrupt)); + +//;0x03E0 PERIA INTA248 +void INT_Excep_PERIA_INTA248(void) __attribute__ ((interrupt)); + +//;0x03E4 PERIA INTA249 +void INT_Excep_PERIA_INTA249(void) __attribute__ ((interrupt)); + +//;0x03E8 PERIA INTA250 +void INT_Excep_PERIA_INTA250(void) __attribute__ ((interrupt)); + +//;0x03EC PERIA INTA251 +void INT_Excep_PERIA_INTA251(void) __attribute__ ((interrupt)); + +//;0x03F0 PERIA INTA252 +void INT_Excep_PERIA_INTA252(void) __attribute__ ((interrupt)); + +//;0x03F4 PERIA INTA253 +void INT_Excep_PERIA_INTA253(void) __attribute__ ((interrupt)); + +//;0x03F8 PERIA INTA254 +void INT_Excep_PERIA_INTA254(void) __attribute__ ((interrupt)); + +//;0x03FC PERIA INTA255 +void INT_Excep_PERIA_INTA255(void) __attribute__ ((interrupt)); + +//;<> +//;Power On Reset PC +extern void PowerON_Reset(void) __attribute__ ((interrupt)); +//;<> + +#endif diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/reset_program.asm b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/reset_program.asm new file mode 100644 index 000000000..1dda5da84 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/reset_program.asm @@ -0,0 +1,206 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : reset_program.asm */ +/* DESCRIPTION : Reset Program */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.01 */ +/* Date Generated: 04/03/2015 */ +/************************************************************************/ + + /*reset_program.asm*/ + + .list + .section .text + .global _PowerON_Reset /*global Start routine */ + + .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/ + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _main + .extern _ustack + .extern _istack + .extern _rvectors + .extern _exit + +_PowerON_Reset : +/* initialise user stack pointer */ + mvtc #_ustack,USP + +/* initialise interrupt stack pointer */ + mvtc #_istack,ISP + +#ifdef __RXv2__ +/* setup exception vector */ + mvtc #_ExceptVectors, extb /* EXCEPTION VECTOR ADDRESS */ +#endif +/* setup intb */ + mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */ + +/* setup FPSW */ + mvtc #100h, fpsw + +/* load data section from ROM to RAM */ + + mov #_mdata,r2 /* src ROM address of data section in R2 */ + mov #_data,r1 /* dest start RAM address of data section in R1 */ + mov #_edata,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ +#ifdef __RX_ALLOW_STRING_INSNS__ + smovf /* block copy R3 bytes from R2 to R1 */ +#else + cmp #0, r3 + beq 2f + +1: mov.b [r2+], r5 + mov.b r5, [r1+] + sub #1, r3 + bne 1b +2: +#endif + + +/* bss initialisation : zero out bss */ + + mov #00h,r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b +/* call the hardware initialiser */ + mov #_HardwareSetup,r7 + jsr r7 + nop + +/* setup PSW */ + mvtc #10000h, psw /* Set Ubit & Ibit for PSW */ + +/* change PSW PM to user-mode */ + MVFC PSW,R1 +/* DON'T CHANGE TO USER MODE OR #00100000h,R1 */ + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +#ifdef CPPAPP + mov #__rx_init,r7 + jsr r7 +#endif + +/* start user program */ + mov #_main,r7 + jsr r7 + mov #_exit,r7 + jsr r7 + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + /* fall through */ + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + mov #next_inilist,r7 + jsr r7 +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + mov #_rx_run_fini_array,r7 + jsr r7 + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + mov #_rx_run_preinit_array,r7 + jsr r7 + mov #_rx_run_init_array,r7 + jsr r7 + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +/* call to exit*/ +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/typedefine.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/typedefine.h new file mode 100644 index 000000000..aedd1ec1d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/typedefine.h @@ -0,0 +1,28 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 08/07/2013 */ +/************************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/vector_table.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/vector_table.c new file mode 100644 index 000000000..2c6ff8573 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/vector_table.c @@ -0,0 +1,867 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vector_table.c */ +/* DESCRIPTION : Vector Table */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Modified: 18/12/2014 */ +/************************************************************************/ + +#include "interrupt_handlers.h" + +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); +extern void vTickISR( void ); +extern void vSoftwareInterruptISR( void ); +extern void vIntQTimerISR0( void ); +extern void vIntQTimerISR1( void ); + +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *ExceptVectors[] EXVECT_SECT = { +//;0xffffff80 Reserved + (fp)0, +//;0xffffff84 Reserved + (fp)0, +//;0xffffff88 Reserved + (fp)0, +//;0xffffff8C Reserved + (fp)0, +//;0xffffff90 Reserved + (fp)0, +//;0xffffff94 Reserved + (fp)0, +//;0xffffff98 Reserved + (fp)0, +//;0xffffff9C Reserved + (fp)0, +//;0xffffffA0 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA4 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA8 Reserved + (fp)0xFFFFFFFF, +//;0xffffffAC Reserved + (fp)0xFFFFFFFF, +//;0xffffffB0 Reserved + (fp)0, +//;0xffffffB4 Reserved + (fp)0, +//;0xffffffB8 Reserved + (fp)0, +//;0xffffffBC Reserved + (fp)0, +//;0xffffffC0 Reserved + (fp)0, +//;0xffffffC4 Reserved + (fp)0, +//;0xffffffC8 Reserved + (fp)0, +//;0xffffffCC Reserved + (fp)0, +//;0xffffffd0 Exception(Supervisor Instruction) + INT_Excep_SuperVisorInst, +//;0xffffffd4 Exception(Access Instruction) + INT_Excep_AccessInst, +//;0xffffffd8 Reserved + Dummy, +//;0xffffffdc Exception(Undefined Instruction) + INT_Excep_UndefinedInst, +//;0xffffffe0 Reserved + Dummy, +//;0xffffffe4 Exception(Floating Point) + INT_Excep_FloatingPoint, +//;0xffffffe8 Reserved + Dummy, +//;0xffffffec Reserved + Dummy, +//;0xfffffff0 Reserved + Dummy, +//;0xfffffff4 Reserved + Dummy, +//;0xfffffff8 NMI + INT_NonMaskableInterrupt, +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) + +const void *HardwareVectors[] FVECT_SECT = { +//;0xfffffffc RESET +//;<> +//;Power On Reset PC + /*(void*)*/ PowerON_Reset +//;<> +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { +//;0x0000 Reserved + (fp)0, +//;0x0004 Reserved + (fp)0, +//;0x0008 Reserved + (fp)0, +//;0x000C Reserved + (fp)0, +//;0x0010 Reserved + (fp)0, +//;0x0014 Reserved + (fp)0, +//;0x0018 Reserved + (fp)0, +//;0x001C Reserved + (fp)0, +//;0x0020 Reserved + (fp)0, +//;0x0024 Reserved + (fp)0, +//;0x0028 Reserved + (fp)0, +//;0x002C Reserved + (fp)0, +//;0x0030 Reserved + (fp)0, +//;0x0034 Reserved + (fp)0, +//;0x0038 Reserved + (fp)0, +//;0x003C Reserved + (fp)0, +//;0x0040 BUSERR + (fp)INT_Excep_BSC_BUSERR, +//;0x0044 Reserved + (fp)0, +//;0x0048 RAMERR + (fp)INT_Excep_RAM_RAMERR, +//;0x004C Reserved + (fp)0, +//;0x0050 Reserved + (fp)0, +//;0x0054 FIFERR + (fp)INT_Excep_FCU_FIFERR, +//;0x0058 Reserved + (fp)0, +//;0x005C FRDYI + (fp)INT_Excep_FCU_FRDYI, +//;0x0060 Reserved + (fp)0, +//;0x0064 Reserved + (fp)0, +//;0x0068 SWINT2 + (fp)INT_Excep_ICU_SWINT2, + +//;0x006C SWINT + (fp)vSoftwareInterruptISR, + +//;0x0070 CMI0 + (fp)vTickISR, + +//;0x0074 CMI1 + (fp)INT_Excep_CMT1_CMI1, + +//;0x0078 CMWI0 + (fp)INT_Excep_CMTW0_CMWI0, + +//;0x007C CMWI1 + (fp)INT_Excep_CMTW1_CMWI1, + +//;0x0080 D0FIFO2 + (fp)INT_Excep_USBA_D0FIFO2, + +//;0x0084 D1FIFO2 + (fp)INT_Excep_USBA_D1FIFO2, + +//;0x0088 D0FIFO0 + (fp)INT_Excep_USB0_D0FIFO0, + +//;0x008C D1FIFO0 + (fp)INT_Excep_USB0_D1FIFO0, +//;0x0090 Reserved + (fp)0, +//;0x0094 Reserved + (fp)0, +//;0x0098 SPRI0 + (fp)INT_Excep_RSPI0_SPRI0, + +//;0x009C SPTI0 + (fp)INT_Excep_RSPI0_SPTI0, + +//;0x00A0 SPRI1 + (fp)INT_Excep_RSPI1_SPRI1, + +//;0x00A4 SPTI1 + (fp)INT_Excep_RSPI1_SPTI1, + +//;0x00A8 SPRI + (fp)INT_Excep_QSPI_SPRI, + +//;0x00AC SPTI + (fp)INT_Excep_QSPI_SPTI, + +//;0x00B0 SBFAI + (fp)INT_Excep_SDHI_SBFAI, + +//;0x00B4 MBFAI + (fp)INT_Excep_MMCIF_MBFAI, + +//;0x00B8 SSITX0 + (fp)INT_Excep_SSI0_SSITXI0, + +//;0x00BC SSIRX0 + (fp)INT_Excep_SSI0_SSIRXI0, + +//;0x00C0 SSIRTI1 + (fp)INT_Excep_SSI1_SSIRTI1, +//;0x00C4 Reserved + (fp)0, +//;0x00C8 IDEI + (fp)INT_Excep_SRC_IDEI, + +//;0x00CC ODFI + (fp)INT_Excep_SRC_ODFI, + +//;0x00D0 RXI0 + (fp)INT_Excep_RIIC0_RXI0, + +//;0x00D4C TXI0 + (fp)INT_Excep_RIIC0_TXI0, + +//;0x00D8 RXI2 + (fp)INT_Excep_RIIC2_RXI2, + +//;0x00DC TXI2 + (fp)INT_Excep_RIIC2_TXI2, +//;0x00E0 Reserved + (fp)0, +//;0x00E4 Reserved + (fp)0, +//;0x00E8 RXI0 + (fp)INT_Excep_SCI0_RXI0, + +//;0x00EC TXI0 + (fp)INT_Excep_SCI0_TXI0, + +//;0x00F0 RXI1 + (fp)INT_Excep_SCI1_RXI1, + +//;0x00F4 TXI1 + (fp)INT_Excep_SCI1_TXI1, + +//;0x00F8 RXI2 + (fp)INT_Excep_SCI2_RXI2, + +//;0x00FC TXI2 + (fp)INT_Excep_SCI2_TXI2, + +//;0x0100 IRQ0 + (fp)INT_Excep_ICU_IRQ0, + +//;0x0104 IRQ1 + (fp)INT_Excep_ICU_IRQ1, + +//;0x0108 IRQ2 + (fp)INT_Excep_ICU_IRQ2, + +//;0x010C IRQ3 + (fp)INT_Excep_ICU_IRQ3, + +//;0x0110 IRQ4 + (fp)INT_Excep_ICU_IRQ4, + +//;0x0114 IRQ5 + (fp)INT_Excep_ICU_IRQ5, + +//;0x0118 IRQ6 + (fp)INT_Excep_ICU_IRQ6, + +//;0x011C IRQ7 + (fp)INT_Excep_ICU_IRQ7, + +//;0x0120 IRQ8 + (fp)INT_Excep_ICU_IRQ8, + +//;0x0124 IRQ9 + (fp)INT_Excep_ICU_IRQ9, + +//;0x0128 IRQ10 + (fp)INT_Excep_ICU_IRQ10, + +//;0x012C IRQ11 + (fp)INT_Excep_ICU_IRQ11, + +//;0x0130 IRQ12 + (fp)INT_Excep_ICU_IRQ12, + +//;0x0134 IRQ13 + (fp)INT_Excep_ICU_IRQ13, + +//;0x0138 IRQ14 + (fp)INT_Excep_ICU_IRQ14, + +//;0x013C IRQ15 + (fp)INT_Excep_ICU_IRQ15, + +//;0x0140 RXI3 + (fp)INT_Excep_SCI3_RXI3, + +//;0x0144 TXI3 + (fp)INT_Excep_SCI3_TXI3, + +//;0x0148 RXI4 + (fp)INT_Excep_SCI4_RXI4, + +//;0x014C TXI4 + (fp)INT_Excep_SCI4_TXI4, + +//;0x0150 RXI5 + (fp)INT_Excep_SCI5_RXI5, + +//;0x0154 TXI5 + (fp)INT_Excep_SCI5_TXI5, + +//;0x0158 RXI6 + (fp)INT_Excep_SCI6_RXI6, + +//;0x015C TXI6 + (fp)INT_Excep_SCI6_TXI6, + +//;0x0160 COMPA1 + (fp)INT_Excep_LVD1_LVD1, + +//;0x0164 COMPA2 + (fp)INT_Excep_LVD2_LVD2, + +//;0x0168 USBR0 + (fp)INT_Excep_USB0_USBR0, +//;0x016C Reserved + (fp)0, +//;0x0170 ALM + (fp)INT_Excep_RTC_ALM, + +//;0x0174 PRD + (fp)INT_Excep_RTC_PRD, + +//;0x0178 HSUSBR + (fp)INT_Excep_USBA_USBAR, + +//;0x017C IWUNI + (fp)INT_Excep_IWDT_IWUNI, + +//;0x0180 WUNI + (fp)INT_Excep_WDT_WUNI, + +//;0x0184 PCDFI + (fp)INT_Excep_PDC_PCDFI, + +//;0x0188 RXI7 + (fp)INT_Excep_SCI7_RXI7, + +//;0x018C TXI7 + (fp)INT_Excep_SCI7_TXI7, + +//;0x0190 RXIF8 + (fp)INT_Excep_SCIFA8_RXIF8, + +//;0x0194 TXIF8 + (fp)INT_Excep_SCIFA8_TXIF8, + +//;0x0198 RXIF9 + (fp)INT_Excep_SCIFA9_RXIF9, + +//;0x019C TXIF9 + (fp)INT_Excep_SCIFA9_TXIF9, + +//;0x01A0 RXIF10 + (fp)INT_Excep_SCIFA10_RXIF10, + +//;0x01A4 TXIF10 + (fp)INT_Excep_SCIFA10_TXIF10, + +//;0x01A8 GROUPBE0 + (fp)INT_Excep_ICU_GROUPBE0, +//;0x01AC Reserved + (fp)0, +//;0x01B0 Reserved + (fp)0, +//;0x01B4 Reserved + (fp)0, +//;0x01B8 GROUPBL0 + (fp)INT_Excep_ICU_GROUPBL0, + +//;0x01BC GROUPBL1 + (fp)INT_Excep_ICU_GROUPBL1, + +//;0x01C0 GROUPAL0 + (fp)INT_Excep_ICU_GROUPAL0, + +//;0x01C4 GROUPAL1 + (fp)INT_Excep_ICU_GROUPAL1, + +//;0x01C8 RXIF11 + (fp)INT_Excep_SCIFA11_RXIF11, + +//;0x01CC TXIF11 + (fp)INT_Excep_SCIFA11_TXIF11, + +//;0x01D0 RXIF12 + (fp)INT_Excep_SCI12_RXI12, + +//;0x01D4 TXIF12 + (fp)INT_Excep_SCI12_TXI12, + +//;0x01D8 Reserved + (fp)0, +//;0x01DC Reserved + (fp)0, +//;0x01E0 DMAC0I + (fp)INT_Excep_DMAC_DMAC0I, + +//;0x01E4 DMAC1I + (fp)INT_Excep_DMAC_DMAC1I, + +//;0x01E8 DMAC2I + (fp)INT_Excep_DMAC_DMAC2I, + +//;0x01EC DMAC3I + (fp)INT_Excep_DMAC_DMAC3I, + +//;0x01F0 DMAC74I + (fp)INT_Excep_DMAC_DMAC74I, + +//;0x01F4 OST + (fp)INT_Excep_OST_OST, + +//;0x01F8 EXDMAC0I + (fp)INT_Excep_EXDMAC_EXDMAC0I, + +//;0x01FC EXDMAC1I + (fp)INT_Excep_EXDMAC_EXDMAC1I, + +//;0x0200 INTB128 + (fp)vIntQTimerISR0, + +//;0x0204 INTB129 + (fp)vIntQTimerISR1, + +//;0x0208 INTB130 + (fp)INT_Excep_PERIB_INTB130, + +//;0x020C INTB131 + (fp)INT_Excep_PERIB_INTB131, + +//;0x0210 INTB132 + (fp)INT_Excep_PERIB_INTB132, + +//;0x0214 INTB133 + (fp)INT_Excep_PERIB_INTB133, + +//;0x0218 INTB134 + (fp)INT_Excep_PERIB_INTB134, + +//;0x021C INTB135 + (fp)INT_Excep_PERIB_INTB135, + +//;0x0220 INTB136 + (fp)INT_Excep_PERIB_INTB136, + +//;0x0224 INTB137 + (fp)INT_Excep_PERIB_INTB137, + +//;0x0228 INTB138 + (fp)INT_Excep_PERIB_INTB138, + +//;0x022C INTB139 + (fp)INT_Excep_PERIB_INTB139, + +//;0x0230 INTB140 + (fp)INT_Excep_PERIB_INTB140, + +//;0x0234 INTB141 + (fp)INT_Excep_PERIB_INTB141, + +//;0x0238 INTB142 + (fp)INT_Excep_PERIB_INTB142, + +//;0x023C INTB143 + (fp)INT_Excep_PERIB_INTB143, + +//;0x0240 INTB144 + (fp)INT_Excep_PERIB_INTB144, + +//;0x0244 INTB145 + (fp)INT_Excep_PERIB_INTB145, + +//;0x0248 INTB146 + (fp)INT_Excep_PERIB_INTB146, + +//;0x024C INTB147 + (fp)INT_Excep_PERIB_INTB147, + +//;0x0250 INTB148 + (fp)INT_Excep_PERIB_INTB148, + +//;0x02540 INTB149 + (fp)INT_Excep_PERIB_INTB149, + +//;0x0258 INTB150 + (fp)INT_Excep_PERIB_INTB150, + +//;0x025C INTB151 + (fp)INT_Excep_PERIB_INTB151, + +//;0x0260 INTB152 + (fp)INT_Excep_PERIB_INTB152, + +//;0x0264 INTB153 + (fp)INT_Excep_PERIB_INTB153, + +//;0x0268 INTB154 + (fp)INT_Excep_PERIB_INTB154, + +//;0x026C INTB155 + (fp)INT_Excep_PERIB_INTB155, + +//;0x0270 INTB156 + (fp)INT_Excep_PERIB_INTB156, + +//;0x0274 INTB157 + (fp)INT_Excep_PERIB_INTB157, + +//;0x0278 INTB158 + (fp)INT_Excep_PERIB_INTB158, + +//;0x027C INTB159 + (fp)INT_Excep_PERIB_INTB159, + +//;0x0280 INTB160 + (fp)INT_Excep_PERIB_INTB160, + +//;0x0284 INTB161 + (fp)INT_Excep_PERIB_INTB161, + +//;0x0288 INTB162 + (fp)INT_Excep_PERIB_INTB162, + +//;0x028C INTB163 + (fp)INT_Excep_PERIB_INTB163, + +//;0x0290 INTB164 + (fp)INT_Excep_PERIB_INTB164, + +//;0x0294 PERIB INTB165 + (fp)INT_Excep_PERIB_INTB165, + +//;0x0298 PERIB INTB166 + (fp)INT_Excep_PERIB_INTB166, + +//;0x029C PERIB INTB167 + (fp)INT_Excep_PERIB_INTB167, + +//;0x02A0 PERIB INTB168 + (fp)INT_Excep_PERIB_INTB168, + +//;0x02A4 PERIB INTB169 + (fp)INT_Excep_PERIB_INTB169, + +//;0x02A8 PERIB INTB170 + (fp)INT_Excep_PERIB_INTB170, + +//;0x02AC PERIB INTB171 + (fp)INT_Excep_PERIB_INTB171, + +//;0x02B0 PERIB INTB172 + (fp)INT_Excep_PERIB_INTB172, + +//;0x02B4 PERIB INTB173 + (fp)INT_Excep_PERIB_INTB173, + +//;0x02B8 PERIB INTB174 + (fp)INT_Excep_PERIB_INTB174, + +//;0x02BC PERIB INTB175 + (fp)INT_Excep_PERIB_INTB175, + +//;0x02C0 PERIB INTB176 + (fp)INT_Excep_PERIB_INTB176, + +//;0x02C4 PERIB INTB177 + (fp)INT_Excep_PERIB_INTB177, + +//;0x02C8 PERIB INTB178 + (fp)INT_Excep_PERIB_INTB178, + +//;0x02CC PERIB INTB179 + (fp)INT_Excep_PERIB_INTB179, + +//;0x02D0 PERIB INTB180 + (fp)INT_Excep_PERIB_INTB180, + +//;0x02D4 PERIB INTB181 + (fp)INT_Excep_PERIB_INTB181, + +//;0x02D8 PERIB INTB182 + (fp)INT_Excep_PERIB_INTB182, + +//;0x02DC PERIB INTB183 + (fp)INT_Excep_PERIB_INTB183, + +//;0x02E0 PERIB INTB184 + (fp)INT_Excep_PERIB_INTB184, + +//;0x02E4 PERIB INTB185 + (fp)INT_Excep_PERIB_INTB185, + +//;0x02E8 PERIB INTB186 + (fp)INT_Excep_PERIB_INTB186, + +//;0x02EC PERIB INTB187 + (fp)INT_Excep_PERIB_INTB187, + +//;0x02F0 PERIB INTB188 + (fp)INT_Excep_PERIB_INTB188, + +//;0x02F4 PERIB INTB189 + (fp)INT_Excep_PERIB_INTB189, + +//;0x02F8 PERIB INTB190 + (fp)INT_Excep_PERIB_INTB190, + +//;0x02FC PERIB INTB191 + (fp)INT_Excep_PERIB_INTB191, + +//;0x0300 PERIB INTB192 + (fp)INT_Excep_PERIB_INTB192, + +//;0x0304 PERIB INTB193 + (fp)INT_Excep_PERIB_INTB193, + +//;0x0308 PERIB INTB194 + (fp)INT_Excep_PERIB_INTB194, + +//;0x030C PERIB INTB195 + (fp)INT_Excep_PERIB_INTB195, + +//;0x0310 PERIB INTB196 + (fp)INT_Excep_PERIB_INTB196, + +//;0x0314 PERIB INTB197 + (fp)INT_Excep_PERIB_INTB197, + +//;0x0318 PERIB INTB198 + (fp)INT_Excep_PERIB_INTB198, + +//;0x031C PERIB INTB199 + (fp)INT_Excep_PERIB_INTB199, + +//;0x0320 PERIB INTB200 + (fp)INT_Excep_PERIB_INTB200, + +//;0x0324 PERIB INTB201 + (fp)INT_Excep_PERIB_INTB201, + +//;0x0328 PERIB INTB202 + (fp)INT_Excep_PERIB_INTB202, + +//;0x032C PERIB INTB203 + (fp)INT_Excep_PERIB_INTB203, + +//;0x0320 PERIB INTB204 + (fp)INT_Excep_PERIB_INTB204, + +//;0x0334 PERIB INTB205 + (fp)INT_Excep_PERIB_INTB205, + +//;0x0338 PERIB INTB206 + (fp)INT_Excep_PERIB_INTB206, + +//;0x033C PERIB INTB207 + (fp)INT_Excep_PERIB_INTB207, + +//;0x0340 PERIA INTA208 + (fp)INT_Excep_PERIA_INTA208, + +//;0x0344 PERIA INTA209 + (fp)INT_Excep_PERIA_INTA209, + +//;0x0348 PERIA INTA210 + (fp)INT_Excep_PERIA_INTA210, + +//;0x034C PERIA INTA211 + (fp)INT_Excep_PERIA_INTA211, + +//;0x0350 PERIA INTA212 + (fp)INT_Excep_PERIA_INTA212, + +//;0x0354 PERIA INTA213 + (fp)INT_Excep_PERIA_INTA213, + +//;0x0358 PERIA INTA214 + (fp)INT_Excep_PERIA_INTA214, + +//;0x035C PERIA INTA215 + (fp)INT_Excep_PERIA_INTA215, + +//;0x0360 PERIA INTA216 + (fp)INT_Excep_PERIA_INTA216, + +//;0x0364 PERIA INTA217 + (fp)INT_Excep_PERIA_INTA217, + +//;0x0368 PERIA INTA218 + (fp)INT_Excep_PERIA_INTA218, + +//;0x036C PERIA INTA219 + (fp)INT_Excep_PERIA_INTA219, + +//;0x0370 PERIA INTA220 + (fp)INT_Excep_PERIA_INTA220, + +//;0x0374 PERIA INTA221 + (fp)INT_Excep_PERIA_INTA221, + +//;0x0378 PERIA INTA222 + (fp)INT_Excep_PERIA_INTA222, + +//;0x037C PERIA INTA223 + (fp)INT_Excep_PERIA_INTA223, + +//;0x0380 PERIA INTA224 + (fp)INT_Excep_PERIA_INTA224, + +//;0x0384 PERIA INTA225 + (fp)INT_Excep_PERIA_INTA225, + +//;0x0388 PERIA INTA226 + (fp)INT_Excep_PERIA_INTA226, + +//;0x038C PERIA INTA227 + (fp)INT_Excep_PERIA_INTA227, + +//;0x0390 PERIA INTA228 + (fp)INT_Excep_PERIA_INTA228, + +//;0x0394 PERIA INTA229 + (fp)INT_Excep_PERIA_INTA229, + +//;0x0398 PERIA INTA230 + (fp)INT_Excep_PERIA_INTA230, + +//;0x039C PERIA INTA231 + (fp)INT_Excep_PERIA_INTA231, + +//;0x03A0 PERIA INTA232 + (fp)INT_Excep_PERIA_INTA232, + +//;0x03A4 PERIA INTA233 + (fp)INT_Excep_PERIA_INTA233, + +//;0x03A8 PERIA INTA234 + (fp)INT_Excep_PERIA_INTA234, + +//;0x03AC PERIA INTA235 + (fp)INT_Excep_PERIA_INTA235, + +//;0x03B0 PERIA INTA236 + (fp)INT_Excep_PERIA_INTA236, + +//;0x04B4 PERIA INTA237 + (fp)INT_Excep_PERIA_INTA237, + +//;0x03B8 PERIA INTA238 + (fp)INT_Excep_PERIA_INTA238, + +//;0x03BC PERIA INTA239 + (fp)INT_Excep_PERIA_INTA239, + +//;0x03C0 PERIA INTA240 + (fp)INT_Excep_PERIA_INTA240, + +//;0x03C4 PERIA INTA241 + (fp)INT_Excep_PERIA_INTA241, + +//;0x03C8 PERIA INTA242 + (fp)INT_Excep_PERIA_INTA242, + +//;0x03CC PERIA INTA243 + (fp)INT_Excep_PERIA_INTA243, + +//;0x03D0 PERIA INTA244 + (fp)INT_Excep_PERIA_INTA244, + +//;0x03D4 PERIA INTA245 + (fp)INT_Excep_PERIA_INTA245, + +//;0x03D8 PERIA INTA246 + (fp)INT_Excep_PERIA_INTA246, + +//;0x03DC PERIA INTA247 + (fp)INT_Excep_PERIA_INTA247, + +//;0x03E0 PERIA INTA248 + (fp)INT_Excep_PERIA_INTA248, + +//;0x03E4 PERIA INTA249 + (fp)INT_Excep_PERIA_INTA249, + +//;0x03E8 PERIA INTA250 + (fp)INT_Excep_PERIA_INTA250, + +//;0x03EC PERIA INTA251 + (fp)INT_Excep_PERIA_INTA251, + +//;0x03F0 PERIA INTA252 + (fp)INT_Excep_PERIA_INTA252, + +//;0x03F4 PERIA INTA253 + (fp)INT_Excep_PERIA_INTA253, + +//;0x03F8 PERIA INTA254 + (fp)INT_Excep_PERIA_INTA254, + +//;0x03FC PERIA INTA255 + (fp)INT_Excep_PERIA_INTA255, +}; + +#define OFS_SPCC __attribute__ ((section (".ofs1"))) /* 0x00120040 */ +#define OFS_TMEF __attribute__ ((section (".ofs2"))) /* 0x00120048 */ +#define OFS_OSIC __attribute__ ((section (".ofs3"))) /* 0x00120050 */ +#define OFS_REG __attribute__ ((section (".ofs4"))) /* 0x00120060 */ + +const unsigned long __SPCCreg OFS_SPCC = 0xffffffff; + +const unsigned long __TMEFreg OFS_TMEF = 0xffffffff; + +// OSIC register (ID codes) +const unsigned long __OSISreg[4] OFS_OSIC = { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, +}; + +// TMINF register +const unsigned long __TMINFreg OFS_REG = 0xffffffff; + +// MDE register (Single Chip Mode) +#ifdef __RX_BIG_ENDIAN__ + const unsigned long __MDEreg OFS_REG = 0xfffffff8; // big +#else + const unsigned long __MDEreg OFS_REG = 0xffffffff; // little +#endif + +// OFS0 register +const unsigned long __OFS0reg OFS_REG = 0xffffffff; + +// OFS1 register +const unsigned long __OFS1reg OFS_REG = 0xffffffff; diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..460160307 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c @@ -0,0 +1,120 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER24M; + SYSTEM.MOSCWTCR.BYTE = _5C_CGC_MOSCWTCR_VALUE; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + SYSTEM.SCKCR.LONG = _00000002_CGC_PCLKD_DIV_4 | _00000020_CGC_PCLKC_DIV_4 | _00000200_CGC_PCLKB_DIV_4 | + _00001000_CGC_PCLKA_DIV_2 | _00020000_CGC_BCLK_DIV_4 | _00000000_CGC_ICLK_DIV_1 | + _20000000_CGC_FCLK_DIV_4; + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0000_CGC_PLL_SOURCE_MAIN | _1300_CGC_PLL_FREQ_MUL_10_0; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Stop sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Stop sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Wait for sub-clock oscillation stopping */ + while (0U != SYSTEM.OSCOVFSR.BIT.SOOVF); + + /* Set UCLK */ + SYSTEM.SCKCR2.WORD = _0040_CGC_UCLK_DIV_5 | _0001_SCKCR2_BIT0; + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set SDCLK */ + SYSTEM.SCKCR.BIT.PSTOP0 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.LONG; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 0U; +} + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..a5b4f123f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h @@ -0,0 +1,218 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock C (PCLKC) */ +#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */ +#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */ +#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */ +#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */ +#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */ +#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */ +#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 2 (SCKCR2) +*/ +#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */ +#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */ +#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */ +#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */ +#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PLL Clock Source Select (PLLSRCSEL) */ +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ +#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + RTC Control Register 4 (RCR4) +*/ +/* Count source select */ +#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */ +#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _5C_CGC_MOSCWTCR_VALUE (0x5CU) /* Main Clock Oscillator Wait Time */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..979646636 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..932b08ff4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,96 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_icu.h" +#include "r_cg_port.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Initialize non-existent pins */ + PORT5.PDR.BYTE = 0x70U; + + /* Set peripheral settings */ + R_CGC_Create(); + R_ICU_Create(); + R_PORT_Create(); + R_SCI7_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.c new file mode 100644 index 000000000..203e97a0c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.c @@ -0,0 +1,214 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_ICU_Create +* Description : This function initializes ICU module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_Create(void) +{ + /* Disable IRQ interrupts */ + ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE | + _00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE; + ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE | _00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE | + _00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE | _00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE; + + /* Disable group interrupts */ + IEN(ICU,GROUPBL0) = 0U; + + /* Set IRQ settings */ + ICU.IRQCR[2].BYTE = _04_ICU_IRQ_EDGE_FALLING; + ICU.IRQCR[5].BYTE = _04_ICU_IRQ_EDGE_FALLING; + + /* Set IRQ2 priority level */ + IPR(ICU,IRQ2) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set IRQ5 priority level */ + IPR(ICU,IRQ5) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set Group BL0 priority level */ + IPR(ICU,GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15; + + /* Enable group BL0 interrupt */ + IEN(ICU,GROUPBL0) = 1U; + + /* Set IRQ2 pin */ + MPC.P12PFS.BYTE = 0x40U; + PORT1.PDR.BYTE &= 0xFBU; + PORT1.PMR.BYTE &= 0xFBU; + + /* Set IRQ5 pin */ + MPC.P15PFS.BYTE = 0x40U; + PORT1.PDR.BYTE &= 0xDFU; + PORT1.PMR.BYTE &= 0xDFU; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ2_Start +* Description : This function enables IRQ2 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ2_Start(void) +{ + /* Enable IRQ2 interrupt */ + IEN(ICU,IRQ2) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ2_Stop +* Description : This function disables IRQ2 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ2_Stop(void) +{ + /* Disable IRQ2 interrupt */ + IEN(ICU,IRQ2) = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ5_Start +* Description : This function enables IRQ5 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ5_Start(void) +{ + /* Enable IRQ5 interrupt */ + IEN(ICU,IRQ5) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ5_Stop +* Description : This function disables IRQ5 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ5_Stop(void) +{ + /* Disable IRQ5 interrupt */ + IEN(ICU,IRQ5) = 0U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/******************************************************************************* +* Function Name: R_ICU_IRQIsFallingEdge +* Description : This function returns 1 if the specified ICU_IRQ is set to +* falling edge triggered, otherwise 0. +* Arguments : uint8_t irq_no +* Return Value : 1 if falling edge triggered, 0 if not +*******************************************************************************/ +uint8_t R_ICU_IRQIsFallingEdge (const uint8_t irq_no) +{ + uint8_t falling_edge_trig = 0x0; + + if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING) + { + falling_edge_trig = 1; + } + + return falling_edge_trig; + +} + +/******************************************************************************* +* End of function R_ICU_IRQIsFallingEdge +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_IRQSetFallingEdge +* Description : This function sets/clears the falling edge trigger for the +* specified ICU_IRQ. +* Arguments : uint8_t irq_no +* uint8_t set_f_edge, 1 if setting falling edge triggered, 0 if +* clearing +* Return Value : None +*******************************************************************************/ +void R_ICU_IRQSetFallingEdge (const uint8_t irq_no, const uint8_t set_f_edge) +{ + if (1 == set_f_edge) + { + ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING; + } +} + +/****************************************************************************** +* End of function R_ICU_IRQSetFallingEdge +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_IRQSetRisingEdge +* Description : This function sets/clear the rising edge trigger for the +* specified ICU_IRQ. +* Arguments : uint8_t irq_no +* uint8_t set_r_edge, 1 if setting rising edge triggered, 0 if +* clearing +* Return Value : None +*******************************************************************************/ +void R_ICU_IRQSetRisingEdge (const uint8_t irq_no, const uint8_t set_r_edge) +{ + if (1 == set_r_edge) + { + ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING; + } +} + +/****************************************************************************** +* End of function R_ICU_IRQSetRisingEdge +*******************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.h new file mode 100644 index 000000000..bf51e8ea7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu.h @@ -0,0 +1,267 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef ICU_H +#define ICU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Interrupt Request Enable Register 08 (IER08) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_IRQ0_DISABLE (0x00U) /* IRQ0 interrupt request is disabled */ +#define _01_ICU_IRQ0_ENABLE (0x01U) /* IRQ0 interrupt request is enabled */ +#define _00_ICU_IRQ1_DISABLE (0x00U) /* IRQ1 interrupt request is disabled */ +#define _02_ICU_IRQ1_ENABLE (0x02U) /* IRQ1 interrupt request is enabled */ +#define _00_ICU_IRQ2_DISABLE (0x00U) /* IRQ2 interrupt request is disabled */ +#define _04_ICU_IRQ2_ENABLE (0x04U) /* IRQ2 interrupt request is enabled */ +#define _00_ICU_IRQ3_DISABLE (0x00U) /* IRQ3 interrupt request is disabled */ +#define _08_ICU_IRQ3_ENABLE (0x08U) /* IRQ3 interrupt request is enabled */ +#define _00_ICU_IRQ4_DISABLE (0x00U) /* IRQ4 interrupt request is disabled */ +#define _10_ICU_IRQ4_ENABLE (0x10U) /* IRQ4 interrupt request is enabled */ +#define _00_ICU_IRQ5_DISABLE (0x00U) /* IRQ5 interrupt request is disabled */ +#define _20_ICU_IRQ5_ENABLE (0x20U) /* IRQ5 interrupt request is enabled */ +#define _00_ICU_IRQ6_DISABLE (0x00U) /* IRQ6 interrupt request is disabled */ +#define _40_ICU_IRQ6_ENABLE (0x40U) /* IRQ6 interrupt request is enabled */ +#define _00_ICU_IRQ7_DISABLE (0x00U) /* IRQ7 interrupt request is disabled */ +#define _80_ICU_IRQ7_ENABLE (0x80U) /* IRQ7 interrupt request is enabled */ + +/* + Interrupt Request Enable Register 09 (IER09) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_IRQ8_DISABLE (0x00U) /* IRQ8 interrupt request is disabled */ +#define _01_ICU_IRQ8_ENABLE (0x01U) /* IRQ8 interrupt request is enabled */ +#define _00_ICU_IRQ9_DISABLE (0x00U) /* IRQ9 interrupt request is disabled */ +#define _02_ICU_IRQ9_ENABLE (0x02U) /* IRQ9 interrupt request is enabled */ +#define _00_ICU_IRQ10_DISABLE (0x00U) /* IRQ10 interrupt request is disabled */ +#define _04_ICU_IRQ10_ENABLE (0x04U) /* IRQ10 interrupt request is enabled */ +#define _00_ICU_IRQ11_DISABLE (0x00U) /* IRQ11 interrupt request is disabled */ +#define _08_ICU_IRQ11_ENABLE (0x08U) /* IRQ11 interrupt request is enabled */ +#define _00_ICU_IRQ12_DISABLE (0x00U) /* IRQ12 interrupt request is disabled */ +#define _10_ICU_IRQ12_ENABLE (0x10U) /* IRQ12 interrupt request is enabled */ +#define _00_ICU_IRQ13_DISABLE (0x00U) /* IRQ13 interrupt request is disabled */ +#define _20_ICU_IRQ13_ENABLE (0x20U) /* IRQ13 interrupt request is enabled */ +#define _00_ICU_IRQ14_DISABLE (0x00U) /* IRQ14 interrupt request is disabled */ +#define _40_ICU_IRQ14_ENABLE (0x40U) /* IRQ14 interrupt request is enabled */ +#define _00_ICU_IRQ15_DISABLE (0x00U) /* IRQ15 interrupt request is disabled */ +#define _80_ICU_IRQ15_ENABLE (0x80U) /* IRQ15 interrupt request is enabled */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Fast Interrupt Set Register (FIR) +*/ +/* Fast Interrupt Enable (FIEN) */ +#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000U) /* Fast interrupt is disabled */ +#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000U) /* Fast interrupt is enabled */ + +/* + IRQ Control Register i (IRQCRi) (i = 0 to 7) +*/ +/* IRQ Detection Sense Select (IRQMD[1:0]) */ +#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _04_ICU_IRQ_EDGE_FALLING (0x04U) /* Falling edge */ +#define _08_ICU_IRQ_EDGE_RISING (0x08U) /* Rising edge */ +#define _0C_ICU_IRQ_EDGE_BOTH (0x0CU) /* Rising and falling edge */ + +/* + IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) +*/ +/* Digital Filter Enable (FLTEN0n) */ +#define _00_ICU_IRQn_FILTER_DISABLE (0x00U) /* IRQn digital filter is disabled */ +#define _01_ICU_IRQ0_FILTER_ENABLE (0x01U) /* IRQ0 digital filter is enabled */ +#define _02_ICU_IRQ1_FILTER_ENABLE (0x02U) /* IRQ1 digital filter is enabled */ +#define _04_ICU_IRQ2_FILTER_ENABLE (0x04U) /* IRQ2 digital filter is enabled */ +#define _08_ICU_IRQ3_FILTER_ENABLE (0x08U) /* IRQ3 digital filter is enabled */ +#define _10_ICU_IRQ4_FILTER_ENABLE (0x10U) /* IRQ4 digital filter is enabled */ +#define _20_ICU_IRQ5_FILTER_ENABLE (0x20U) /* IRQ5 digital filter is enabled */ +#define _40_ICU_IRQ6_FILTER_ENABLE (0x40U) /* IRQ6 digital filter is enabled */ +#define _80_ICU_IRQ7_FILTER_ENABLE (0x80U) /* IRQ7 digital filter is enabled */ + +/* + IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1) +*/ +/* Digital Filter Enable (FLTEN8~15) */ +#define _01_ICU_IRQ8_FILTER_ENABLE (0x01U) /* IRQ8 digital filter is enabled */ +#define _02_ICU_IRQ9_FILTER_ENABLE (0x02U) /* IRQ9 digital filter is enabled */ +#define _04_ICU_IRQ10_FILTER_ENABLE (0x04U) /* IRQ10 digital filter is enabled */ +#define _08_ICU_IRQ11_FILTER_ENABLE (0x08U) /* IRQ11 digital filter is enabled */ +#define _10_ICU_IRQ12_FILTER_ENABLE (0x10U) /* IRQ12 digital filter is enabled */ +#define _20_ICU_IRQ13_FILTER_ENABLE (0x20U) /* IRQ13 digital filter is enabled */ +#define _40_ICU_IRQ14_FILTER_ENABLE (0x40U) /* IRQ14 digital filter is enabled */ +#define _80_ICU_IRQ15_FILTER_ENABLE (0x80U) /* IRQ15 digital filter is enabled */ + +/* + IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) +*/ +/* IRQn Digital Filter Sampling Clock (FCLKSELn) */ +#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000U) /* IRQ0 sample clock is run at every PCLK cycle */ +#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001U) /* IRQ0 sample clock is run at every PCLK/8 cycle */ +#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002U) /* IRQ0 sample clock is run at every PCLK/32 cycle */ +#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003U) /* IRQ0 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000U) /* IRQ1 sample clock is run at every PCLK cycle */ +#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004U) /* IRQ1 sample clock is run at every PCLK/8 cycle */ +#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008U) /* IRQ1 sample clock is run at every PCLK/32 cycle */ +#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000CU) /* IRQ1 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000U) /* IRQ2 sample clock is run at every PCLK cycle */ +#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010U) /* IRQ2 sample clock is run at every PCLK/8 cycle */ +#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020U) /* IRQ2 sample clock is run at every PCLK/32 cycle */ +#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030U) /* IRQ2 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000U) /* IRQ3 sample clock is run at every PCLK cycle */ +#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040U) /* IRQ3 sample clock is run at every PCLK/8 cycle */ +#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080U) /* IRQ3 sample clock is run at every PCLK/32 cycle */ +#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00C0U) /* IRQ3 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000U) /* IRQ4 sample clock is run at every PCLK cycle */ +#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100U) /* IRQ4 sample clock is run at every PCLK/8 cycle */ +#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200U) /* IRQ4 sample clock is run at every PCLK/32 cycle */ +#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300U) /* IRQ4 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000U) /* IRQ5 sample clock is run at every PCLK cycle */ +#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400U) /* IRQ5 sample clock is run at every PCLK/8 cycle */ +#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800U) /* IRQ5 sample clock is run at every PCLK/32 cycle */ +#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0C00U) /* IRQ5 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000U) /* IRQ6 sample clock is run at every PCLK cycle */ +#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000U) /* IRQ6 sample clock is run at every PCLK/8 cycle */ +#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000U) /* IRQ6 sample clock is run at every PCLK/32 cycle */ +#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000U) /* IRQ6 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000U) /* IRQ7 sample clock is run at every PCLK cycle */ +#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000U) /* IRQ7 sample clock is run at every PCLK/8 cycle */ +#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000U) /* IRQ7 sample clock is run at every PCLK/32 cycle */ +#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xC000U) /* IRQ7 sample clock is run at every PCLK/64 cycle */ + +/* + IRQ Pin Digital Filter Setting Register 0 (IRQFLTC1) +*/ +/* IRQn Digital Filter Sampling Clock (FCLKSEL8~15) */ +#define _0000_ICU_IRQ8_FILTER_PCLK (0x0000U) /* IRQ8 sample clock is run at every PCLK cycle */ +#define _0001_ICU_IRQ8_FILTER_PCLK_8 (0x0001U) /* IRQ8 sample clock is run at every PCLK/8 cycle */ +#define _0002_ICU_IRQ8_FILTER_PCLK_32 (0x0002U) /* IRQ8 sample clock is run at every PCLK/32 cycle */ +#define _0003_ICU_IRQ8_FILTER_PCLK_64 (0x0003U) /* IRQ8 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ9_FILTER_PCLK (0x0000U) /* IRQ9 sample clock is run at every PCLK cycle */ +#define _0004_ICU_IRQ9_FILTER_PCLK_8 (0x0004U) /* IRQ9 sample clock is run at every PCLK/8 cycle */ +#define _0008_ICU_IRQ9_FILTER_PCLK_32 (0x0008U) /* IRQ9 sample clock is run at every PCLK/32 cycle */ +#define _000C_ICU_IRQ9_FILTER_PCLK_64 (0x000CU) /* IRQ9 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ10_FILTER_PCLK (0x0000U) /* IRQ10 sample clock is run at every PCLK cycle */ +#define _0010_ICU_IRQ10_FILTER_PCLK_8 (0x0010U) /* IRQ10 sample clock is run at every PCLK/8 cycle */ +#define _0020_ICU_IRQ10_FILTER_PCLK_32 (0x0020U) /* IRQ10 sample clock is run at every PCLK/32 cycle */ +#define _0030_ICU_IRQ10_FILTER_PCLK_64 (0x0030U) /* IRQ10 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ11_FILTER_PCLK (0x0000U) /* IRQ11 sample clock is run at every PCLK cycle */ +#define _0040_ICU_IRQ11_FILTER_PCLK_8 (0x0040U) /* IRQ11 sample clock is run at every PCLK/8 cycle */ +#define _0080_ICU_IRQ11_FILTER_PCLK_32 (0x0080U) /* IRQ11 sample clock is run at every PCLK/32 cycle */ +#define _00C0_ICU_IRQ11_FILTER_PCLK_64 (0x00C0U) /* IRQ11 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ12_FILTER_PCLK (0x0000U) /* IRQ12 sample clock is run at every PCLK cycle */ +#define _0100_ICU_IRQ12_FILTER_PCLK_8 (0x0100U) /* IRQ12 sample clock is run at every PCLK/8 cycle */ +#define _0200_ICU_IRQ12_FILTER_PCLK_32 (0x0200U) /* IRQ12 sample clock is run at every PCLK/32 cycle */ +#define _0300_ICU_IRQ12_FILTER_PCLK_64 (0x0300U) /* IRQ12 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ13_FILTER_PCLK (0x0000U) /* IRQ13 sample clock is run at every PCLK cycle */ +#define _0400_ICU_IRQ13_FILTER_PCLK_8 (0x0400U) /* IRQ13 sample clock is run at every PCLK/8 cycle */ +#define _0800_ICU_IRQ13_FILTER_PCLK_32 (0x0800U) /* IRQ13 sample clock is run at every PCLK/32 cycle */ +#define _0C00_ICU_IRQ13_FILTER_PCLK_64 (0x0C00U) /* IRQ13 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ14_FILTER_PCLK (0x0000U) /* IRQ14 sample clock is run at every PCLK cycle */ +#define _1000_ICU_IRQ14_FILTER_PCLK_8 (0x1000U) /* IRQ14 sample clock is run at every PCLK/8 cycle */ +#define _2000_ICU_IRQ14_FILTER_PCLK_32 (0x2000U) /* IRQ14 sample clock is run at every PCLK/32 cycle */ +#define _3000_ICU_IRQ14_FILTER_PCLK_64 (0x3000U) /* IRQ14 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ15_FILTER_PCLK (0x0000U) /* IRQ15 sample clock is run at every PCLK cycle */ +#define _4000_ICU_IRQ15_FILTER_PCLK_8 (0x4000U) /* IRQ15 sample clock is run at every PCLK/8 cycle */ +#define _8000_ICU_IRQ15_FILTER_PCLK_32 (0x8000U) /* IRQ15 sample clock is run at every PCLK/32 cycle */ +#define _C000_ICU_IRQ15_FILTER_PCLK_64 (0xC000U) /* IRQ15 sample clock is run at every PCLK/64 cycle */ + + +/* + NMI Pin Interrupt Control Register (NMICR) +*/ +/* NMI Digital Filter Sampling Clock (NMIMD) */ +#define _00_ICU_NMI_EDGE_FALLING (0x00U) /* Falling edge */ +#define _08_ICU_NMI_EDGE_RISING (0x08U) /* Rising edge */ + +/* + NMI Pin Digital Filter Setting Register (NMIFLTC) +*/ +/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */ +#define _00_ICU_NMI_FILTER_PCLK (0x00U) /* NMI sample clock is run at every PCLK cycle */ +#define _01_ICU_NMI_FILTER_PCLK_8 (0x01U) /* NMI sample clock is run at every PCLK/8 cycle */ +#define _02_ICU_NMI_FILTER_PCLK_32 (0x02U) /* NMI sample clock is run at every PCLK/32 cycle */ +#define _03_ICU_NMI_FILTER_PCLK_64 (0x03U) /* NMI sample clock is run at every PCLK/64 cycle */ + +/* + EXDMAC Activation Peripheral Interrupt Select Register (SELEXDR) +*/ +/* EXDMAC0 Activation Peripheral Interrupt Select (SELEXD0) */ +#define _00_ICU_EXDMAC0_SLIBR144 (0x00U) /* Interrupt B selected in SLIBR144 activates EXDMAC0 */ +#define _01_ICU_EXDMAC0_SLIAR208 (0x01U) /* Interrupt B selected in SLIAR208 activates EXDMAC0 */ +/* EXDMAC1 Activation Peripheral Interrupt Select (SELEXD1) */ +#define _00_ICU_EXDMAC1_SLIBR145 (0x00U) /* Interrupt B selected in SLIBR145 activates EXDMAC1 */ +#define _02_ICU_EXDMAC1_SLIAR209 (0x02U) /* Interrupt B selected in SLIAR209 activates EXDMAC1 */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_ICU_Create(void); +void R_ICU_IRQ2_Start(void); +void R_ICU_IRQ2_Stop(void); +void R_ICU_IRQ5_Start(void); +void R_ICU_IRQ5_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ + +/* Function prototypes for detecting and setting the edge trigger of ICU_IRQ */ +uint8_t R_ICU_IRQIsFallingEdge(const uint8_t irq_no); +void R_ICU_IRQSetFallingEdge(const uint8_t irq_no, const uint8_t set_f_edge); +void R_ICU_IRQSetRisingEdge(const uint8_t irq_no, const uint8_t set_r_edge); + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu_user.c new file mode 100644 index 000000000..90be5f36f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_icu_user.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_icu_irq2_interrupt +* Description : This function is IRQ2 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ2 +#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2),fint) +#else +#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2)) +#endif +static void r_icu_irq2_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_icu_irq5_interrupt +* Description : This function is IRQ5 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ5 +#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5),fint) +#else +#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5)) +#endif +static void r_icu_irq5_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..bd639b9ac --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,102 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +//_RB_#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #ifndef __int8_t_defined + #define __int8_t_defined + typedef signed char int8_t; + typedef signed short int16_t; + #endif + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c new file mode 100644 index 000000000..79935ce3c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + PORT0.PODR.BYTE = _08_Pm3_OUTPUT_1 | _20_Pm5_OUTPUT_1; + PORT2.PODR.BYTE = _02_Pm1_OUTPUT_1 | _40_Pm6_OUTPUT_1 | _80_Pm7_OUTPUT_1; + PORT4.PODR.BYTE = _20_Pm5_OUTPUT_1 | _40_Pm6_OUTPUT_1; + PORT0.DSCR.BYTE |= _08_Pm3_HIDRV_ON | _20_Pm5_HIDRV_ON; + PORT2.DSCR.BYTE |= _02_Pm1_HIDRV_ON | _40_Pm6_HIDRV_ON | _80_Pm7_HIDRV_ON; + PORT0.PDR.BYTE = _08_Pm3_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT; + PORT2.PDR.BYTE = _02_Pm1_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT; + PORT4.PDR.BYTE = _20_Pm5_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h new file mode 100644 index 000000000..7d586cbf5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Direction Register (PDR) +*/ +/* Pmn Direction Control (B7 - B0) */ +#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */ +#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */ +#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */ +#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */ +#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */ +#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */ +#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */ +#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */ +#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */ +#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */ +#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */ +#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */ +#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */ +#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */ +#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */ +#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */ +#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */ +#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */ +#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */ +#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */ +#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */ +#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */ +#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */ +#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */ + +/* + Port Output Data Register (PODR) +*/ +/* Pmn Output Data Store (B7 - B0) */ +#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */ +#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */ +#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */ +#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */ +#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */ +#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */ +#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */ +#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */ +#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */ +#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */ +#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */ +#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */ +#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */ +#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */ +#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */ +#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */ + +/* + Open Drain Control Register 0 (ODR0) +*/ +/* Pmn Output Type Select (Pm0 to Pm3) */ +#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */ +#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */ +#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* PMOS open-drain output, for PE1 only*/ +#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */ +#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */ + +/* + Open Drain Control Register 1 (ODR1) +*/ +/* Pmn Output Type Select (Pm4 to Pm7) */ +#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */ +#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */ +#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */ +#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */ + +/* + Pull-Up Control Register (PCR) +*/ +/* Pmn Input Pull-Up Resistor Control (B7 - B0) */ +#define _00_Pm0_PULLUP_OFF (0x00U) /* Pm0 pull-up resistor not connected */ +#define _01_Pm0_PULLUP_ON (0x01U) /* Pm0 pull-up resistor connected */ +#define _00_Pm1_PULLUP_OFF (0x00U) /* Pm1 pull-up resistor not connected */ +#define _02_Pm1_PULLUP_ON (0x02U) /* Pm1 pull-up resistor connected */ +#define _00_Pm2_PULLUP_OFF (0x00U) /* Pm2 Pull-up resistor not connected */ +#define _04_Pm2_PULLUP_ON (0x04U) /* Pm2 pull-up resistor connected */ +#define _00_Pm3_PULLUP_OFF (0x00U) /* Pm3 pull-up resistor not connected */ +#define _08_Pm3_PULLUP_ON (0x08U) /* Pm3 pull-up resistor connected */ +#define _00_Pm4_PULLUP_OFF (0x00U) /* Pm4 pull-up resistor not connected */ +#define _10_Pm4_PULLUP_ON (0x10U) /* Pm4 pull-up resistor connected */ +#define _00_Pm5_PULLUP_OFF (0x00U) /* Pm5 pull-up resistor not connected */ +#define _20_Pm5_PULLUP_ON (0x20U) /* Pm5 pull-up resistor connected */ +#define _00_Pm6_PULLUP_OFF (0x00U) /* Pm6 pull-up resistor not connected */ +#define _40_Pm6_PULLUP_ON (0x40U) /* Pm6 pull-up resistor connected */ +#define _00_Pm7_PULLUP_OFF (0x00U) /* Pm7 pull-up resistor not connected */ +#define _80_Pm7_PULLUP_ON (0x80U) /* Pm7 pull-up resistor connected */ + +/* + Drive Capacity Control Register (DSCR) +*/ +/* Pmn Drive Capacity Control (B7 - B0) */ +#define _00_Pm0_HIDRV_OFF (0x00U) /* Pm0 Normal drive output */ +#define _01_Pm0_HIDRV_ON (0x01U) /* Pm0 High-drive output */ +#define _00_Pm1_HIDRV_OFF (0x00U) /* Pm1 Normal drive output */ +#define _02_Pm1_HIDRV_ON (0x02U) /* Pm1 High-drive output */ +#define _00_Pm2_HIDRV_OFF (0x00U) /* Pm2 Normal drive output */ +#define _04_Pm2_HIDRV_ON (0x04U) /* Pm2 High-drive output */ +#define _00_Pm3_HIDRV_OFF (0x00U) /* Pm3 Normal drive output */ +#define _08_Pm3_HIDRV_ON (0x08U) /* Pm3 High-drive output */ +#define _00_Pm4_HIDRV_OFF (0x00U) /* Pm4 Normal drive output */ +#define _10_Pm4_HIDRV_ON (0x10U) /* Pm4 High-drive output */ +#define _00_Pm5_HIDRV_OFF (0x00U) /* Pm5 Normal drive output */ +#define _20_Pm5_HIDRV_ON (0x20U) /* Pm5 High-drive output */ +#define _00_Pm6_HIDRV_OFF (0x00U) /* Pm6 Normal drive output */ +#define _40_Pm6_HIDRV_ON (0x40U) /* Pm6 High-drive output */ +#define _00_Pm7_HIDRV_OFF (0x00U) /* Pm7 Normal drive output */ +#define _80_Pm7_HIDRV_ON (0x80U) /* Pm7 High-drive output */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _70_PDR5_DEFAULT (0x70U) /* PDR5 default value */ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c new file mode 100644 index 000000000..dfaa939c5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_port_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..c972d5f80 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..a998a4337 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c new file mode 100644 index 000000000..4b2528c33 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +uint8_t * gp_sci7_tx_address; /* SCI7 transmit buffer address */ +uint16_t g_sci7_tx_count; /* SCI7 transmit data number */ +uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_SCI7_Create +* Description : This function initializes SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Create(void) +{ + /* Cancel SCI7 module stop state */ + MSTP(SCI7) = 0U; + + /* Set interrupt priority */ + IPR(SCI7, RXI7) = _0F_SCI_PRIORITY_LEVEL15; + IPR(SCI7, TXI7) = _0F_SCI_PRIORITY_LEVEL15; + + /* Clear the control register */ + SCI7.SCR.BYTE = 0x00U; + + /* Set clock enable */ + SCI7.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + + /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit, and set SPMR */ + SCI7.SIMR1.BIT.IICM = 0U; + SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; + + /* Set control registers */ + SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; + SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | + _00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE; + + /* Set bitrate */ + SCI7.BRR = 0xC2U; + + /* Set RXD7 pin */ + MPC.P92PFS.BYTE = 0x0AU; + PORT9.PMR.BYTE |= 0x04U; + + /* Set TXD7 pin */ + MPC.P90PFS.BYTE = 0x0AU; + PORT9.PODR.BYTE |= 0x01U; + PORT9.PDR.BYTE |= 0x01U; + PORT9.PMR.BYTE |= 0x01U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Start +* Description : This function starts SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Start(void) +{ + /* Clear interrupt flag */ + IR(SCI7, TXI7) = 0U; + IR(SCI7, RXI7) = 0U; + + /* Enable SCI interrupt */ + IEN(SCI7, TXI7) = 1U; + ICU.GENBL0.BIT.EN14 = 1U; + IEN(SCI7, RXI7) = 1U; + ICU.GENBL0.BIT.EN15 = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Stop +* Description : This function stops SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Stop(void) +{ + /* Set TXD7 pin */ + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TE = 0U; /* Disable serial transmit */ + SCI7.SCR.BIT.RE = 0U; /* Disable serial receive */ + + /* Disable SCI interrupt */ + SCI7.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */ + SCI7.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */ + IR(SCI7, TXI7) = 0U; + IEN(SCI7, TXI7) = 0U; + ICU.GENBL0.BIT.EN14 = 0U; + IR(SCI7, RXI7) = 0U; + IEN(SCI7, RXI7) = 0U; + ICU.GENBL0.BIT.EN15 = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Serial_Receive +* Description : This function receives SCI7 data. +* Arguments : rx_buf - +* receive buffer pointer (Not used when receive data handled by DTC or DMAC) +* rx_num - +* buffer size (Not used when receive data handled by DTC or DMAC) +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + MD_STATUS status = MD_OK; + + if (1U > rx_num) + { + status = MD_ARGERROR; + } + else + { + g_sci7_rx_count = 0U; + g_sci7_rx_length = rx_num; + gp_sci7_rx_address = rx_buf; + SCI7.SCR.BIT.RIE = 1U; + SCI7.SCR.BIT.RE = 1U; + } + + return (status); +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Serial_Send +* Description : This function transmits SCI7 data. +* Arguments : tx_buf - +* transfer buffer pointer (Not used when transmit data handled by DTC) +* tx_num - +* buffer size (Not used when transmit data handled by DTC or DMAC) +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (1U > tx_num) + { + status = MD_ARGERROR; + } + else + { + gp_sci7_tx_address = tx_buf; + g_sci7_tx_count = tx_num; + + /* Set TXD7 pin */ + PORT9.PMR.BYTE |= 0x01U; + SCI7.SCR.BIT.TIE = 1U; + SCI7.SCR.BIT.TE = 1U; + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h new file mode 100644 index 000000000..7a963b554 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef SCI_H +#define SCI_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* + Serial mode register (SMR) +*/ +/* Clock select (CKS) */ +#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */ +#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */ +#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */ +#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */ +/* Multi-processor Mode (MP) */ +#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */ +#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */ +/* Stop bit length (STOP) */ +#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */ +#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */ +/* Parity mode (PM) */ +#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */ +#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */ +/* Parity enable (PE) */ +#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */ +#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */ +/* Character length (CHR) */ +#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */ +#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */ +/* Communications mode (CM) */ +#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */ +#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */ +/* Base clock pulse (BCP) */ +#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */ +#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */ +#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */ +#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */ +/* Block transfer mode (BLK) */ +#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */ +#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */ +/* GSM mode (GSM) */ +#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */ +#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */ + +/* + Serial control register (SCR) +*/ +/* Clock enable (CKE) */ +#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */ +#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */ +#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */ +#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */ +/* Transmit end interrupt enable (TEIE) */ +#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */ +#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */ +/* Multi-processor interrupt enable (MPIE) */ +#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */ +#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */ +/* Receive enable (RE) */ +#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */ +#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */ +/* Transmit enable (TE) */ +#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */ +#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */ +/* Receive interrupt enable (RIE) */ +#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */ +#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */ +/* Transmit interrupt enable (TIE) */ +#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */ +#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */ +/* Clock enable (CKE) */ +#define _00_SCI_SCK_OUTPUT_DISABLE (0x00U) /* SCK output is disabled */ +#define _01_SCI_SCK_OUTPUT_ENABLE (0x01U) /* SCK output is enabled */ +#define _00_SCI_SCK_OUTPUT_FIX_LOW (0x00U) /* GSM mode SCK fixed to low */ +#define _02_SCI_SCK_OUTPUT_FIX_HIGH (0x02U) /* GSM mode SCK fixed to high */ + +/* + Serial status register (SSR) +*/ +/* Multi-Processor bit transfer */ +#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */ +#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */ +/* Multi-Processor */ +#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */ +#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */ +/* Transmit end flag (TEND) */ +#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */ +#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */ +/* Parity error flag (PER) */ +#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */ +/* Framing error flag (FER) */ +#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */ +/* Error signal status flag (ERS) */ +#define _10_SCI_LOW_ERROR_DETECTED (0x10U) /* A low error signal responded */ +/* Overrun error flag (ORER) */ +#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */ +/* Receive Data Full Flag (RDRF) */ +#define _40_SCI_RECEIVE_DATAFULL (0x40U) /* Data has been received normally, and transferred from + RSR to RDR */ +/* Transmit Data Empty Flag (TDRE) */ +#define _80_SCI_TRANSMIT_DATAEMPTY (0x80U) /* Data is transferred from TDR to TSR */ + +/* + Smart card mode register (SCMR) +*/ +/* Smart card interface mode select (SMIF) */ +#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */ +#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */ +/* Transmitted / received data invert (SINV) */ +#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */ +#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */ +/* Transmitted / received data transfer direction (SDIR) */ +#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */ +#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */ +/* Character length 1 */ +#define _00_SCI_DATA_LENGTH_9 (0x00U) /* Transmit/receive in 9-bit data length */ +#define _10_SCI_DATA_LENGTH_8_OR_7 (0x10U) /* Transmit/receive in 8-bit or 7-bit data length */ +/* Base clock pulse 2 (BCP2) */ +#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */ +#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */ +#define _62_SCI_SCMR_DEFAULT (0x62U) /* Write default value of SCMR */ + +/* + Serial extended mode register (SEMR) +*/ +/* Asynchronous Mode Clock Source Select (ACS0) */ +#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */ +#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */ +/* Bit Modulation Enable (BRME) */ +#define _00_SCI_BIT_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */ +#define _04_SCI_BIT_MODULATION_ENABLE (0x04U) /* Bit rate modulation function is enabled */ +/* Asynchronous mode base clock select (ABCS) */ +#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */ +#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ +/* Digital noise filter function enable (NFEN) */ +#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */ +#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */ +/* Baud Rate Generator Double-Speed Mode Select (BGDM) */ +#define _00_SCI_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */ +#define _40_SCI_BAUDRATE_DOUBLE (0x40U) /* Baud rate generator doubles output frequency */ +/* Asynchronous start bit edge detections select (RXDESEL) */ +#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */ +#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */ + +/* + Noise filter setting register (SNFR) +*/ +/* Noise filter clock select (NFCS) */ +#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */ +#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */ +#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */ +#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */ +#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */ + +/* + I2C mode register 1 (SIMR1) +*/ +/* Simple IIC mode select (IICM) */ +#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */ +#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */ + +/* + I2C mode register 2 (SIMR2) +*/ +/* IIC interrupt mode select (IICINTM) */ +#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */ +#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */ +/* Clock synchronization (IICCSC) */ +#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */ +#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */ +/* ACK transmission data (IICACKT) */ +#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */ +#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */ + +/* + I2C mode register 3 (SIMR3) +*/ +/* Start condition generation (IICSTAREQ) */ +#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */ +#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */ +/* Restart condition generation (IICRSTAREQ) */ +#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */ +#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */ +/* Stop condition generation (IICSTPREQ) */ +#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */ +#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */ +/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */ +#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */ +#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */ +/* SSDA output select (IICSDAS) */ +#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */ +#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */ +#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */ +#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */ +/* SSCL output select (IICSCLS) */ +#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */ +#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */ +#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */ +#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */ + +/* + I2C status register (SISR) +*/ +/* ACK reception data flag (IICACKR) */ +#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */ +#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */ + +/* + SPI mode register (SPMR) +*/ +/* SS pin function enable (SSE) */ +#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */ +#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */ +/* CTS enable (CTSE) */ +#define _00_SCI_RTS (0x00U) /* RTS function is enabled */ +#define _02_SCI_CTS (0x02U) /* CTS function is disabled */ +/* Master slave select (MSS) */ +#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */ +#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */ +/* Mode fault flag (MFF) */ +#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */ +#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */ +/* Clock polarity select (CKPOL) */ +#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */ +#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */ +/* Clock phase select (CKPH) */ +#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */ +#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Transfer status control value +*/ +/* Simple IIC Transmit Receive Flag */ +#define _80_SCI_IIC_TRANSMISSION (0x80U) +#define _00_SCI_IIC_RECEPTION (0x00U) +/* Simple IIC Start Stop Flag */ +#define _80_SCI_IIC_START_CYCLE (0x80U) +#define _00_SCI_IIC_STOP_CYCLE (0x00U) +/* Multiprocessor Asynchronous Communication Flag */ +#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U) +#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U) + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_SCI7_Create(void); +void R_SCI7_Start(void); +void R_SCI7_Stop(void); +MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num); +MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num); +static void r_sci7_callback_transmitend(void); +static void r_sci7_callback_receiveend(void); +static void r_sci7_callback_receiveerror(void); + +/* Start user code for function. Do not edit comment generated here */ +/* Exported functions used to transmit a number of bytes and wait for completion */ +MD_STATUS R_SCI6_SPIMasterTransmit(uint8_t * const tx_buf, const uint16_t tx_num); +MD_STATUS R_SCI7_AsyncTransmit(uint8_t * const tx_buf, const uint16_t tx_num); + +/* Character is used to receive key presses from PC terminal */ +extern uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +extern volatile uint8_t g_tx_flag; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c new file mode 100644 index 000000000..6f4c8bca6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */ +extern uint16_t g_sci7_tx_count; /* SCI7 send data number */ +extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* Flag used locally to detect transmission complete */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci6_txdone; +static volatile uint8_t sci7_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI7_TXI7 +#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7),fint) +#else +#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7)) +#endif +static void r_sci7_transmit_interrupt(void) +{ + if (0U < g_sci7_tx_count) + { + SCI7.TDR = *gp_sci7_tx_address; + gp_sci7_tx_address++; + g_sci7_tx_count--; + } + else + { + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TEIE = 1U; + } +} + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmitend_interrupt +* Description : This function is TEI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_transmitend_interrupt(void) +{ + /* Set TXD7 pin */ + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TE = 0U; + SCI7.SCR.BIT.TEIE = 0U; + + r_sci7_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI7_RXI7 +#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7),fint) +#else +#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7)) +#endif +static void r_sci7_receive_interrupt(void) +{ + if (g_sci7_rx_length > g_sci7_rx_count) + { + *gp_sci7_rx_address = SCI7.RDR; + gp_sci7_rx_address++; + g_sci7_rx_count++; + + if (g_sci7_rx_length <= g_sci7_rx_count) + { + r_sci7_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receiveerror_interrupt +* Description : This function is ERI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci7_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI7.SSR.BYTE; + err_type &= 0xC7U; + err_type |= 0xC0U; + SCI7.SSR.BYTE = err_type; +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_transmitend +* Description : This function is a callback function when SCI7 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci7_txdone = TRUE; + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveend +* Description : This function is a callback function when SCI7 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if (('c' == g_rx_char) || ('C' == g_rx_char)) + { +//_RB_ g_adc_trigger = TRUE; + } + + /* Set up SCI7 receive buffer and callback function again */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveerror +* Description : This function is a callback function when SCI7 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ + +/******************************************************************************* +* Function Name: R_SCI7_AsyncTransmit +* Description : This function sends SCI7 data and waits for the transmit end flag. +* Arguments : tx_buf - +* transfer buffer pointer +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +*******************************************************************************/ +MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci7_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI7_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci7_txdone) + { + /* Wait */ + } + return (status); +} + +/******************************************************************************* +* End of function R_SCI7_AsyncTransmit +*******************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_stacksct.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_stacksct.h new file mode 100644 index 000000000..dea784bde --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_stacksct.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_stacksct.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Setting of Stack area. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _STACKSCT_H +#define _STACKSCT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +#pragma stacksize su = 0x100 +#pragma stacksize si = 0x300 + + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..45c8b7429 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +#define TRUE (1) +#define FALSE (0) + +extern volatile uint8_t g_adc_trigger; + +/* used to stop warnings being generated in r_cg_intprg.c */ +extern void r_sci6_transmitend_interrupt(void); +extern void r_sci7_transmitend_interrupt(void); +extern void r_sci7_receiveerror_interrupt(void); +extern void r_s12ad0_compare_interrupt(void); + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vect.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vect.h new file mode 100644 index 000000000..6ac0c9593 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vect.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vect.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file contains definition of vector. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _VECT_H +#define _VECT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Undefined */ +#pragma interrupt (r_undefined_exception) +void r_undefined_exception(void); + +/* Reserved */ +#pragma interrupt (r_reserved_exception) +void r_reserved_exception(void); + +/* NMI */ +#pragma interrupt (r_nmi_exception) +void r_nmi_exception(void); + +/* BRK */ +#pragma interrupt (r_brk_exception(vect=0)) +void r_brk_exception(void); + +/* ICU GROUPBE0 */ +#pragma interrupt (r_icu_group_be0_interrupt(vect=106)) +void r_icu_group_be0_interrupt(void); + +/* ICU GROUPBL0 */ +#pragma interrupt (r_icu_group_bl0_interrupt(vect=110)) +void r_icu_group_bl0_interrupt(void); + +/* ICU GROUPBL1 */ +#pragma interrupt (r_icu_group_bl1_interrupt(vect=111)) +void r_icu_group_bl1_interrupt(void); + +/* ICU GROUPAL0 */ +#pragma interrupt (r_icu_group_al0_interrupt(vect=112)) +void r_icu_group_al0_interrupt(void); + +/* ICU GROUPAL1 */ +#pragma interrupt (r_icu_group_al1_interrupt(vect=113)) +void r_icu_group_al1_interrupt(void); + +/*;<> */ +/*;Power On Reset PC */ +extern void PowerON_Reset_PC(void); +/*;<> */ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/iodefine.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/iodefine.h new file mode 100644 index 000000000..85a9ad2c2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/iodefine.h @@ -0,0 +1,29843 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : Definition of I/O Registers */ +/* CPU SERIES : RX700 */ +/* CPU TYPE : RX71M */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/******************************************************************************** +* +* Device : RX/RX700/RX71M +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register +* +* History : 0.10 (2014-03-22) [Hardware Manual Revision : 0.10] +* : 1.00 (2014-12-08) [Hardware Manual Revision : 1.00] +* +* Note : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2014 Renesas Electronics Corporation. +* +*********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX71M */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX71MIODEFINE_HEADER__ +#define __RX71MIODEFINE_HEADER__ + +#pragma pack(4) + +struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif + } BIT; + } CSRECEN; + char wk29[894]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXENB : 1; + unsigned char : 3; + unsigned char BSIZE : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BSIZE : 2; + unsigned char : 3; + unsigned char EXENB : 1; +#endif + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EMODE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EMODE : 1; +#endif + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BE : 1; +#endif + } BIT; + } SDAMOD; + char wk30[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SFEN : 1; +#endif + } BIT; + } SDSELF; + char wk31[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 12; + unsigned short REFW : 4; +#else + unsigned short REFW : 4; + unsigned short RFC : 12; +#endif + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RFEN : 1; +#endif + } BIT; + } SDRFEN; + char wk32[9]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INIRQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char INIRQ : 1; +#endif + } BIT; + } SDICR; + char wk33[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ARFI : 4; + unsigned short ARFC : 4; + unsigned short PRC : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short PRC : 3; + unsigned short ARFC : 4; + unsigned short ARFI : 4; +#endif + } BIT; + } SDIR; + char wk34[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MXC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MXC : 2; +#endif + } BIT; + } SDADR; + char wk35[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CL : 3; + unsigned long : 5; + unsigned long WR : 1; + unsigned long RP : 3; + unsigned long RCD : 2; + unsigned long : 2; + unsigned long RAS : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RAS : 3; + unsigned long : 2; + unsigned long RCD : 2; + unsigned long RP : 3; + unsigned long WR : 1; + unsigned long : 5; + unsigned long CL : 3; +#endif + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MR : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short MR : 15; +#endif + } BIT; + } SDMOD; + char wk36[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MRSST : 1; + unsigned char : 2; + unsigned char INIST : 1; + unsigned char SRFST : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SRFST : 1; + unsigned char INIST : 1; + unsigned char : 2; + unsigned char MRSST : 1; +#endif + } BIT; + } SDSR; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SENTDATA : 1; + unsigned char TRMACTIVE : 1; + unsigned char TRMABT : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char TRMABT : 1; + unsigned char TRMACTIVE : 1; + unsigned char SENTDATA : 1; +#endif + } TX; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NEWDATA : 1; + unsigned char INVALDATA : 1; + unsigned char MSGLOST : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char MSGLOST : 1; + unsigned char INVALDATA : 1; + unsigned char NEWDATA : 1; +#endif + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MBM : 1; + unsigned short IDFM : 2; + unsigned short MLM : 1; + unsigned short TPM : 1; + unsigned short TSRC : 1; + unsigned short TSPS : 2; + unsigned short CANM : 2; + unsigned short SLPM : 1; + unsigned short BOM : 2; + unsigned short RBOC : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RBOC : 1; + unsigned short BOM : 2; + unsigned short SLPM : 1; + unsigned short CANM : 2; + unsigned short TSPS : 2; + unsigned short TSRC : 1; + unsigned short TPM : 1; + unsigned short MLM : 1; + unsigned short IDFM : 2; + unsigned short MBM : 1; +#endif + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NDST : 1; + unsigned short SDST : 1; + unsigned short RFST : 1; + unsigned short TFST : 1; + unsigned short NMLST : 1; + unsigned short FMLST : 1; + unsigned short TABST : 1; + unsigned short EST : 1; + unsigned short RSTST : 1; + unsigned short HLTST : 1; + unsigned short SLPST : 1; + unsigned short EPST : 1; + unsigned short BOST : 1; + unsigned short TRMST : 1; + unsigned short RECST : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RECST : 1; + unsigned short TRMST : 1; + unsigned short BOST : 1; + unsigned short EPST : 1; + unsigned short SLPST : 1; + unsigned short HLTST : 1; + unsigned short RSTST : 1; + unsigned short EST : 1; + unsigned short TABST : 1; + unsigned short FMLST : 1; + unsigned short NMLST : 1; + unsigned short TFST : 1; + unsigned short RFST : 1; + unsigned short SDST : 1; + unsigned short NDST : 1; +#endif + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCLKS : 1; + unsigned long : 7; + unsigned long TSEG2 : 3; + unsigned long : 1; + unsigned long SJW : 2; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long TSEG1 : 4; +#else + unsigned long TSEG1 : 4; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long SJW : 2; + unsigned long : 1; + unsigned long TSEG2 : 3; + unsigned long : 7; + unsigned long CCLKS : 1; +#endif + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFE : 1; + unsigned char RFUST : 3; + unsigned char RFMLF : 1; + unsigned char RFFST : 1; + unsigned char RFWST : 1; + unsigned char RFEST : 1; +#else + unsigned char RFEST : 1; + unsigned char RFWST : 1; + unsigned char RFFST : 1; + unsigned char RFMLF : 1; + unsigned char RFUST : 3; + unsigned char RFE : 1; +#endif + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TFE : 1; + unsigned char TFUST : 3; + unsigned char : 2; + unsigned char TFFST : 1; + unsigned char TFEST : 1; +#else + unsigned char TFEST : 1; + unsigned char TFFST : 1; + unsigned char : 2; + unsigned char TFUST : 3; + unsigned char TFE : 1; +#endif + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIE : 1; + unsigned char EWIE : 1; + unsigned char EPIE : 1; + unsigned char BOEIE : 1; + unsigned char BORIE : 1; + unsigned char ORIE : 1; + unsigned char OLIE : 1; + unsigned char BLIE : 1; +#else + unsigned char BLIE : 1; + unsigned char OLIE : 1; + unsigned char ORIE : 1; + unsigned char BORIE : 1; + unsigned char BOEIE : 1; + unsigned char EPIE : 1; + unsigned char EWIE : 1; + unsigned char BEIE : 1; +#endif + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIF : 1; + unsigned char EWIF : 1; + unsigned char EPIF : 1; + unsigned char BOEIF : 1; + unsigned char BORIF : 1; + unsigned char ORIF : 1; + unsigned char OLIF : 1; + unsigned char BLIF : 1; +#else + unsigned char BLIF : 1; + unsigned char OLIF : 1; + unsigned char ORIF : 1; + unsigned char BORIF : 1; + unsigned char BOEIF : 1; + unsigned char EPIF : 1; + unsigned char EWIF : 1; + unsigned char BEIF : 1; +#endif + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEF : 1; + unsigned char FEF : 1; + unsigned char AEF : 1; + unsigned char CEF : 1; + unsigned char BE1F : 1; + unsigned char BE0F : 1; + unsigned char ADEF : 1; + unsigned char EDPM : 1; +#else + unsigned char EDPM : 1; + unsigned char ADEF : 1; + unsigned char BE0F : 1; + unsigned char BE1F : 1; + unsigned char CEF : 1; + unsigned char AEF : 1; + unsigned char FEF : 1; + unsigned char SEF : 1; +#endif + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBNST : 5; + unsigned char : 2; + unsigned char SEST : 1; +#else + unsigned char SEST : 1; + unsigned char : 2; + unsigned char MBNST : 5; +#endif + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBSM : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MBSM : 2; +#endif + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSTE : 1; + unsigned char TSTM : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TSTM : 2; + unsigned char TSTE : 1; +#endif + } BIT; + } TCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_cmtw { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short STR : 1; +#endif + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short CMWIE : 1; + unsigned short IC0IE : 1; + unsigned short IC1IE : 1; + unsigned short OC0IE : 1; + unsigned short OC1IE : 1; + unsigned short : 1; + unsigned short CMS : 1; + unsigned short : 3; + unsigned short CCLR : 3; +#else + unsigned short CCLR : 3; + unsigned short : 3; + unsigned short CMS : 1; + unsigned short : 1; + unsigned short OC1IE : 1; + unsigned short OC0IE : 1; + unsigned short IC1IE : 1; + unsigned short IC0IE : 1; + unsigned short CMWIE : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IC0 : 2; + unsigned short IC1 : 2; + unsigned short IC0E : 1; + unsigned short IC1E : 1; + unsigned short : 2; + unsigned short OC0 : 2; + unsigned short OC1 : 2; + unsigned short OC0E : 1; + unsigned short OC1E : 1; + unsigned short : 1; + unsigned short CMWE : 1; +#else + unsigned short CMWE : 1; + unsigned short : 1; + unsigned short OC1E : 1; + unsigned short OC0E : 1; + unsigned short OC1 : 2; + unsigned short OC0 : 2; + unsigned short : 2; + unsigned short IC1E : 1; + unsigned short IC0E : 1; + unsigned short IC1 : 2; + unsigned short IC0 : 2; +#endif + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char DAE : 1; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char DAE : 1; + unsigned char : 5; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAAMP0 : 1; + unsigned char DAAMP1 : 1; +#else + unsigned char DAAMP1 : 1; + unsigned char DAAMP0 : 1; + unsigned char : 6; +#endif + } BIT; + } DAAMPCR; + char wk1[17783]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char AMADSEL1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char AMADSEL1 : 1; + unsigned char : 1; +#endif + } BIT; + } DAADUSR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char DMIS4 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS7 : 1; +#else + unsigned char DMIS7 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS4 : 1; + unsigned char : 4; +#endif + } BIT; + } DMIST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; +}; + +struct st_eccram { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMOD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMOD : 2; +#endif + } BIT; + } ECCRAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC2ERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC2ERR : 1; +#endif + } BIT; + } ECCRAM2STS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC1STSEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC1STSEN : 1; +#endif + } BIT; + } ECCRAM1STSEN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC1ERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC1ERR : 1; +#endif + } BIT; + } ECCRAM1STS; +// union { +// unsigned char BYTE; +// struct { +// unsigned char KW:7; +// unsigned char PRCR:1; +// } BIT; +// } ECCRAMPRCR; + unsigned char ECCRAMPRCR; + char wk0[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long ECC2EAD : 12; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ECC2EAD : 12; + unsigned long : 3; +#endif + } BIT; + } ECCRAM2ECAD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long ECC1EAD : 12; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ECC1EAD : 12; + unsigned long : 3; +#endif + } BIT; + } ECCRAM1ECAD; +// union { +// unsigned char BYTE; +// struct { +// unsigned char KW2:7; +// unsigned char PRCR2:1; +// } BIT; +// } ECCRAMPRCR2; + unsigned char ECCRAMPRCR2; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSTBYP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TSTBYP : 1; +#endif + } BIT; + } ECCRAMETST; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SWR : 1; + unsigned long : 3; + unsigned long DL : 2; + unsigned long DE : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long DE : 1; + unsigned long DL : 2; + unsigned long : 3; + unsigned long SWR : 1; +#endif + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long TR : 1; +#endif + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RR : 1; +#endif + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERF : 1; + unsigned long PRE : 1; + unsigned long RTSF : 1; + unsigned long RTLF : 1; + unsigned long RRF : 1; + unsigned long : 2; + unsigned long RMAF : 1; + unsigned long TRO : 1; + unsigned long CD : 1; + unsigned long DLC : 1; + unsigned long CND : 1; + unsigned long : 4; + unsigned long RFOF : 1; + unsigned long RDE : 1; + unsigned long FR : 1; + unsigned long TFUF : 1; + unsigned long TDE : 1; + unsigned long TC : 1; + unsigned long ECI : 1; + unsigned long ADE : 1; + unsigned long RFCOF : 1; + unsigned long RABT : 1; + unsigned long TABT : 1; + unsigned long : 3; + unsigned long TWB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWB : 1; + unsigned long : 3; + unsigned long TABT : 1; + unsigned long RABT : 1; + unsigned long RFCOF : 1; + unsigned long ADE : 1; + unsigned long ECI : 1; + unsigned long TC : 1; + unsigned long TDE : 1; + unsigned long TFUF : 1; + unsigned long FR : 1; + unsigned long RDE : 1; + unsigned long RFOF : 1; + unsigned long : 4; + unsigned long CND : 1; + unsigned long DLC : 1; + unsigned long CD : 1; + unsigned long TRO : 1; + unsigned long RMAF : 1; + unsigned long : 2; + unsigned long RRF : 1; + unsigned long RTLF : 1; + unsigned long RTSF : 1; + unsigned long PRE : 1; + unsigned long CERF : 1; +#endif + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERFIP : 1; + unsigned long PREIP : 1; + unsigned long RTSFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RRFIP : 1; + unsigned long : 2; + unsigned long RMAFIP : 1; + unsigned long TROIP : 1; + unsigned long CDIP : 1; + unsigned long DLCIP : 1; + unsigned long CNDIP : 1; + unsigned long : 4; + unsigned long RFOFIP : 1; + unsigned long RDEIP : 1; + unsigned long FRIP : 1; + unsigned long TFUFIP : 1; + unsigned long TDEIP : 1; + unsigned long TCIP : 1; + unsigned long ECIIP : 1; + unsigned long ADEIP : 1; + unsigned long RFCOFIP : 1; + unsigned long RABTIP : 1; + unsigned long TABTIP : 1; + unsigned long : 3; + unsigned long TWBIP : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWBIP : 1; + unsigned long : 3; + unsigned long TABTIP : 1; + unsigned long RABTIP : 1; + unsigned long RFCOFIP : 1; + unsigned long ADEIP : 1; + unsigned long ECIIP : 1; + unsigned long TCIP : 1; + unsigned long TDEIP : 1; + unsigned long TFUFIP : 1; + unsigned long FRIP : 1; + unsigned long RDEIP : 1; + unsigned long RFOFIP : 1; + unsigned long : 4; + unsigned long CNDIP : 1; + unsigned long DLCIP : 1; + unsigned long CDIP : 1; + unsigned long TROIP : 1; + unsigned long RMAFIP : 1; + unsigned long : 2; + unsigned long RRFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RTSFIP : 1; + unsigned long PREIP : 1; + unsigned long CERFIP : 1; +#endif + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RRFCE : 1; + unsigned long : 2; + unsigned long RMAFCE : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RMAFCE : 1; + unsigned long : 2; + unsigned long RRFCE : 1; + unsigned long : 4; +#endif + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MFC : 16; +#endif + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TFT : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long TFT : 11; +#endif + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFD : 5; + unsigned long : 3; + unsigned long TFD : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TFD : 5; + unsigned long : 3; + unsigned long RFD : 5; +#endif + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RNR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RNR : 1; +#endif + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UNDER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long UNDER : 16; +#endif + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long OVER : 16; +#endif + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long ELB : 1; +#endif + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDO : 3; + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; + unsigned long RFDO : 3; +#endif + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PADR : 6; + unsigned long : 10; + unsigned long PADS : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long PADS : 2; + unsigned long : 10; + unsigned long PADR : 6; +#endif + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIS : 1; + unsigned long : 3; + unsigned long TIM : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long TIM : 1; + unsigned long : 3; + unsigned long TIS : 1; +#endif + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0MD : 2; + unsigned char : 4; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char : 4; + unsigned char MTU0MD : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR3MD : 2; +#else + unsigned char TMR3MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL3; + union { + unsigned char BYTE; +// struct { +// unsigned char WI:1; +// unsigned char WE:1; +// unsigned char :5; +// unsigned char SEG:1; +// } BIT; + } ELSEGR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR33; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR35; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR36; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR37; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR38; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR41; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR42; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR43; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR44; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR45; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPU0MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU3MD : 2; +#else + unsigned char TPU3MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU0MD : 2; +#endif + } BIT; + } ELOPF; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMTW0MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMTW0MD : 2; +#endif + } BIT; + } ELOPH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPT0MD : 3; + unsigned char : 1; + unsigned char GPT1MD : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char GPT1MD : 3; + unsigned char : 1; + unsigned char GPT0MD : 3; +#endif + } BIT; + } ELOPI; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPT2MD : 3; + unsigned char : 1; + unsigned char GPT3MD : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char GPT3MD : 3; + unsigned char : 1; + unsigned char GPT2MD : 3; +#endif + } BIT; + } ELOPJ; +}; + +struct st_eptpc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RESET : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RESET : 1; +#endif + } BIT; + } PTRSTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SCLKDIV : 3; + unsigned long : 5; + unsigned long SCLKSEL : 3; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long SCLKSEL : 3; + unsigned long : 5; + unsigned long SCLKDIV : 3; +#endif + } BIT; + } STCSELR; + char wk0[15096]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :10; +// unsigned long CYC5:1; +// unsigned long CYC4:1; +// unsigned long CYC3:1; +// unsigned long CYC2:1; +// unsigned long CYC1:1; +// unsigned long CYC0:1; +// unsigned long :12; +// unsigned long PRC:1; +// unsigned long SY1:1; +// unsigned long SY0:1; +// unsigned long ST:1; +// } BIT; +// } MIESR; + unsigned long MIESR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ST : 1; + unsigned long SY0 : 1; + unsigned long SY1 : 1; + unsigned long PR : 1; + unsigned long : 12; + unsigned long CYC0 : 1; + unsigned long CYC1 : 1; + unsigned long CYC2 : 1; + unsigned long CYC3 : 1; + unsigned long CYC4 : 1; + unsigned long CYC5 : 1; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long CYC5 : 1; + unsigned long CYC4 : 1; + unsigned long CYC3 : 1; + unsigned long CYC2 : 1; + unsigned long CYC1 : 1; + unsigned long CYC0 : 1; + unsigned long : 12; + unsigned long PR : 1; + unsigned long SY1 : 1; + unsigned long SY0 : 1; + unsigned long ST : 1; +#endif + } BIT; + } MIEIPR; + char wk1[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYCP0 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP5 : 1; + unsigned long : 2; + unsigned long CYCN0 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN5 : 1; + unsigned long : 2; + unsigned long PLSP : 1; + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; + unsigned long PLSP : 1; + unsigned long : 2; + unsigned long CYCN5 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN0 : 1; + unsigned long : 2; + unsigned long CYCP5 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP0 : 1; +#endif + } BIT; + } ELIPPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYCP0 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP5 : 1; + unsigned long : 2; + unsigned long CYCN0 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN5 : 1; + unsigned long : 2; + unsigned long PLSP : 1; + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; + unsigned long PLSP : 1; + unsigned long : 2; + unsigned long CYCN5 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN0 : 1; + unsigned long : 2; + unsigned long CYCP5 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP0 : 1; +#endif + } BIT; + } ELIPACR; + char wk2[40]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :27; +// unsigned long W10D:1; +// unsigned long SYNTOUT:1; +// unsigned long :1; +// unsigned long SYNCOUT:1; +// unsigned long SYNC:1; +// } BIT; +// } STSR; + unsigned long STSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SYNC : 1; + unsigned long SYNCOUT : 1; + unsigned long : 1; + unsigned long SYNTOUT : 1; + unsigned long W10D : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long W10D : 1; + unsigned long SYNTOUT : 1; + unsigned long : 1; + unsigned long SYNCOUT : 1; + unsigned long SYNC : 1; +#endif + } BIT; + } STIPR; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STCF : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long STCF : 2; +#endif + } BIT; + } STCFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WINT : 8; + unsigned long : 5; + unsigned long CMOD : 1; + unsigned long : 1; + unsigned long W10S : 1; + unsigned long SYTH : 4; + unsigned long DVTH : 4; + unsigned long : 4; + unsigned long ALEN0 : 1; + unsigned long ALEN1 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long ALEN1 : 1; + unsigned long ALEN0 : 1; + unsigned long : 4; + unsigned long DVTH : 4; + unsigned long SYTH : 4; + unsigned long W10S : 1; + unsigned long : 1; + unsigned long CMOD : 1; + unsigned long : 5; + unsigned long WINT : 8; +#endif + } BIT; + } STMR; + unsigned long SYNTOR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IPTSEL0 : 1; + unsigned long IPTSEL1 : 1; + unsigned long IPTSEL2 : 1; + unsigned long IPTSEL3 : 1; + unsigned long IPTSEL4 : 1; + unsigned long IPTSEL5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long IPTSEL5 : 1; + unsigned long IPTSEL4 : 1; + unsigned long IPTSEL3 : 1; + unsigned long IPTSEL2 : 1; + unsigned long IPTSEL1 : 1; + unsigned long IPTSEL0 : 1; +#endif + } BIT; + } IPTSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MINTEN0 : 1; + unsigned long MINTEN1 : 1; + unsigned long MINTEN2 : 1; + unsigned long MINTEN3 : 1; + unsigned long MINTEN4 : 1; + unsigned long MINTEN5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long MINTEN5 : 1; + unsigned long MINTEN4 : 1; + unsigned long MINTEN3 : 1; + unsigned long MINTEN2 : 1; + unsigned long MINTEN1 : 1; + unsigned long MINTEN0 : 1; +#endif + } BIT; + } MITSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELTDIS0 : 1; + unsigned long ELTDIS1 : 1; + unsigned long ELTDIS2 : 1; + unsigned long ELTDIS3 : 1; + unsigned long ELTDIS4 : 1; + unsigned long ELTDIS5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long ELTDIS5 : 1; + unsigned long ELTDIS4 : 1; + unsigned long ELTDIS3 : 1; + unsigned long ELTDIS2 : 1; + unsigned long ELTDIS1 : 1; + unsigned long ELTDIS0 : 1; +#endif + } BIT; + } ELTSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SYSEL : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SYSEL : 1; +#endif + } BIT; + } STCHSELR; + char wk5[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long STR : 1; +#endif + } BIT; + } SYNSTARTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LOAD : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long LOAD : 1; +#endif + } BIT; + } LCIVLDR; + char wk6[8]; + unsigned long SYNTDARU; + unsigned long SYNTDARL; + unsigned long SYNTDBRU; + unsigned long SYNTDBRL; + char wk7[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VALU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long VALU : 16; +#endif + } BIT; + } LCIVRU; + unsigned long LCIVRM; + unsigned long LCIVRL; + char wk8[104]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GW10 : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long GW10 : 1; +#endif + } BIT; + } GETW10R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMTU : 31; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long LMTU : 31; +#endif + } BIT; + } PLIMITRU; + unsigned long PLIMITRM; + unsigned long PLIMITRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMTU : 31; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long LMTU : 31; +#endif + } BIT; + } MLIMITRU; + unsigned long MLIMITRM; + unsigned long MLIMITRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INFO : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long INFO : 1; +#endif + } BIT; + } GETINFOR; + char wk9[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CNTU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CNTU : 16; +#endif + } BIT; + } LCCVRU; + unsigned long LCCVRM; + unsigned long LCCVRL; + char wk10[148]; + unsigned long PW10VRU; + unsigned long PW10VRM; + unsigned long PW10VRL; + char wk11[180]; + unsigned long MW10RU; + unsigned long MW10RM; + unsigned long MW10RL; + char wk12[36]; + unsigned long TMSTTRU0; + unsigned long TMSTTRL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR0; + unsigned long TMSTTRU1; + unsigned long TMSTTRL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR1; + unsigned long TMSTTRU2; + unsigned long TMSTTRL2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR2; + unsigned long TMSTTRU3; + unsigned long TMSTTRL3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR3; + unsigned long TMSTTRU4; + unsigned long TMSTTRL4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR4; + unsigned long TMSTTRU5; + unsigned long TMSTTRL5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR5; + char wk13[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } TMSTARTR; + char wk14[128]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :2; +// unsigned long URE1:1; +// unsigned long URE0:1; +// unsigned long :19; +// unsigned long MACE:1; +// unsigned long :4; +// unsigned long OVRE3:1; +// unsigned long OVRE2:1; +// unsigned long OVRE1:1; +// unsigned long OVRE0:1; +// } BIT; +// } PRSR; + unsigned long PRSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVRE0 : 1; + unsigned long OVRE1 : 1; + unsigned long OVRE2 : 1; + unsigned long OVRE3 : 1; + unsigned long : 4; + unsigned long MACE : 1; + unsigned long : 19; + unsigned long URE0 : 1; + unsigned long URE1 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long URE1 : 1; + unsigned long URE0 : 1; + unsigned long : 19; + unsigned long MACE : 1; + unsigned long : 4; + unsigned long OVRE3 : 1; + unsigned long OVRE2 : 1; + unsigned long OVRE1 : 1; + unsigned long OVRE0 : 1; +#endif + } BIT; + } PRIPR; + char wk15[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PRMACRU0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PRMACRL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PRMACRU1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PRMACRL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDIS : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long TDIS : 2; +#endif + } BIT; + } TRNDISR; + char wk16[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MOD : 1; + unsigned long : 7; + unsigned long FWD0 : 1; + unsigned long FWD1 : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long FWD1 : 1; + unsigned long FWD0 : 1; + unsigned long : 7; + unsigned long MOD : 1; +#endif + } BIT; + } TRNMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long THVAL : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long THVAL : 11; +#endif + } BIT; + } TRNCTTDR; +}; + +struct st_eptpc0 { +// union { +// unsigned long LONG; +// struct { +// unsigned long :14; +// unsigned long GENDN:1; +// unsigned long RESDN:1; +// unsigned long :1; +// unsigned long INFABT:1; +// unsigned long :1; +// unsigned long RECLP:1; +// unsigned long :5; +// unsigned long DRQOVR:1; +// unsigned long INTDEV:1; +// unsigned long DRPTO:1; +// unsigned long :1; +// unsigned long MPDUD:1; +// unsigned long INTCHG:1; +// unsigned long OFMUD:1; +// } BIT; +// } SYSR; + unsigned long SYSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OFMUD : 1; + unsigned long INTCHG : 1; + unsigned long MPDUD : 1; + unsigned long : 1; + unsigned long DRPTO : 1; + unsigned long INTDEV : 1; + unsigned long DRQOVR : 1; + unsigned long : 5; + unsigned long RECLP : 1; + unsigned long : 1; + unsigned long INFABT : 1; + unsigned long : 1; + unsigned long RESDN : 1; + unsigned long GENDN : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long GENDN : 1; + unsigned long RESDN : 1; + unsigned long : 1; + unsigned long INFABT : 1; + unsigned long : 1; + unsigned long RECLP : 1; + unsigned long : 5; + unsigned long DRQOVR : 1; + unsigned long INTDEV : 1; + unsigned long DRPTO : 1; + unsigned long : 1; + unsigned long MPDUD : 1; + unsigned long INTCHG : 1; + unsigned long OFMUD : 1; +#endif + } BIT; + } SYIPR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } SYMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } SYMACRL; + unsigned long SYLLCCTLR; + unsigned long SYIPADDRR; + char wk1[32]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VER : 4; + unsigned long TRSP : 4; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TRSP : 4; + unsigned long VER : 4; +#endif + } BIT; + } SYSPVRR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DNUM : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long DNUM : 8; +#endif + } BIT; + } SYDOMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FLAG0 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG15 : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FLAG15 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG0 : 1; +#endif + } BIT; + } ANFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FLAG0 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG15 : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FLAG15 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG0 : 1; +#endif + } BIT; + } SYNFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FLAG0 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG15 : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FLAG15 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG0 : 1; +#endif + } BIT; + } DYRQFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FLAG0 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG15 : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FLAG15 : 1; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long FLAG12 : 1; + unsigned long FLAG11 : 1; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long FLAG7 : 1; + unsigned long FLAG6 : 1; + unsigned long FLAG5 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG0 : 1; +#endif + } BIT; + } DYRPFR; + unsigned long SYCIDRU; + unsigned long SYCIDRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PNUM : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PNUM : 16; +#endif + } BIT; + } SYPNUMR; + char wk3[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BMUP : 1; + unsigned long STUP : 1; + unsigned long ANUP : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long ANUP : 1; + unsigned long STUP : 1; + unsigned long BMUP : 1; +#endif + } BIT; + } SYRVLDR; + char wk4[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 2; + unsigned long : 2; + unsigned long SYNC : 3; + unsigned long : 1; + unsigned long FUP : 3; + unsigned long : 1; + unsigned long DRQ : 3; + unsigned long : 1; + unsigned long DRP : 3; + unsigned long : 1; + unsigned long PDRQ : 3; + unsigned long : 1; + unsigned long PDRP : 3; + unsigned long : 1; + unsigned long PDFUP : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long PDFUP : 3; + unsigned long : 1; + unsigned long PDRP : 3; + unsigned long : 1; + unsigned long PDRQ : 3; + unsigned long : 1; + unsigned long DRP : 3; + unsigned long : 1; + unsigned long DRQ : 3; + unsigned long : 1; + unsigned long FUP : 3; + unsigned long : 1; + unsigned long SYNC : 3; + unsigned long : 2; + unsigned long ANCE : 2; +#endif + } BIT; + } SYRFL1R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MAN : 2; + unsigned long : 2; + unsigned long SIG : 2; + unsigned long : 22; + unsigned long ILL : 2; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long ILL : 2; + unsigned long : 22; + unsigned long SIG : 2; + unsigned long : 2; + unsigned long MAN : 2; +#endif + } BIT; + } SYRFL2R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 1; + unsigned long : 3; + unsigned long SYNC : 1; + unsigned long : 3; + unsigned long DRQ : 1; + unsigned long : 3; + unsigned long PDRQ : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long PDRQ : 1; + unsigned long : 3; + unsigned long DRQ : 1; + unsigned long : 3; + unsigned long SYNC : 1; + unsigned long : 3; + unsigned long ANCE : 1; +#endif + } BIT; + } SYTRENR; + char wk5[4]; + unsigned long MTCIDU; + unsigned long MTCIDL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PNUM : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PNUM : 16; +#endif + } BIT; + } MTPID; + char wk6[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 8; + unsigned long SYNC : 8; + unsigned long DREQ : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DREQ : 8; + unsigned long SYNC : 8; + unsigned long ANCE : 8; +#endif + } BIT; + } SYTLIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 8; + unsigned long SYNC : 8; + unsigned long DRESP : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DRESP : 8; + unsigned long SYNC : 8; + unsigned long ANCE : 8; +#endif + } BIT; + } SYRLIR; + unsigned long OFMRU; + unsigned long OFMRL; + unsigned long MPDRU; + unsigned long MPDRL; + char wk7[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GMPR2 : 8; + unsigned long : 8; + unsigned long GMPR1 : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long GMPR1 : 8; + unsigned long : 8; + unsigned long GMPR2 : 8; +#endif + } BIT; + } GMPR; + unsigned long GMCQR; + unsigned long GMIDRU; + unsigned long GMIDRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TSRC : 8; + unsigned long : 8; + unsigned long CUTO : 16; +#else + unsigned long CUTO : 16; + unsigned long : 8; + unsigned long TSRC : 8; +#endif + } BIT; + } CUOTSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRMV : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long SRMV : 16; +#endif + } BIT; + } SRR; + char wk8[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PPMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PPMACRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PDMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PDMACRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TYPE : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long TYPE : 16; +#endif + } BIT; + } PETYPER; + char wk9[12]; + unsigned long PPIPR; + unsigned long PDIPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EVTO : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long EVTO : 8; +#endif + } BIT; + } PETOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GETO : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long GETO : 8; +#endif + } BIT; + } PGTOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRTL : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long PRTL : 8; +#endif + } BIT; + } PPTTLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PDTL : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long PDTL : 8; +#endif + } BIT; + } PDTTLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EVUPT : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EVUPT : 16; +#endif + } BIT; + } PEUDPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GEUPT : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long GEUPT : 16; +#endif + } BIT; + } PGUDPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 1; + unsigned long PRT : 1; + unsigned long ENB : 1; + unsigned long : 13; + unsigned long EXTPRM : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long EXTPRM : 1; + unsigned long : 13; + unsigned long ENB : 1; + unsigned long PRT : 1; + unsigned long SEL : 1; +#endif + } BIT; + } FFLTR; + char wk10[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } FMAC0RU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } FMAC0RL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } FMAC1RU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } FMAC1RL; + char wk11[80]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ASYMU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ASYMU : 16; +#endif + } BIT; + } DASYMRU; + unsigned long DASYMRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EGP : 16; + unsigned long INGP : 16; +#else + unsigned long INGP : 16; + unsigned long EGP : 16; +#endif + } BIT; + } TSLATR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCYC : 8; + unsigned long : 4; + unsigned long SBDIS : 1; + unsigned long : 3; + unsigned long FILDIS : 1; + unsigned long : 3; + unsigned long TCMOD : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TCMOD : 1; + unsigned long : 3; + unsigned long FILDIS : 1; + unsigned long : 3; + unsigned long SBDIS : 1; + unsigned long : 4; + unsigned long TCYC : 8; +#endif + } BIT; + } SYCONFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FORM0 : 1; + unsigned long FORM1 : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long FORM1 : 1; + unsigned long FORM0 : 1; +#endif + } BIT; + } SYFORMR; + unsigned long RSTOUTR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRM : 1; + unsigned long DM : 1; + unsigned long RTM : 1; + unsigned long ILB : 1; + unsigned long : 1; + unsigned long TE : 1; + unsigned long RE : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long PRCEF : 1; + unsigned long : 3; + unsigned long TXF : 1; + unsigned long RXF : 1; + unsigned long PFR : 1; + unsigned long ZPF : 1; + unsigned long TPC : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TPC : 1; + unsigned long ZPF : 1; + unsigned long PFR : 1; + unsigned long RXF : 1; + unsigned long TXF : 1; + unsigned long : 3; + unsigned long PRCEF : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long RE : 1; + unsigned long TE : 1; + unsigned long : 1; + unsigned long ILB : 1; + unsigned long RTM : 1; + unsigned long DM : 1; + unsigned long PRM : 1; +#endif + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFL : 12; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long RFL : 12; +#endif + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICD : 1; + unsigned long MPD : 1; + unsigned long LCHNG : 1; + unsigned long : 1; + unsigned long PSRTO : 1; + unsigned long BFR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFR : 1; + unsigned long PSRTO : 1; + unsigned long : 1; + unsigned long LCHNG : 1; + unsigned long MPD : 1; + unsigned long ICD : 1; +#endif + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICDIP : 1; + unsigned long MPDIP : 1; + unsigned long LCHNGIP : 1; + unsigned long : 1; + unsigned long PSRTOIP : 1; + unsigned long BFSIPR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFSIPR : 1; + unsigned long PSRTOIP : 1; + unsigned long : 1; + unsigned long LCHNGIP : 1; + unsigned long MPDIP : 1; + unsigned long ICDIP : 1; +#endif + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDC : 1; + unsigned long MMD : 1; + unsigned long MDO : 1; + unsigned long MDI : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long MDI : 1; + unsigned long MDO : 1; + unsigned long MMD : 1; + unsigned long MDC : 1; +#endif + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMON : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long LMON : 1; +#endif + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RMD : 20; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long RMD : 20; +#endif + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IPG : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long IPG : 5; +#endif + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long AP : 16; +#endif + } BIT; + } APR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MP : 16; +#endif + } BIT; + } MPR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RPAUSE : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RPAUSE : 8; +#endif + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TPAUSE : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long TPAUSE : 16; +#endif + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TXP : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TXP : 8; +#endif + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCF : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long BCF : 16; +#endif + } BIT; + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MA : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MA : 16; +#endif + } BIT; + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif + } BIT; + } EDMPRF; +}; + +struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif + } BIT; + } EDMPRF; +}; + +struct st_flash { + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLWE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char FLWE : 2; +#endif + } BIT; + } FWEPROR; + char wk1[7806329]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECRCT : 1; + unsigned char : 2; + unsigned char DFAE : 1; + unsigned char CMDLK : 1; + unsigned char : 2; + unsigned char CFAE : 1; +#else + unsigned char CFAE : 1; + unsigned char : 2; + unsigned char CMDLK : 1; + unsigned char DFAE : 1; + unsigned char : 2; + unsigned char ECRCT : 1; +#endif + } BIT; + } FASTAT; + char wk2[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECRCTIE : 1; + unsigned char : 2; + unsigned char DFAEIE : 1; + unsigned char CMDLKIE : 1; + unsigned char : 2; + unsigned char CFAEIE : 1; +#else + unsigned char CFAEIE : 1; + unsigned char : 2; + unsigned char CMDLKIE : 1; + unsigned char DFAEIE : 1; + unsigned char : 2; + unsigned char ECRCTIE : 1; +#endif + } BIT; + } FAEINT; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRDYIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRDYIE : 1; +#endif + } BIT; + } FRDYIE; + char wk4[23]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FSADDR : 32; +#else + unsigned long FSADDR : 32; +#endif + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FEADDR : 32; +#else + unsigned long FEADDR : 32; +#endif + } BIT; + } FEADDR; + char wk5[28]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCRME : 1; + unsigned short FRAMTRAN : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short FRAMTRAN : 1; + unsigned short FCRME : 1; +#endif + } BIT; + } FCURAME; + char wk6[42]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FRCRCT : 1; + unsigned long FRDTCT : 1; + unsigned long : 4; + unsigned long FLWEERR : 1; + unsigned long FCUERR : 1; + unsigned long PRGSPD : 1; + unsigned long ERSSPD : 1; + unsigned long DBFULL : 1; + unsigned long SUSRDY : 1; + unsigned long PRGERR : 1; + unsigned long ERSERR : 1; + unsigned long ILGLERR : 1; + unsigned long FRDY : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FRDY : 1; + unsigned long ILGLERR : 1; + unsigned long ERSERR : 1; + unsigned long PRGERR : 1; + unsigned long SUSRDY : 1; + unsigned long DBFULL : 1; + unsigned long ERSSPD : 1; + unsigned long PRGSPD : 1; + unsigned long FCUERR : 1; + unsigned long FLWEERR : 1; + unsigned long : 4; + unsigned long FRDTCT : 1; + unsigned long FRCRCT : 1; +#endif + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRYC : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRYC : 1; +#endif + } BIT; + } FENTRYR; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FPROTCN : 1; + unsigned short : 7; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 7; + unsigned short FPROTCN : 1; +#endif + } BIT; + } FPROTR; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SUINIT : 1; + unsigned short : 7; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 7; + unsigned short SUINIT : 1; +#endif + } BIT; + } FSUINITR; + char wk9[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLOCKST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FLOCKST : 1; +#endif + } BIT; + } FLKSTAT; + char wk10[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCMDR : 8; + unsigned short CMDR : 8; +#else + unsigned short CMDR : 8; + unsigned short PCMDR : 8; +#endif + } BIT; + } FCMDR; + char wk11[30]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PEERRST : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short PEERRST : 8; +#endif + } BIT; + } FPESTAT; + char wk12[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCDIR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCDIR : 1; +#endif + } BIT; + } FBCCNT; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCST : 1; +#endif + } BIT; + } FBCSTAT; + char wk14[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSADR : 19; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long PSADR : 19; +#endif + } BIT; + } FPSADDR; + char wk15[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ESUSPMD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ESUSPMD : 1; +#endif + } BIT; + } FCPSR; + char wk16[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCKA : 8; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short PCKA : 8; +#endif + } BIT; + } FPCKAR; +}; + +struct st_gpt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CST0 : 1; + unsigned short CST1 : 1; + unsigned short CST2 : 1; + unsigned short CST3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short CST3 : 1; + unsigned short CST2 : 1; + unsigned short CST1 : 1; + unsigned short CST0 : 1; +#endif + } BIT; + } GTSTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NFA0EN : 1; + unsigned short NFB0EN : 1; + unsigned short NFA1EN : 1; + unsigned short NFB1EN : 1; + unsigned short NFA2EN : 1; + unsigned short NFB2EN : 1; + unsigned short NFA3EN : 1; + unsigned short NFB3EN : 1; + unsigned short NFCS0 : 2; + unsigned short NFCS1 : 2; + unsigned short NFCS2 : 2; + unsigned short NFCS3 : 2; +#else + unsigned short NFCS3 : 2; + unsigned short NFCS2 : 2; + unsigned short NFCS1 : 2; + unsigned short NFCS0 : 2; + unsigned short NFB3EN : 1; + unsigned short NFA3EN : 1; + unsigned short NFB2EN : 1; + unsigned short NFA2EN : 1; + unsigned short NFB1EN : 1; + unsigned short NFA1EN : 1; + unsigned short NFB0EN : 1; + unsigned short NFA0EN : 1; +#endif + } BIT; + } NFCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CSHW0 : 2; + unsigned short CSHW1 : 2; + unsigned short CSHW2 : 2; + unsigned short CSHW3 : 2; + unsigned short CPHW0 : 2; + unsigned short CPHW1 : 2; + unsigned short CPHW2 : 2; + unsigned short CPHW3 : 2; +#else + unsigned short CPHW3 : 2; + unsigned short CPHW2 : 2; + unsigned short CPHW1 : 2; + unsigned short CPHW0 : 2; + unsigned short CSHW3 : 2; + unsigned short CSHW2 : 2; + unsigned short CSHW1 : 2; + unsigned short CSHW0 : 2; +#endif + } BIT; + } GTHSCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CCHW0 : 2; + unsigned short CCHW1 : 2; + unsigned short CCHW2 : 2; + unsigned short CCHW3 : 2; + unsigned short CCSW0 : 1; + unsigned short CCSW1 : 1; + unsigned short CCSW2 : 1; + unsigned short CCSW3 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CCSW3 : 1; + unsigned short CCSW2 : 1; + unsigned short CCSW1 : 1; + unsigned short CCSW0 : 1; + unsigned short CCHW3 : 2; + unsigned short CCHW2 : 2; + unsigned short CCHW1 : 2; + unsigned short CCHW0 : 2; +#endif + } BIT; + } GTHCCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CSHSL0 : 4; + unsigned short CSHSL1 : 4; + unsigned short CSHSL2 : 4; + unsigned short CSHSL3 : 4; +#else + unsigned short CSHSL3 : 4; + unsigned short CSHSL2 : 4; + unsigned short CSHSL1 : 4; + unsigned short CSHSL0 : 4; +#endif + } BIT; + } GTHSSR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CSHPL0 : 4; + unsigned short CSHPL1 : 4; + unsigned short CSHPL2 : 4; + unsigned short CSHPL3 : 4; +#else + unsigned short CSHPL3 : 4; + unsigned short CSHPL2 : 4; + unsigned short CSHPL1 : 4; + unsigned short CSHPL0 : 4; +#endif + } BIT; + } GTHPSR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WP0 : 1; + unsigned short WP1 : 1; + unsigned short WP2 : 1; + unsigned short WP3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short WP3 : 1; + unsigned short WP2 : 1; + unsigned short WP1 : 1; + unsigned short WP0 : 1; +#endif + } BIT; + } GTWP; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SYNC0 : 2; + unsigned short : 2; + unsigned short SYNC1 : 2; + unsigned short : 2; + unsigned short SYNC2 : 2; + unsigned short : 2; + unsigned short SYNC3 : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short SYNC3 : 2; + unsigned short : 2; + unsigned short SYNC2 : 2; + unsigned short : 2; + unsigned short SYNC1 : 2; + unsigned short : 2; + unsigned short SYNC0 : 2; +#endif + } BIT; + } GTSYNC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ETIPEN : 1; + unsigned short ETINEN : 1; + unsigned short : 11; + unsigned short GTENFCS : 2; + unsigned short GTETRGEN : 1; +#else + unsigned short GTETRGEN : 1; + unsigned short GTENFCS : 2; + unsigned short : 11; + unsigned short ETINEN : 1; + unsigned short ETIPEN : 1; +#endif + } BIT; + } GTETINT; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BD00 : 1; + unsigned short BD01 : 1; + unsigned short BD02 : 1; + unsigned short BD03 : 1; + unsigned short BD10 : 1; + unsigned short BD11 : 1; + unsigned short BD12 : 1; + unsigned short BD13 : 1; + unsigned short BD20 : 1; + unsigned short BD21 : 1; + unsigned short BD22 : 1; + unsigned short BD23 : 1; + unsigned short BD30 : 1; + unsigned short BD31 : 1; + unsigned short BD32 : 1; + unsigned short BD33 : 1; +#else + unsigned short BD33 : 1; + unsigned short BD32 : 1; + unsigned short BD31 : 1; + unsigned short BD30 : 1; + unsigned short BD23 : 1; + unsigned short BD22 : 1; + unsigned short BD21 : 1; + unsigned short BD20 : 1; + unsigned short BD13 : 1; + unsigned short BD12 : 1; + unsigned short BD11 : 1; + unsigned short BD10 : 1; + unsigned short BD03 : 1; + unsigned short BD02 : 1; + unsigned short BD01 : 1; + unsigned short BD00 : 1; +#endif + } BIT; + } GTBDR; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SWP0 : 1; + unsigned short SWP1 : 1; + unsigned short SWP2 : 1; + unsigned short SWP3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short SWP3 : 1; + unsigned short SWP2 : 1; + unsigned short SWP1 : 1; + unsigned short SWP0 : 1; +#endif + } BIT; + } GTSWP; +}; + +struct st_gpt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GTIOA : 6; + unsigned short OADFLT : 1; + unsigned short OAHLD : 1; + unsigned short GTIOB : 6; + unsigned short OBDFLT : 1; + unsigned short OBHLD : 1; +#else + unsigned short OBHLD : 1; + unsigned short OBDFLT : 1; + unsigned short GTIOB : 6; + unsigned short OAHLD : 1; + unsigned short OADFLT : 1; + unsigned short GTIOA : 6; +#endif + } BIT; + } GTIOR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GTINTA : 1; + unsigned short GTINTB : 1; + unsigned short GTINTC : 1; + unsigned short GTINTD : 1; + unsigned short GTINTE : 1; + unsigned short GTINTF : 1; + unsigned short GTINTPR : 2; + unsigned short : 3; + unsigned short EINT : 1; + unsigned short ADTRAUEN : 1; + unsigned short ADTRADEN : 1; + unsigned short ADTRBUEN : 1; + unsigned short ADTRBDEN : 1; +#else + unsigned short ADTRBDEN : 1; + unsigned short ADTRBUEN : 1; + unsigned short ADTRADEN : 1; + unsigned short ADTRAUEN : 1; + unsigned short EINT : 1; + unsigned short : 3; + unsigned short GTINTPR : 2; + unsigned short GTINTF : 1; + unsigned short GTINTE : 1; + unsigned short GTINTD : 1; + unsigned short GTINTC : 1; + unsigned short GTINTB : 1; + unsigned short GTINTA : 1; +#endif + } BIT; + } GTINTAD; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 3; + unsigned short : 5; + unsigned short TPCS : 2; + unsigned short : 2; + unsigned short CCLR : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short CCLR : 2; + unsigned short : 2; + unsigned short TPCS : 2; + unsigned short : 5; + unsigned short MD : 3; +#endif + } BIT; + } GTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CCRA : 2; + unsigned short CCRB : 2; + unsigned short PR : 2; + unsigned short CCRSWT : 1; + unsigned short : 1; + unsigned short ADTTA : 2; + unsigned short ADTDA : 1; + unsigned short : 1; + unsigned short ADTTB : 2; + unsigned short ADTDB : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short ADTDB : 1; + unsigned short ADTTB : 2; + unsigned short : 1; + unsigned short ADTDA : 1; + unsigned short ADTTA : 2; + unsigned short : 1; + unsigned short CCRSWT : 1; + unsigned short PR : 2; + unsigned short CCRB : 2; + unsigned short CCRA : 2; +#endif + } BIT; + } GTBER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short UD : 1; + unsigned short UDF : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short UDF : 1; + unsigned short UD : 1; +#endif + } BIT; + } GTUDC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITLA : 1; + unsigned short ITLB : 1; + unsigned short ITLC : 1; + unsigned short ITLD : 1; + unsigned short ITLE : 1; + unsigned short ITLF : 1; + unsigned short IVTC : 2; + unsigned short IVTT : 3; + unsigned short : 1; + unsigned short ADTAL : 1; + unsigned short : 1; + unsigned short ADTBL : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short ADTBL : 1; + unsigned short : 1; + unsigned short ADTAL : 1; + unsigned short : 1; + unsigned short IVTT : 3; + unsigned short IVTC : 2; + unsigned short ITLF : 1; + unsigned short ITLE : 1; + unsigned short ITLD : 1; + unsigned short ITLC : 1; + unsigned short ITLB : 1; + unsigned short ITLA : 1; +#endif + } BIT; + } GTITC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short ITCNT : 3; + unsigned short DTEF : 1; + unsigned short : 3; + unsigned short TUCF : 1; +#else + unsigned short TUCF : 1; + unsigned short : 3; + unsigned short DTEF : 1; + unsigned short ITCNT : 3; + unsigned short : 8; +#endif + } BIT; + } GTST; + unsigned short GTCNT; + unsigned short GTCCRA; + unsigned short GTCCRB; + unsigned short GTCCRC; + unsigned short GTCCRD; + unsigned short GTCCRE; + unsigned short GTCCRF; + unsigned short GTPR; + unsigned short GTPBR; + unsigned short GTPDBR; + char wk0[2]; + unsigned short GTADTRA; + unsigned short GTADTBRA; + unsigned short GTADTDBRA; + char wk1[2]; + unsigned short GTADTRB; + unsigned short GTADTBRB; + unsigned short GTADTDBRB; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NEA : 1; + unsigned short NEB : 1; + unsigned short NVA : 1; + unsigned short NVB : 1; + unsigned short NFS : 4; + unsigned short NFV : 1; + unsigned short : 3; + unsigned short SWN : 1; + unsigned short : 1; + unsigned short OAE : 1; + unsigned short OBE : 1; +#else + unsigned short OBE : 1; + unsigned short OAE : 1; + unsigned short : 1; + unsigned short SWN : 1; + unsigned short : 3; + unsigned short NFV : 1; + unsigned short NFS : 4; + unsigned short NVB : 1; + unsigned short NVA : 1; + unsigned short NEB : 1; + unsigned short NEA : 1; +#endif + } BIT; + } GTONCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TDE : 1; + unsigned short : 3; + unsigned short TDBUE : 1; + unsigned short TDBDE : 1; + unsigned short : 2; + unsigned short TDFER : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short TDFER : 1; + unsigned short : 2; + unsigned short TDBDE : 1; + unsigned short TDBUE : 1; + unsigned short : 3; + unsigned short TDE : 1; +#endif + } BIT; + } GTDTCR; + unsigned short GTDVU; + unsigned short GTDVD; + unsigned short GTDBU; + unsigned short GTDBD; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SOS : 2; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short SOS : 2; +#endif + } BIT; + } GTSOS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SOTR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short SOTR : 1; +#endif + } BIT; + } GTSOTR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT2 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT2 : 1; +#endif + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN8 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN15 : 1; +#else + unsigned char FLTEN15 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN8 : 1; +#endif + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL8 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL15 : 2; +#else + unsigned short FCLKSEL15 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL8 : 2; +#endif + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char ECCRAMST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ECCRAMST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char ECCRAMEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ECCRAMEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk14[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; + char wk16[107]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBE0; + char wk17[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL1; + char wk18[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBE0; + char wk19[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL1; + char wk20[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR0 : 1; + unsigned long CLR1 : 1; + unsigned long CLR2 : 1; + unsigned long CLR3 : 1; + unsigned long CLR4 : 1; + unsigned long CLR5 : 1; + unsigned long CLR6 : 1; + unsigned long CLR7 : 1; + unsigned long CLR8 : 1; + unsigned long CLR9 : 1; + unsigned long CLR10 : 1; + unsigned long CLR11 : 1; + unsigned long CLR12 : 1; + unsigned long CLR13 : 1; + unsigned long CLR14 : 1; + unsigned long CLR15 : 1; + unsigned long CLR16 : 1; + unsigned long CLR17 : 1; + unsigned long CLR18 : 1; + unsigned long CLR19 : 1; + unsigned long CLR20 : 1; + unsigned long CLR21 : 1; + unsigned long CLR22 : 1; + unsigned long CLR23 : 1; + unsigned long CLR24 : 1; + unsigned long CLR25 : 1; + unsigned long CLR26 : 1; + unsigned long CLR27 : 1; + unsigned long CLR28 : 1; + unsigned long CLR29 : 1; + unsigned long CLR30 : 1; + unsigned long CLR31 : 1; +#else + unsigned long CLR31 : 1; + unsigned long CLR30 : 1; + unsigned long CLR29 : 1; + unsigned long CLR28 : 1; + unsigned long CLR27 : 1; + unsigned long CLR26 : 1; + unsigned long CLR25 : 1; + unsigned long CLR24 : 1; + unsigned long CLR23 : 1; + unsigned long CLR22 : 1; + unsigned long CLR21 : 1; + unsigned long CLR20 : 1; + unsigned long CLR19 : 1; + unsigned long CLR18 : 1; + unsigned long CLR17 : 1; + unsigned long CLR16 : 1; + unsigned long CLR15 : 1; + unsigned long CLR14 : 1; + unsigned long CLR13 : 1; + unsigned long CLR12 : 1; + unsigned long CLR11 : 1; + unsigned long CLR10 : 1; + unsigned long CLR9 : 1; + unsigned long CLR8 : 1; + unsigned long CLR7 : 1; + unsigned long CLR6 : 1; + unsigned long CLR5 : 1; + unsigned long CLR4 : 1; + unsigned long CLR3 : 1; + unsigned long CLR2 : 1; + unsigned long CLR1 : 1; + unsigned long CLR0 : 1; +#endif + } BIT; + } GCRBE0; + char wk21[124]; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR0; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR1; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR2; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR3; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR4; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR5; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR6; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR7; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR8; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR9; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBRA; + char wk22[117]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR128; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR129; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR130; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR131; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR132; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR133; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR134; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR135; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR136; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR137; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR138; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR139; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR140; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR141; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR142; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR143; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR144; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR145; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR146; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR147; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR148; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR149; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR150; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR151; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR152; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR153; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR154; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR155; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR156; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR157; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR158; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR159; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR160; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR161; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR162; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR163; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR164; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR165; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR166; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR167; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR168; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR169; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR170; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR171; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR172; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR173; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR174; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR175; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR176; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR177; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR178; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR179; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR180; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR181; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR182; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR183; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR184; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR185; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR186; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR187; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR188; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR189; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR190; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR191; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR192; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR193; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR194; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR195; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR196; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR197; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR198; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR199; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR200; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR201; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR202; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR203; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR204; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR205; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR206; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR207; + char wk23[96]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL1; + char wk24[56]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL1; + char wk25[136]; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR0; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR1; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR2; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR3; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR4; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR5; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR6; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR7; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR8; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR9; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIARA; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIARB; + char wk26[196]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR208; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR209; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR210; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR211; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR212; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR213; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR214; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR215; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR216; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR217; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR218; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR219; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR220; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR221; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR222; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR223; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR224; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR225; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR226; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR227; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR228; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR229; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR230; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR231; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR232; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR233; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR234; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR235; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR236; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR237; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR238; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR239; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR240; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR241; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR242; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR243; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR244; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR245; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR246; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR247; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR248; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR249; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR250; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR251; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR252; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR253; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR254; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR255; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WPRC : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char WPRC : 1; +#endif + } BIT; + } SLIPRCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SELEXD0 : 1; + unsigned char SELEXD1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SELEXD1 : 1; + unsigned char SELEXD0 : 1; +#endif + } BIT; + } SELEXDR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +}; + +struct st_mmcif { + union { + unsigned long LONG; +// struct { +// unsigned long :1; +// unsigned long BOOT:1; +// unsigned long CMD:6; +// unsigned long RTYP:2; +// unsigned long RBSY:1; +// unsigned long :1; +// unsigned long WDAT:1; +// unsigned long DWEN:1; +// unsigned long CMLTE:1; +// unsigned long CMD12EN:1; +// unsigned long RIDXC:2; +// unsigned long RCRC7C:2; +// unsigned long :1; +// unsigned long CRC16C:1; +// unsigned long BOOTACK:1; +// unsigned long CRCSTE:1; +// unsigned long TBIT:1; +// unsigned long OPDM:1; +// unsigned long :2; +// unsigned long SBIT:1; +// unsigned long :1; +// unsigned long DATW:2; +// } BIT; + } CECMDSET; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARG : 32; +#else + unsigned long ARG : 32; +#endif + } BIT; + } CEARG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long C12ARG : 32; +#else + unsigned long C12ARG : 32; +#endif + } BIT; + } CEARGCMD12; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BREAK : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long BREAK : 1; +#endif + } BIT; + } CECMDCTRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BLKSIZ : 16; + unsigned long BLKCNT : 16; +#else + unsigned long BLKCNT : 16; + unsigned long BLKSIZ : 16; +#endif + } BIT; + } CEBLOCKSET; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long SRWDTO : 4; + unsigned long SRBSYTO : 4; + unsigned long SRSPTO : 2; + unsigned long : 2; + unsigned long CLKDIV : 4; + unsigned long : 4; + unsigned long CLKEN : 1; + unsigned long : 6; + unsigned long MMCBUSBSY : 1; +#else + unsigned long MMCBUSBSY : 1; + unsigned long : 6; + unsigned long CLKEN : 1; + unsigned long : 4; + unsigned long CLKDIV : 4; + unsigned long : 2; + unsigned long SRSPTO : 2; + unsigned long SRBSYTO : 4; + unsigned long SRWDTO : 4; + unsigned long : 4; +#endif + } BIT; + } CECLKCTRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long ATYP : 1; + unsigned long : 7; + unsigned long DMAREN : 1; + unsigned long DMAWEN : 1; + unsigned long DMATYP : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long DMATYP : 1; + unsigned long DMAWEN : 1; + unsigned long DMAREN : 1; + unsigned long : 7; + unsigned long ATYP : 1; + unsigned long : 16; +#endif + } BIT; + } CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSP12 : 32; +#else + unsigned long RSP12 : 32; +#endif + } BIT; + } CERESPCMD12; + union { + unsigned long LONG; +// struct { +// unsigned long DATA:32; +// } BIT; + } CEDATA; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long SBTDATTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTACKTO : 4; + unsigned long SBTCLKDIV : 4; +#else + unsigned long SBTCLKDIV : 4; + unsigned long SBTACKTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTDATTO : 4; + unsigned long : 16; +#endif + } BIT; + } CEBOOT; + union { + unsigned long LONG; +// struct { +// unsigned long :5; +// unsigned long CMD12DRE:1; +// unsigned long CMD12RBE:1; +// unsigned long CMD12CRE:1; +// unsigned long DTRANE:1; +// unsigned long BUFRE:1; +// unsigned long BUFWEN:1; +// unsigned long BUFREN:1; +// unsigned long :2; +// unsigned long RBSYE:1; +// unsigned long CRSPE:1; +// unsigned long CMDVIO:1; +// unsigned long BUFVIO:1; +// unsigned long :2; +// unsigned long WDATERR:1; +// unsigned long RDATERR:1; +// unsigned long RIDXERR:1; +// unsigned long RSPERR:1; +// unsigned long :3; +// unsigned long CRCSTO:1; +// unsigned long WDATTO:1; +// unsigned long RDATTO:1; +// unsigned long RBSYTO:1; +// unsigned long RSPTO:1; +// } BIT; + } CEINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRSPTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRDATTO : 1; + unsigned long MWDATTO : 1; + unsigned long MCRCSTO : 1; + unsigned long : 3; + unsigned long MRSPERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRDATERR : 1; + unsigned long MWDATERR : 1; + unsigned long : 2; + unsigned long MBUFVIO : 1; + unsigned long MCMDVIO : 1; + unsigned long MCRSPE : 1; + unsigned long MRBSYE : 1; + unsigned long : 2; + unsigned long MBUFREN : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFRE : 1; + unsigned long MDTRANE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12DRE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long MCMD12DRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MDTRANE : 1; + unsigned long MBUFRE : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFREN : 1; + unsigned long : 2; + unsigned long MRBSYE : 1; + unsigned long MCRSPE : 1; + unsigned long MCMDVIO : 1; + unsigned long MBUFVIO : 1; + unsigned long : 2; + unsigned long MWDATERR : 1; + unsigned long MRDATERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRSPERR : 1; + unsigned long : 3; + unsigned long MCRCSTO : 1; + unsigned long MWDATTO : 1; + unsigned long MRDATTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRSPTO : 1; +#endif + } BIT; + } CEINTEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RCVBLK : 16; + unsigned long DATSIG : 8; + unsigned long RSPIDX : 6; + unsigned long CMDSIG : 1; + unsigned long CMDSEQ : 1; +#else + unsigned long CMDSEQ : 1; + unsigned long CMDSIG : 1; + unsigned long RSPIDX : 6; + unsigned long DATSIG : 8; + unsigned long RCVBLK : 16; +#endif + } BIT; + } CEHOSTSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 5; + unsigned long BTDATTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTACKTO : 1; + unsigned long STRSPTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long DATBSYTO : 1; + unsigned long STRDATTO : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long BTACKEBE : 1; + unsigned long BTACKPATE : 1; + unsigned long RSPIDXE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RDATEBE : 1; + unsigned long CRCSTEBE : 1; + unsigned long RSPCRC7E : 1; + unsigned long AC12CRCE : 1; + unsigned long CRC16E : 1; + unsigned long CRCSTE : 1; +#else + unsigned long CRCSTE : 1; + unsigned long CRC16E : 1; + unsigned long AC12CRCE : 1; + unsigned long RSPCRC7E : 1; + unsigned long CRCSTEBE : 1; + unsigned long RDATEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPIDXE : 1; + unsigned long BTACKPATE : 1; + unsigned long BTACKEBE : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long STRDATTO : 1; + unsigned long DATBSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long STRSPTO : 1; + unsigned long BTACKTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTDATTO : 1; + unsigned long : 5; +#endif + } BIT; + } CEHOSTSTS2; + char wk2[32]; + union { + unsigned long LONG; +// struct { +// unsigned long :17; +// unsigned long CDSIG:1; +// unsigned long CDRISE:1; +// unsigned long CDFALL:1; +// unsigned long :6; +// unsigned long MCDRISE:1; +// unsigned long MCDFALL:1; +// } BIT; + } CEDETECT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 19; + unsigned long CLKMAIN : 1; + unsigned long : 1; + unsigned long RESNOUT : 1; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long RESNOUT : 1; + unsigned long : 1; + unsigned long CLKMAIN : 1; + unsigned long : 19; +#endif + } BIT; + } CEADDMODE; + char wk3[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VERSION : 16; + unsigned long : 15; + unsigned long SWRST : 1; +#else + unsigned long SWRST : 1; + unsigned long : 15; + unsigned long VERSION : 16; +#endif + } BIT; + } CEVERSION; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0S : 1; + unsigned char : 1; + unsigned char CS1S : 2; + unsigned char CS2S : 2; + unsigned char CS3S : 2; +#else + unsigned char CS3S : 2; + unsigned char CS2S : 2; + unsigned char CS1S : 2; + unsigned char : 1; + unsigned char CS0S : 1; +#endif + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS4S : 2; + unsigned char CS5S : 2; + unsigned char CS6S : 2; + unsigned char CS7S : 2; +#else + unsigned char CS7S : 2; + unsigned char CS6S : 2; + unsigned char CS5S : 2; + unsigned char CS4S : 2; +#endif + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char ADRHMS : 1; + unsigned char ADRHMS2 : 1; + unsigned char BCLKO : 1; + unsigned char DHE : 1; + unsigned char DH32E : 1; + unsigned char WR1BC1E : 1; + unsigned char WR32BC32E : 1; +#else + unsigned char WR32BC32E : 1; + unsigned char WR1BC1E : 1; + unsigned char DH32E : 1; + unsigned char DHE : 1; + unsigned char BCLKO : 1; + unsigned char ADRHMS2 : 1; + unsigned char ADRHMS : 1; + unsigned char ADRLE : 1; +#endif + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char ALES : 1; + unsigned char MDSDE : 1; + unsigned char : 1; + unsigned char DQM1E : 1; + unsigned char SDCLKE : 1; +#else + unsigned char SDCLKE : 1; + unsigned char DQM1E : 1; + unsigned char : 1; + unsigned char MDSDE : 1; + unsigned char ALES : 1; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif + } BIT; + } PFBCR1; + char wk1[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char PHYMODE0 : 1; + unsigned char PHYMODE1 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PHYMODE1 : 1; + unsigned char PHYMODE0 : 1; + unsigned char : 4; +#endif + } BIT; + } PFENET; + char wk2[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P56PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P60PFS; + char wk9[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P67PFS; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P83PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P96PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P97PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF2PFS; + char wk12[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PF5PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG7PFS; + char wk14[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ3PFS; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ5PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4COR : 3; +#endif + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4CNT : 3; +#endif + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST8 : 1; + unsigned char : 2; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 2; + unsigned char CST8 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCH7 : 1; + unsigned char SCH6 : 1; + unsigned char : 1; + unsigned char SCH4 : 1; + unsigned char SCH3 : 1; + unsigned char SCH2 : 1; + unsigned char SCH1 : 1; + unsigned char SCH0 : 1; +#else + unsigned char SCH0 : 1; + unsigned char SCH1 : 1; + unsigned char SCH2 : 1; + unsigned char SCH3 : 1; + unsigned char SCH4 : 1; + unsigned char : 1; + unsigned char SCH6 : 1; + unsigned char SCH7 : 1; +#endif + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE6B : 1; + unsigned char OE7A : 1; + unsigned char OE7B : 1; + unsigned char OE6D : 1; + unsigned char OE7C : 1; + unsigned char OE7D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE7D : 1; + unsigned char OE7C : 1; + unsigned char OE6D : 1; + unsigned char OE7B : 1; + unsigned char OE7A : 1; + unsigned char OE6B : 1; +#endif + } BIT; + } TOERB; + char wk12[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCOR : 3; + unsigned char T7VEN : 1; + unsigned char T6ACOR : 3; + unsigned char T6AEN : 1; +#else + unsigned char T6AEN : 1; + unsigned char T6ACOR : 3; + unsigned char T7VEN : 1; + unsigned char T7VCOR : 3; +#endif + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCNT : 3; + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; + unsigned char T7VCNT : 3; +#endif + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7COR : 3; +#endif + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7CNT : 3; +#endif + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char CST6 : 1; + unsigned char CST7 : 1; +#else + unsigned char CST7 : 1; + unsigned char CST6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char SYNC6 : 1; + unsigned char SYNC7 : 1; +#else + unsigned char SYNC7 : 1; + unsigned char SYNC6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERB; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 5; + unsigned char TTGE2 : 1; +#else + unsigned char TTGE2 : 1; + unsigned char : 5; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LWA : 1; + unsigned char PHCKSEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PHCKSEL : 1; + unsigned char LWA : 1; +#endif + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR3; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR4; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +}; + +struct st_mtu6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CE2B : 1; + unsigned char CE2A : 1; + unsigned char CE1B : 1; + unsigned char CE1A : 1; + unsigned char CE0D : 1; + unsigned char CE0C : 1; + unsigned char CE0B : 1; + unsigned char CE0A : 1; +#else + unsigned char CE0A : 1; + unsigned char CE0B : 1; + unsigned char CE0C : 1; + unsigned char CE0D : 1; + unsigned char CE1A : 1; + unsigned char CE1B : 1; + unsigned char CE2A : 1; + unsigned char CE2B : 1; +#endif + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR6; +}; + +struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITA6AE : 1; + unsigned short DT7BE : 1; + unsigned short UT7BE : 1; + unsigned short DT7AE : 1; + unsigned short UT7AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT7AE : 1; + unsigned short DT7AE : 1; + unsigned short UT7BE : 1; + unsigned short DT7BE : 1; + unsigned short ITA6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITB7VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR7; +}; + +struct st_mtu8 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR8; + char wk0[871]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +}; + +struct st_pdc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKE : 1; + unsigned long VPS : 1; + unsigned long HPS : 1; + unsigned long PRST : 1; + unsigned long DFIE : 1; + unsigned long FEIE : 1; + unsigned long OVIE : 1; + unsigned long UDRIE : 1; + unsigned long VERIE : 1; + unsigned long HERIE : 1; + unsigned long PCKOE : 1; + unsigned long PCKDIV : 3; + unsigned long EDS : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long EDS : 1; + unsigned long PCKDIV : 3; + unsigned long PCKOE : 1; + unsigned long HERIE : 1; + unsigned long VERIE : 1; + unsigned long UDRIE : 1; + unsigned long OVIE : 1; + unsigned long FEIE : 1; + unsigned long DFIE : 1; + unsigned long PRST : 1; + unsigned long HPS : 1; + unsigned long VPS : 1; + unsigned long PCKE : 1; +#endif + } BIT; + } PCCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCE : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long PCE : 1; +#endif + } BIT; + } PCCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBSY : 1; + unsigned long FEMPF : 1; + unsigned long FEF : 1; + unsigned long OVRF : 1; + unsigned long UDRF : 1; + unsigned long VERF : 1; + unsigned long HERF : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long HERF : 1; + unsigned long VERF : 1; + unsigned long UDRF : 1; + unsigned long OVRF : 1; + unsigned long FEF : 1; + unsigned long FEMPF : 1; + unsigned long FBSY : 1; +#endif + } BIT; + } PCSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VSYNC : 1; + unsigned long HSYNC : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long HSYNC : 1; + unsigned long VSYNC : 1; +#endif + } BIT; + } PCMONR; + union { + unsigned long LONG; + } PCDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VST : 12; + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; + unsigned long VST : 12; +#endif + } BIT; + } VCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HST : 12; + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; + unsigned long HST : 12; +#endif + } BIT; + } HCR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short : 6; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short : 6; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE4M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE4M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE2 : 1; + unsigned short OCE2 : 1; + unsigned short : 5; + unsigned short OSF2 : 1; +#else + unsigned short OSF2 : 1; + unsigned short : 5; + unsigned short OCE2 : 1; + unsigned short OIE2 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE3 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE3 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTUCH34HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH0HIZ : 1; + unsigned char GPT01HIZ : 1; + unsigned char GPT23HIZ : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char GPT23HIZ : 1; + unsigned char GPT01HIZ : 1; + unsigned char MTUCH0HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0AZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0DZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MTU0DZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0AZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU7BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU6BDZE : 1; + unsigned short : 5; + unsigned short MTU4BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU3BDZE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short MTU3BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU4BDZE : 1; + unsigned short : 5; + unsigned short MTU6BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU7BDZE : 1; +#endif + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GPT0ABZE : 1; + unsigned short GPT1ABZE : 1; + unsigned short : 6; + unsigned short GPT2ABZE : 1; + unsigned short GPT3ABZE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short GPT3ABZE : 1; + unsigned short GPT2ABZE : 1; + unsigned short : 6; + unsigned short GPT1ABZE : 1; + unsigned short GPT0ABZE : 1; +#endif + } BIT; + } POECR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 2; + unsigned short IC2ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC5ADDMT34ZE : 1; + unsigned short : 3; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC5ADDMT67ZE : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short IC5ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 3; + unsigned short IC5ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC2ADDMT34ZE : 1; + unsigned short : 2; +#endif + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short IC5ADDMT0ZE : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short IC5ADDMT0ZE : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short : 1; +#endif + } BIT; + } POECR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short IC1ADDGPT01ZE : 1; + unsigned short IC2ADDGPT01ZE : 1; + unsigned short IC3ADDGPT01ZE : 1; + unsigned short : 1; + unsigned short IC5ADDGPT01ZE : 1; + unsigned short : 3; + unsigned short IC1ADDGPT23ZE : 1; + unsigned short IC2ADDGPT23ZE : 1; + unsigned short IC3ADDGPT23ZE : 1; + unsigned short IC4ADDGPT23ZE : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short IC4ADDGPT23ZE : 1; + unsigned short IC3ADDGPT23ZE : 1; + unsigned short IC2ADDGPT23ZE : 1; + unsigned short IC1ADDGPT23ZE : 1; + unsigned short : 3; + unsigned short IC5ADDGPT01ZE : 1; + unsigned short : 1; + unsigned short IC3ADDGPT01ZE : 1; + unsigned short IC2ADDGPT01ZE : 1; + unsigned short IC1ADDGPT01ZE : 1; + unsigned short : 1; +#endif + } BIT; + } POECR6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE10M : 2; + unsigned short : 6; + unsigned short PIE4 : 1; + unsigned short POE10E : 1; + unsigned short : 2; + unsigned short POE10F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE10F : 1; + unsigned short : 2; + unsigned short POE10E : 1; + unsigned short PIE4 : 1; + unsigned short : 6; + unsigned short POE10M : 2; +#endif + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE11M : 2; + unsigned short : 6; + unsigned short PIE5 : 1; + unsigned short POE11E : 1; + unsigned short : 2; + unsigned short POE11F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE11F : 1; + unsigned short : 2; + unsigned short POE11E : 1; + unsigned short PIE5 : 1; + unsigned short : 6; + unsigned short POE11M : 2; +#endif + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 9; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 9; +#endif + } BIT; + } ICSR6; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0ASEL : 4; + unsigned char G0BSEL : 4; +#else + unsigned char G0BSEL : 4; + unsigned char G0ASEL : 4; +#endif + } BIT; + } G0SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G1ASEL : 4; + unsigned char G1BSEL : 4; +#else + unsigned char G1BSEL : 4; + unsigned char G1ASEL : 4; +#endif + } BIT; + } G1SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G2ASEL : 4; + unsigned char G2BSEL : 4; +#else + unsigned char G2BSEL : 4; + unsigned char G2ASEL : 4; +#endif + } BIT; + } G2SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G3ASEL : 4; + unsigned char G3BSEL : 4; +#else + unsigned char G3BSEL : 4; + unsigned char G3ASEL : 4; +#endif + } BIT; + } G3SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0ASEL : 4; + unsigned char M0BSEL : 4; +#else + unsigned char M0BSEL : 4; + unsigned char M0ASEL : 4; +#endif + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0CSEL : 4; + unsigned char M0DSEL : 4; +#else + unsigned char M0DSEL : 4; + unsigned char M0CSEL : 4; +#endif + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M3BSEL : 4; + unsigned char M3DSEL : 4; +#else + unsigned char M3DSEL : 4; + unsigned char M3BSEL : 4; +#endif + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4ASEL : 4; + unsigned char M4CSEL : 4; +#else + unsigned char M4CSEL : 4; + unsigned char M4ASEL : 4; +#endif + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4BSEL : 4; + unsigned char M4DSEL : 4; +#else + unsigned char M4DSEL : 4; + unsigned char M4BSEL : 4; +#endif + } BIT; + } M4SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M3G0SEL : 1; + unsigned char M4G1SEL : 1; + unsigned char M4G2SEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char M4G2SEL : 1; + unsigned char M4G1SEL : 1; + unsigned char M3G0SEL : 1; +#endif + } BIT; + } MGSELR; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER8 : 1; + unsigned char NDER9 : 1; + unsigned char NDER10 : 1; + unsigned char NDER11 : 1; + unsigned char NDER12 : 1; + unsigned char NDER13 : 1; + unsigned char NDER14 : 1; + unsigned char NDER15 : 1; +#else + unsigned char NDER15 : 1; + unsigned char NDER14 : 1; + unsigned char NDER13 : 1; + unsigned char NDER12 : 1; + unsigned char NDER11 : 1; + unsigned char NDER10 : 1; + unsigned char NDER9 : 1; + unsigned char NDER8 : 1; +#endif + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER0 : 1; + unsigned char NDER1 : 1; + unsigned char NDER2 : 1; + unsigned char NDER3 : 1; + unsigned char NDER4 : 1; + unsigned char NDER5 : 1; + unsigned char NDER6 : 1; + unsigned char NDER7 : 1; +#else + unsigned char NDER7 : 1; + unsigned char NDER6 : 1; + unsigned char NDER5 : 1; + unsigned char NDER4 : 1; + unsigned char NDER3 : 1; + unsigned char NDER2 : 1; + unsigned char NDER1 : 1; + unsigned char NDER0 : 1; +#endif + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD8 : 1; + unsigned char POD9 : 1; + unsigned char POD10 : 1; + unsigned char POD11 : 1; + unsigned char POD12 : 1; + unsigned char POD13 : 1; + unsigned char POD14 : 1; + unsigned char POD15 : 1; +#else + unsigned char POD15 : 1; + unsigned char POD14 : 1; + unsigned char POD13 : 1; + unsigned char POD12 : 1; + unsigned char POD11 : 1; + unsigned char POD10 : 1; + unsigned char POD9 : 1; + unsigned char POD8 : 1; +#endif + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD0 : 1; + unsigned char POD1 : 1; + unsigned char POD2 : 1; + unsigned char POD3 : 1; + unsigned char POD4 : 1; + unsigned char POD5 : 1; + unsigned char POD6 : 1; + unsigned char POD7 : 1; +#else + unsigned char POD7 : 1; + unsigned char POD6 : 1; + unsigned char POD5 : 1; + unsigned char POD4 : 1; + unsigned char POD3 : 1; + unsigned char POD2 : 1; + unsigned char POD1 : 1; + unsigned char POD0 : 1; +#endif + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char NDR12 : 1; + unsigned char NDR13 : 1; + unsigned char NDR14 : 1; + unsigned char NDR15 : 1; +#else + unsigned char NDR15 : 1; + unsigned char NDR14 : 1; + unsigned char NDR13 : 1; + unsigned char NDR12 : 1; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char NDR4 : 1; + unsigned char NDR5 : 1; + unsigned char NDR6 : 1; + unsigned char NDR7 : 1; +#else + unsigned char NDR7 : 1; + unsigned char NDR6 : 1; + unsigned char NDR5 : 1; + unsigned char NDR4 : 1; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PTRSL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PTRSL : 1; +#endif + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER24 : 1; + unsigned char NDER25 : 1; + unsigned char NDER26 : 1; + unsigned char NDER27 : 1; + unsigned char NDER28 : 1; + unsigned char NDER29 : 1; + unsigned char NDER30 : 1; + unsigned char NDER31 : 1; +#else + unsigned char NDER31 : 1; + unsigned char NDER30 : 1; + unsigned char NDER29 : 1; + unsigned char NDER28 : 1; + unsigned char NDER27 : 1; + unsigned char NDER26 : 1; + unsigned char NDER25 : 1; + unsigned char NDER24 : 1; +#endif + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER16 : 1; + unsigned char NDER17 : 1; + unsigned char NDER18 : 1; + unsigned char NDER19 : 1; + unsigned char NDER20 : 1; + unsigned char NDER21 : 1; + unsigned char NDER22 : 1; + unsigned char NDER23 : 1; +#else + unsigned char NDER23 : 1; + unsigned char NDER22 : 1; + unsigned char NDER21 : 1; + unsigned char NDER20 : 1; + unsigned char NDER19 : 1; + unsigned char NDER18 : 1; + unsigned char NDER17 : 1; + unsigned char NDER16 : 1; +#endif + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD24 : 1; + unsigned char POD25 : 1; + unsigned char POD26 : 1; + unsigned char POD27 : 1; + unsigned char POD28 : 1; + unsigned char POD29 : 1; + unsigned char POD30 : 1; + unsigned char POD31 : 1; +#else + unsigned char POD31 : 1; + unsigned char POD30 : 1; + unsigned char POD29 : 1; + unsigned char POD28 : 1; + unsigned char POD27 : 1; + unsigned char POD26 : 1; + unsigned char POD25 : 1; + unsigned char POD24 : 1; +#endif + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD16 : 1; + unsigned char POD17 : 1; + unsigned char POD18 : 1; + unsigned char POD19 : 1; + unsigned char POD20 : 1; + unsigned char POD21 : 1; + unsigned char POD22 : 1; + unsigned char POD23 : 1; +#else + unsigned char POD23 : 1; + unsigned char POD22 : 1; + unsigned char POD21 : 1; + unsigned char POD20 : 1; + unsigned char POD19 : 1; + unsigned char POD18 : 1; + unsigned char POD17 : 1; + unsigned char POD16 : 1; +#endif + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char NDR28 : 1; + unsigned char NDR29 : 1; + unsigned char NDR30 : 1; + unsigned char NDR31 : 1; +#else + unsigned char NDR31 : 1; + unsigned char NDR30 : 1; + unsigned char NDR29 : 1; + unsigned char NDR28 : 1; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char NDR20 : 1; + unsigned char NDR21 : 1; + unsigned char NDR22 : 1; + unsigned char NDR23 : 1; +#else + unsigned char NDR23 : 1; + unsigned char NDR22 : 1; + unsigned char NDR21 : 1; + unsigned char NDR20 : 1; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif + } BIT; + } NDRL2; +}; + +struct st_ptpedmac { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SWR : 1; + unsigned long : 3; + unsigned long DL : 2; + unsigned long DE : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long DE : 1; + unsigned long DL : 2; + unsigned long : 3; + unsigned long SWR : 1; +#endif + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long TR : 1; +#endif + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RR : 1; +#endif + } BIT; + } EDRRR; + char wk2[4]; + unsigned long TDLAR; + char wk3[4]; + unsigned long RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TYPE : 4; + unsigned long PVER : 1; + unsigned long : 2; + unsigned long RPORT : 1; + unsigned long MACE : 1; + unsigned long : 7; + unsigned long RFOF : 1; + unsigned long RDE : 1; + unsigned long FR : 1; + unsigned long TFUF : 1; + unsigned long TDE : 1; + unsigned long TC : 1; + unsigned long : 1; + unsigned long ADE : 1; + unsigned long RFCOF : 1; + unsigned long : 1; + unsigned long TABT : 1; + unsigned long : 3; + unsigned long TWB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWB : 1; + unsigned long : 3; + unsigned long TABT : 1; + unsigned long : 1; + unsigned long RFCOF : 1; + unsigned long ADE : 1; + unsigned long : 1; + unsigned long TC : 1; + unsigned long TDE : 1; + unsigned long TFUF : 1; + unsigned long FR : 1; + unsigned long RDE : 1; + unsigned long RFOF : 1; + unsigned long : 7; + unsigned long MACE : 1; + unsigned long RPORT : 1; + unsigned long : 2; + unsigned long PVER : 1; + unsigned long TYPE : 4; +#endif + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long PVERIP : 1; + unsigned long : 2; + unsigned long RPORTIP : 1; + unsigned long MACEIP : 1; + unsigned long : 7; + unsigned long RFOFIP : 1; + unsigned long RDEIP : 1; + unsigned long FRIP : 1; + unsigned long TFUFIP : 1; + unsigned long TDEIP : 1; + unsigned long TCIP : 1; + unsigned long : 1; + unsigned long ADEIP : 1; + unsigned long RFCOFIP : 1; + unsigned long : 1; + unsigned long TABTIP : 1; + unsigned long : 3; + unsigned long TWBIP : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWBIP : 1; + unsigned long : 3; + unsigned long TABTIP : 1; + unsigned long : 1; + unsigned long RFCOFIP : 1; + unsigned long ADEIP : 1; + unsigned long : 1; + unsigned long TCIP : 1; + unsigned long TDEIP : 1; + unsigned long TFUFIP : 1; + unsigned long FRIP : 1; + unsigned long RDEIP : 1; + unsigned long RFOFIP : 1; + unsigned long : 7; + unsigned long MACEIP : 1; + unsigned long RPORTIP : 1; + unsigned long : 2; + unsigned long PVERIP : 1; + unsigned long : 4; +#endif + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TYPECE : 4; + unsigned long PVERCE : 1; + unsigned long : 2; + unsigned long RPORTCE : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RPORTCE : 1; + unsigned long : 2; + unsigned long PVERCE : 1; + unsigned long TYPECE : 4; +#endif + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MFC : 16; +#endif + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TFT : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long TFT : 11; +#endif + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFD : 5; + unsigned long : 3; + unsigned long TFD : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TFD : 5; + unsigned long : 3; + unsigned long RFD : 5; +#endif + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RNR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RNR : 1; +#endif + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UNDER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long UNDER : 16; +#endif + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long OVER : 16; +#endif + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long ELB : 1; +#endif + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDO : 3; + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; + unsigned long RFDO : 3; +#endif + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PADR : 6; + unsigned long : 10; + unsigned long PADS : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long PADS : 2; + unsigned long : 10; + unsigned long PADR : 6; +#endif + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIS : 1; + unsigned long : 3; + unsigned long TIM : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long TIM : 1; + unsigned long : 3; + unsigned long TIS : 1; +#endif + } BIT; + } TRIMD; + char wk13[72]; + unsigned long RBWAR; + unsigned long RDFAR; + char wk14[4]; + unsigned long TBRAR; + unsigned long TDFAR; +}; + +struct st_qspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSLP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SSLP : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char IO2FV : 1; + unsigned char IO3FV : 1; + unsigned char : 1; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 1; + unsigned char IO3FV : 1; + unsigned char IO2FV : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char SPSSLF : 1; + unsigned char SPTEF : 1; + unsigned char TREND : 1; + unsigned char SPRFF : 1; +#else + unsigned char SPRFF : 1; + unsigned char TREND : 1; + unsigned char SPTEF : 1; + unsigned char SPSSLF : 1; + unsigned char : 4; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSC : 2; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSS : 2; +#endif + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPBR0 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR7 : 1; +#else + unsigned char SPBR7 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR0 : 1; +#endif + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TXDMY : 1; +#else + unsigned char TXDMY : 1; + unsigned char : 7; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXTRG : 3; + unsigned char TXTRGEX : 1; + unsigned char TXTRG : 2; + unsigned char RXRST : 1; + unsigned char TXRST : 1; +#else + unsigned char TXRST : 1; + unsigned char RXRST : 1; + unsigned char TXTRG : 2; + unsigned char TXTRGEX : 1; + unsigned char RXTRG : 3; +#endif + } BIT; + } SPBFCR; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RXBC : 6; + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; + unsigned short RXBC : 6; +#endif + } BIT; + } SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +}; + +struct st_ram { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMODE : 2; +#endif + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RAMERR : 1; +#endif + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMPRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char RAMPRCR : 1; +#endif + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif + } BIT; + } RAMECAD; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char FMPE : 1; +#else + unsigned char FMPE : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RCKSEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RCKSEL : 1; +#endif + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RFC : 1; +#endif + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 16; +#else + unsigned short RFC : 16; +#endif + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR2; + char wk21[13]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP0 : 8; +#else + unsigned char BCNCP0 : 8; +#endif + } BIT; + } BCNT0CP0; + }; + char wk22[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP0 : 8; +#else + unsigned char BCNCP0 : 8; +#endif + } BIT; + } BCNT1CP0; + }; + char wk23[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP0 : 8; +#else + unsigned char BCNCP0 : 8; +#endif + } BIT; + } BCNT2CP0; + }; + char wk24[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP0 : 8; +#else + unsigned char BCNCP0 : 8; +#endif + } BIT; + } BCNT3CP0; + }; + char wk25[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP0; + char wk26[5]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP1 : 8; +#else + unsigned char BCNCP1 : 8; +#endif + } BIT; + } BCNT0CP1; + }; + char wk27[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP1 : 8; +#else + unsigned char BCNCP1 : 8; +#endif + } BIT; + } BCNT1CP1; + }; + char wk28[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP1 : 8; +#else + unsigned char BCNCP1 : 8; +#endif + } BIT; + } BCNT2CP1; + }; + char wk29[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP1 : 8; +#else + unsigned char BCNCP1 : 8; +#endif + } BIT; + } BCNT3CP1; + }; + char wk30[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP1; + char wk31[5]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP2 : 8; +#else + unsigned char BCNCP2 : 8; +#endif + } BIT; + } BCNT0CP2; + }; + char wk32[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP2 : 8; +#else + unsigned char BCNCP2 : 8; +#endif + } BIT; + } BCNT1CP2; + }; + char wk33[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP2 : 8; +#else + unsigned char BCNCP2 : 8; +#endif + } BIT; + } BCNT2CP2; + }; + char wk34[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNCP2 : 8; +#else + unsigned char BCNCP2 : 8; +#endif + } BIT; + } BCNT3CP2; + }; + char wk35[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA0 : 16; +#else + unsigned short ANSA0 : 16; +#endif + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS0 : 16; +#else + unsigned short ADS0 : 16; +#endif + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 2; + unsigned char : 5; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 5; + unsigned char ADC : 2; +#endif + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB0 : 16; +#else + unsigned short ANSB0 : 16; +#endif + } BIT; + } ADANSB0; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 2; + unsigned short AD : 12; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short AD : 12; + unsigned short : 2; +#endif + } BIT; + } ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[48]; + unsigned char ADSSTR0; + char wk8[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SSTSH : 8; + unsigned short SHANS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SHANS : 3; + unsigned short SSTSH : 8; +#endif + } BIT; + } ADSHCR; + char wk9[11]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk9a[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHMD : 1; +#endif + } BIT; + } ADSHMSR; + char wk10[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk11[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk12[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char WCMPE : 1; + unsigned char CMPIE : 1; +#else + unsigned char CMPIE : 1; + unsigned char WCMPE : 1; + unsigned char : 6; +#endif + } BIT; + } ADCMPCR; + char wk13[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPS0 : 16; +#else + unsigned short CMPS0 : 16; +#endif + } BIT; + } ADCMPANSR0; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPL0 : 16; +#else + unsigned short CMPL0 : 16; +#endif + } BIT; + } ADCMPLR0; + char wk15[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPF0 : 16; +#else + unsigned short CMPF0 : 16; +#endif + } BIT; + } ADCMPSR0; +}; + +struct st_s12ad1 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA0 : 16; +#else + unsigned short ANSA0 : 16; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSA1 : 5; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS0 : 16; +#else + unsigned short ADS0 : 16; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ADS1 : 5; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 2; + unsigned char : 5; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 5; + unsigned char ADC : 2; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short TSSB : 1; + unsigned short OCSB : 1; + unsigned short : 1; + unsigned short EXSEL : 2; + unsigned short EXOEN : 1; +#else + unsigned short EXOEN : 1; + unsigned short EXSEL : 2; + unsigned short : 1; + unsigned short OCSB : 1; + unsigned short TSSB : 1; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB0 : 16; +#else + unsigned short ANSB0 : 16; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSB1 : 5; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[22]; + unsigned char ADSSTR0; + unsigned char ADSSTRL; + char wk3[14]; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + char wk4[1]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk5[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char WCMPE : 1; + unsigned char CMPIE : 1; +#else + unsigned char CMPIE : 1; + unsigned char WCMPE : 1; + unsigned char : 6; +#endif + } BIT; + } ADCMPCR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTS : 1; + unsigned char CMPSOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSOC : 1; + unsigned char CMPSTS : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTS : 1; + unsigned char CMPLOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOC : 1; + unsigned char CMPLTS : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPS0 : 16; +#else + unsigned short CMPS0 : 16; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPS1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPS1 : 5; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPL0 : 16; +#else + unsigned short CMPL0 : 16; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPL1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPL1 : 5; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPF0 : 16; +#else + unsigned short CMPF0 : 16; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPF1 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPF1 : 5; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPFTS : 1; + unsigned char CMPFOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPFOC : 1; + unsigned char CMPFTS : 1; +#endif + } BIT; + } ADCMPSER; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_scifa { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short STOP : 1; + unsigned short PM : 1; + unsigned short PE : 1; + unsigned short CHR : 1; + unsigned short CM : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CM : 1; + unsigned short CHR : 1; + unsigned short PE : 1; + unsigned short PM : 1; + unsigned short STOP : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif + } BIT; + } SMR; +// unsigned char BRR; + union { + unsigned char BRR; + unsigned char MDDR; + }; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKE : 2; + unsigned short TEIE : 1; + unsigned short REIE : 1; + unsigned short RE : 1; + unsigned short TE : 1; + unsigned short RIE : 1; + unsigned short TIE : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short TIE : 1; + unsigned short RIE : 1; + unsigned short TE : 1; + unsigned short RE : 1; + unsigned short REIE : 1; + unsigned short TEIE : 1; + unsigned short CKE : 2; +#endif + } BIT; + } SCR; + unsigned char FTDR; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DR : 1; + unsigned short RDF : 1; + unsigned short PER : 1; + unsigned short FER : 1; + unsigned short BRK : 1; + unsigned short TDFE : 1; + unsigned short TEND : 1; + unsigned short ER : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ER : 1; + unsigned short TEND : 1; + unsigned short TDFE : 1; + unsigned short BRK : 1; + unsigned short FER : 1; + unsigned short PER : 1; + unsigned short RDF : 1; + unsigned short DR : 1; +#endif + } BIT; + } FSR; + unsigned char FRDR; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LOOP : 1; + unsigned short RFRST : 1; + unsigned short TFRST : 1; + unsigned short MCE : 1; + unsigned short TTRG : 2; + unsigned short RTRG : 2; + unsigned short RSTRG : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short RSTRG : 3; + unsigned short RTRG : 2; + unsigned short TTRG : 2; + unsigned short MCE : 1; + unsigned short TFRST : 1; + unsigned short RFRST : 1; + unsigned short LOOP : 1; +#endif + } BIT; + } FCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short R : 5; + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; + unsigned short R : 5; +#endif + } BIT; + } FDR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SPB2DT : 1; + unsigned short SPB2IO : 1; + unsigned short SCKDT : 1; + unsigned short SCKIO : 1; + unsigned short CTS2DT : 1; + unsigned short CTS2IO : 1; + unsigned short RTS2DT : 1; + unsigned short RTS2IO : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RTS2IO : 1; + unsigned short RTS2DT : 1; + unsigned short CTS2IO : 1; + unsigned short CTS2DT : 1; + unsigned short SCKIO : 1; + unsigned short SCKDT : 1; + unsigned short SPB2IO : 1; + unsigned short SPB2DT : 1; +#endif + } BIT; + } SPTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ORER : 1; + unsigned short : 1; + unsigned short FER : 4; + unsigned short : 2; + unsigned short PER : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short PER : 4; + unsigned short : 2; + unsigned short FER : 4; + unsigned short : 1; + unsigned short ORER : 1; +#endif + } BIT; + } LSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ABCS0 : 1; + unsigned char : 1; + unsigned char NFEN : 1; + unsigned char DIR : 1; + unsigned char MDDRS : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char BGDM : 1; +#else + unsigned char BGDM : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char MDDRS : 1; + unsigned char DIR : 1; + unsigned char NFEN : 1; + unsigned char : 1; + unsigned char ABCS0 : 1; +#endif + } BIT; + } SEMR; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TFTC : 5; + unsigned short : 2; + unsigned short TTRGS : 1; + unsigned short RFTC : 5; + unsigned short : 2; + unsigned short RTRGS : 1; +#else + unsigned short RTRGS : 1; + unsigned short : 2; + unsigned short RFTC : 5; + unsigned short TTRGS : 1; + unsigned short : 2; + unsigned short TFTC : 5; +#endif + } BIT; + } FTCR; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STP : 1; + unsigned long : 7; + unsigned long SDBLKCNTEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long SDBLKCNTEN : 1; + unsigned long : 7; + unsigned long STP : 1; +#endif + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPENDM : 1; + unsigned long : 1; + unsigned long ACENDM : 1; + unsigned long SDCDRMM : 1; + unsigned long SDCDINM : 1; + unsigned long : 3; + unsigned long SDD3RMM : 1; + unsigned long SDD3INM : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long SDD3INM : 1; + unsigned long SDD3RMM : 1; + unsigned long : 3; + unsigned long SDCDINM : 1; + unsigned long SDCDRMM : 1; + unsigned long ACENDM : 1; + unsigned long : 1; + unsigned long RSPENDM : 1; +#endif + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDEM : 1; + unsigned long CRCEM : 1; + unsigned long ENDEM : 1; + unsigned long DTTOM : 1; + unsigned long ILWM : 1; + unsigned long ILRM : 1; + unsigned long RSPTOM : 1; + unsigned long : 1; + unsigned long BREM : 1; + unsigned long BWEM : 1; + unsigned long : 5; + unsigned long ILAM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILAM : 1; + unsigned long : 5; + unsigned long BWEM : 1; + unsigned long BREM : 1; + unsigned long : 1; + unsigned long RSPTOM : 1; + unsigned long ILRM : 1; + unsigned long ILWM : 1; + unsigned long DTTOM : 1; + unsigned long ENDEM : 1; + unsigned long CRCEM : 1; + unsigned long CMDEM : 1; +#endif + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLKSEL : 8; + unsigned long CLKEN : 1; + unsigned long CLKCTRLEN : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long CLKCTRLEN : 1; + unsigned long CLKEN : 1; + unsigned long CLKSEL : 8; +#endif + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LEN : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long LEN : 10; +#endif + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTOP : 4; + unsigned long TOP : 4; + unsigned long : 7; + unsigned long WIDTH : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long WIDTH : 1; + unsigned long : 7; + unsigned long TOP : 4; + unsigned long CTOP : 4; +#endif + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE0 : 1; + unsigned long CMDE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long RSPLENE1 : 1; + unsigned long RDLENE : 1; + unsigned long CRCLENE : 1; + unsigned long : 2; + unsigned long RSPCRCE0 : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RDCRCE : 1; + unsigned long CRCTKE : 1; + unsigned long CRCTK : 3; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CRCTK : 3; + unsigned long CRCTKE : 1; + unsigned long RDCRCE : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RSPCRCE0 : 1; + unsigned long : 2; + unsigned long CRCLENE : 1; + unsigned long RDLENE : 1; + unsigned long RSPLENE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long CMDE1 : 1; + unsigned long CMDE0 : 1; +#endif + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long BSYTO1 : 1; + unsigned long RDTO : 1; + unsigned long CRCTO : 1; + unsigned long CRCBSYTO : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long CRCBSYTO : 1; + unsigned long CRCTO : 1; + unsigned long RDTO : 1; + unsigned long BSYTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long RSPTO0 : 1; +#endif + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INTEN : 1; + unsigned long : 1; + unsigned long RWREQ : 1; + unsigned long : 5; + unsigned long IOABT : 1; + unsigned long C52PUB : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long C52PUB : 1; + unsigned long IOABT : 1; + unsigned long : 5; + unsigned long RWREQ : 1; + unsigned long : 1; + unsigned long INTEN : 1; +#endif + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQM : 1; + unsigned long : 13; + unsigned long EXPUB52M : 1; + unsigned long EXWTM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWTM : 1; + unsigned long EXPUB52M : 1; + unsigned long : 13; + unsigned long IOIRQM : 1; +#endif + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long DMAEN : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long DMAEN : 1; + unsigned long : 1; +#endif + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDRST : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SDRST : 1; +#endif + } BIT; + } SDRST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IP1 : 8; + unsigned long IP2 : 4; + unsigned long : 2; + unsigned long CLKRAT : 1; + unsigned long CPRM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CPRM : 1; + unsigned long CLKRAT : 1; + unsigned long : 2; + unsigned long IP2 : 4; + unsigned long IP1 : 8; +#endif + } BIT; + } SDVER; + char wk10[24]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long BWSWP : 1; + unsigned long BRSWP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long BRSWP : 1; + unsigned long BWSWP : 1; + unsigned long : 6; +#endif + } BIT; + } SDSWAP; +}; + +struct st_smci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; +}; + +struct st_src { + union { + unsigned long LONG; + } SRCFCTR[5552]; + char wk0[2352]; + union { + unsigned long LONG; + } SRCID; + union { + unsigned long LONG; + } SRCOD; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IFTRG : 2; + unsigned short : 6; + unsigned short IEN : 1; + unsigned short IED : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short IED : 1; + unsigned short IEN : 1; + unsigned short : 6; + unsigned short IFTRG : 2; +#endif + } BIT; + } SRCIDCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OFTRG : 2; + unsigned short : 6; + unsigned short OEN : 1; + unsigned short OED : 1; + unsigned short OCH : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short OCH : 1; + unsigned short OED : 1; + unsigned short OEN : 1; + unsigned short : 6; + unsigned short OFTRG : 2; +#endif + } BIT; + } SRCODCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OFS : 3; + unsigned short : 1; + unsigned short IFS : 4; + unsigned short CL : 1; + unsigned short FL : 1; + unsigned short OVEN : 1; + unsigned short UDEN : 1; + unsigned short SRCEN : 1; + unsigned short CEEN : 1; + unsigned short : 1; + unsigned short FICRAE : 1; +#else + unsigned short FICRAE : 1; + unsigned short : 1; + unsigned short CEEN : 1; + unsigned short SRCEN : 1; + unsigned short UDEN : 1; + unsigned short OVEN : 1; + unsigned short FL : 1; + unsigned short CL : 1; + unsigned short IFS : 4; + unsigned short : 1; + unsigned short OFS : 3; +#endif + } BIT; + } SRCCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OINT : 1; + unsigned short IINT : 1; + unsigned short OVF : 1; + unsigned short UDF : 1; + unsigned short FLF : 1; + unsigned short CEF : 1; + unsigned short : 1; + unsigned short IFDN : 4; + unsigned short OFDN : 5; +#else + unsigned short OFDN : 5; + unsigned short IFDN : 4; + unsigned short : 1; + unsigned short CEF : 1; + unsigned short FLF : 1; + unsigned short UDF : 1; + unsigned short OVF : 1; + unsigned short IINT : 1; + unsigned short OINT : 1; +#endif + } BIT; + } SRCSTAT; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REN : 1; + unsigned long TEN : 1; + unsigned long : 1; + unsigned long MUEN : 1; + unsigned long CKDV : 4; + unsigned long DEL : 1; + unsigned long PDTA : 1; + unsigned long SDTA : 1; + unsigned long SPDP : 1; + unsigned long SWSP : 1; + unsigned long SCKP : 1; + unsigned long SWSD : 1; + unsigned long SCKD : 1; + unsigned long SWL : 3; + unsigned long DWL : 3; + unsigned long CHNL : 2; + unsigned long : 1; + unsigned long IIEN : 1; + unsigned long ROIEN : 1; + unsigned long RUIEN : 1; + unsigned long TOIEN : 1; + unsigned long TUIEN : 1; + unsigned long CKS : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CKS : 1; + unsigned long TUIEN : 1; + unsigned long TOIEN : 1; + unsigned long RUIEN : 1; + unsigned long ROIEN : 1; + unsigned long IIEN : 1; + unsigned long : 1; + unsigned long CHNL : 2; + unsigned long DWL : 3; + unsigned long SWL : 3; + unsigned long SCKD : 1; + unsigned long SWSD : 1; + unsigned long SCKP : 1; + unsigned long SWSP : 1; + unsigned long SPDP : 1; + unsigned long SDTA : 1; + unsigned long PDTA : 1; + unsigned long DEL : 1; + unsigned long CKDV : 4; + unsigned long MUEN : 1; + unsigned long : 1; + unsigned long TEN : 1; + unsigned long REN : 1; +#endif + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IDST : 1; + unsigned long RSWNO : 1; + unsigned long RCHNO : 2; + unsigned long TSWNO : 1; + unsigned long TCHNO : 2; + unsigned long : 18; + unsigned long IIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long TUIRQ : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long IIRQ : 1; + unsigned long : 18; + unsigned long TCHNO : 2; + unsigned long TSWNO : 1; + unsigned long RCHNO : 2; + unsigned long RSWNO : 1; + unsigned long IDST : 1; +#endif + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFRST : 1; + unsigned long TFRST : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; + unsigned long RTRG : 2; + unsigned long TTRG : 2; + unsigned long : 8; + unsigned long SSIRST : 1; + unsigned long : 14; + unsigned long AUCKE : 1; +#else + unsigned long AUCKE : 1; + unsigned long : 14; + unsigned long SSIRST : 1; + unsigned long : 8; + unsigned long TTRG : 2; + unsigned long RTRG : 2; + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long TFRST : 1; + unsigned long RFRST : 1; +#endif + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDF : 1; + unsigned long : 7; + unsigned long RDC : 4; + unsigned long : 4; + unsigned long TDE : 1; + unsigned long : 7; + unsigned long TDC : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TDC : 4; + unsigned long : 7; + unsigned long TDE : 1; + unsigned long : 4; + unsigned long RDC : 4; + unsigned long : 7; + unsigned long RDF : 1; +#endif + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long CONT : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CONT : 1; + unsigned long : 8; +#endif + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short UBTS : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short UBTS : 1; + unsigned short : 5; +#endif + } BIT; + } MDSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 5; + unsigned short ECCRAME : 1; + unsigned short SBYRAME : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SBYRAME : 1; + unsigned short ECCRAME : 1; + unsigned short : 5; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPA0 : 1; + unsigned long MSTPA1 : 1; + unsigned long : 2; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA9 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA11 : 1; + unsigned long : 1; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 4; + unsigned long MSTPA24 : 1; + unsigned long : 2; + unsigned long MSTPA27 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA29 : 1; + unsigned long : 1; + unsigned long ACSE : 1; +#else + unsigned long ACSE : 1; + unsigned long : 1; + unsigned long MSTPA29 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA27 : 1; + unsigned long : 2; + unsigned long MSTPA24 : 1; + unsigned long : 4; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 1; + unsigned long MSTPA11 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA9 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 2; + unsigned long MSTPA1 : 1; + unsigned long MSTPA0 : 1; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long MSTPB1 : 1; + unsigned long MSTPB2 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB8 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB12 : 1; + unsigned long : 1; + unsigned long MSTPB14 : 1; + unsigned long MSTPB15 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB15 : 1; + unsigned long MSTPB14 : 1; + unsigned long : 1; + unsigned long MSTPB12 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB8 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB2 : 1; + unsigned long MSTPB1 : 1; + unsigned long MSTPB0 : 1; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 5; + unsigned long MSTPC6 : 1; + unsigned long MSTPC7 : 1; + unsigned long : 9; + unsigned long MSTPC17 : 1; + unsigned long : 1; + unsigned long MSTPC19 : 1; + unsigned long : 3; + unsigned long MSTPC23 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC23 : 1; + unsigned long : 3; + unsigned long MSTPC19 : 1; + unsigned long : 1; + unsigned long MSTPC17 : 1; + unsigned long : 9; + unsigned long MSTPC7 : 1; + unsigned long MSTPC6 : 1; + unsigned long : 5; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPD0 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD7 : 1; + unsigned long : 6; + unsigned long MSTPD14 : 1; + unsigned long MSTPD15 : 1; + unsigned long : 3; + unsigned long MSTPD19 : 1; + unsigned long : 1; + unsigned long MSTPD21 : 1; + unsigned long : 1; + unsigned long MSTPD23 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MSTPD23 : 1; + unsigned long : 1; + unsigned long MSTPD21 : 1; + unsigned long : 1; + unsigned long MSTPD19 : 1; + unsigned long : 3; + unsigned long MSTPD15 : 1; + unsigned long MSTPD14 : 1; + unsigned long : 6; + unsigned long MSTPD7 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD0 : 1; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long PCKC : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 2; + unsigned long PSTOP0 : 1; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long PSTOP0 : 1; + unsigned long : 2; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long PCKC : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short UCK : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short UCK : 4; + unsigned short : 4; +#endif + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 2; + unsigned short PLLSRCSEL : 1; + unsigned short : 3; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 3; + unsigned short PLLSRCSEL : 1; + unsigned short : 2; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk3[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif + } BIT; + } BCKCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char SOOVF : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char ILCOVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILCOVF : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char SOOVF : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk7[94]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 8; +#else + unsigned char MSTS : 8; +#endif + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSTS : 8; +#else + unsigned char SSTS : 8; +#endif + } BIT; + } SOSCWTCR; + char wk8[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk9[1]; + unsigned short SWRR; + char wk10[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk11[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk12a[25104]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MEMWAIT : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MEMWAIT : 1; +#endif + } BIT; + } MEMWAIT; + char wk12b[23660]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEEPCUT : 2; + unsigned char : 4; + unsigned char IOKEEP : 1; + unsigned char DPSBY : 1; +#else + unsigned char DPSBY : 1; + unsigned char IOKEEP : 1; + unsigned char : 4; + unsigned char DEEPCUT : 2; +#endif + } BIT; + } DPSBYCR; + char wk13[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ7E : 1; +#else + unsigned char DIRQ7E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ0E : 1; +#endif + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ15E : 1; +#else + unsigned char DIRQ15E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ8E : 1; +#endif + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IE : 1; + unsigned char DLVD2IE : 1; + unsigned char DRTCIIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DNMIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DUSBIE : 1; +#else + unsigned char DUSBIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DNMIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DRTCIIE : 1; + unsigned char DLVD2IE : 1; + unsigned char DLVD1IE : 1; +#endif + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIE : 1; +#endif + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ7F : 1; +#else + unsigned char DIRQ7F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ0F : 1; +#endif + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ15F : 1; +#else + unsigned char DIRQ15F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ8F : 1; +#endif + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IF : 1; + unsigned char DLVD2IF : 1; + unsigned char DRTCIIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DNMIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DUSBIF : 1; +#else + unsigned char DUSBIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DNMIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DRTCIIF : 1; + unsigned char DLVD2IF : 1; + unsigned char DLVD1IF : 1; +#endif + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIF : 1; +#endif + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ7EG : 1; +#else + unsigned char DIRQ7EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ0EG : 1; +#endif + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ15EG : 1; +#else + unsigned char DIRQ15EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ8EG : 1; +#endif + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1EG : 1; + unsigned char DLVD2EG : 1; + unsigned char : 2; + unsigned char DNMIEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DRIICCEG : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DRIICCEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DNMIEG : 1; + unsigned char : 2; + unsigned char DLVD2EG : 1; + unsigned char DLVD1EG : 1; +#endif + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIEG : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIEG : 1; +#endif + } BIT; + } DPSIEGR3; + char wk14[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 3; + unsigned char DPSRSTF : 1; +#else + unsigned char DPSRSTF : 1; + unsigned char : 3; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOFXIN : 1; + unsigned char : 3; + unsigned char MODRV2 : 2; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV2 : 2; + unsigned char : 3; + unsigned char MOFXIN : 1; +#endif + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOPCNT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOCOPCNT : 1; +#endif + } BIT; + } HOCOPCR; + char wk16[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 5; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 4; +#else + unsigned char LVD2LVL : 4; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk17[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1FSAMP : 2; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char LVD1FSAMP : 2; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2FSAMP : 2; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char LVD2FSAMP : 2; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; + char wk18[4]; + unsigned char DPSBKR[32]; +}; + +struct st_temps { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char TSOE : 1; + unsigned char : 2; + unsigned char TSEN : 1; +#else + unsigned char TSEN : 1; + unsigned char : 2; + unsigned char TSOE : 1; + unsigned char : 4; +#endif + } BIT; + } TSCR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char ADTE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADTE : 1; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpua { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; + unsigned char CST5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CST5 : 1; + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SYNC5 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRPC0 : 1; + unsigned long RPUE0 : 1; + unsigned long : 1; + unsigned long DRPD0 : 1; + unsigned long FIXPHY0 : 1; + unsigned long : 11; + unsigned long DP0 : 1; + unsigned long DM0 : 1; + unsigned long : 2; + unsigned long DOVCA0 : 1; + unsigned long DOVCB0 : 1; + unsigned long : 1; + unsigned long DVBSTS0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBSTS0 : 1; + unsigned long : 1; + unsigned long DOVCB0 : 1; + unsigned long DOVCA0 : 1; + unsigned long : 2; + unsigned long DM0 : 1; + unsigned long DP0 : 1; + unsigned long : 11; + unsigned long FIXPHY0 : 1; + unsigned long DRPD0 : 1; + unsigned long : 1; + unsigned long RPUE0 : 1; + unsigned long SRPC0 : 1; +#endif + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DPINTE0 : 1; + unsigned long DMINTE0 : 1; + unsigned long : 2; + unsigned long DOVRCRAE0 : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long : 1; + unsigned long DVBSE0 : 1; + unsigned long : 8; + unsigned long DPINT0 : 1; + unsigned long DMINT0 : 1; + unsigned long : 2; + unsigned long DOVRCRA0 : 1; + unsigned long DOVRCRB0 : 1; + unsigned long : 1; + unsigned long DVBINT0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBINT0 : 1; + unsigned long : 1; + unsigned long DOVRCRB0 : 1; + unsigned long DOVRCRA0 : 1; + unsigned long : 2; + unsigned long DMINT0 : 1; + unsigned long DPINT0 : 1; + unsigned long : 8; + unsigned long DVBSE0 : 1; + unsigned long : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long DOVRCRAE0 : 1; + unsigned long : 2; + unsigned long DMINTE0 : 1; + unsigned long DPINTE0 : 1; +#endif + } BIT; + } DPUSR1R; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :3; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short :3; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 2; + unsigned short SOFEA : 1; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short SOFEA : 1; + unsigned short : 2; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short DVCHG : 1; +#else + unsigned short DVCHG : 1; + unsigned short : 15; +#endif + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBADDR : 7; + unsigned short : 1; + unsigned short STSRECOV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short STSRECOV : 4; + unsigned short : 1; + unsigned short USBADDR : 7; +#endif + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD5; + char wk16[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SLEWR00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWF01 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long SLEWF01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWR00 : 1; +#endif + } BIT; + } PHYSLEW; +}; + +struct st_usba { + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short CNEN:1; +// unsigned short HSE:1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short :3; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short BWAIT:4; +// } BIT; + } BUSWAIT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 2; + unsigned short SOFEA : 1; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short SOFEA : 1; + unsigned short : 2; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLLLOCK : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short PLLLOCK : 1; +#endif + } BIT; + } PLLSTA; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk0[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short UTST:4; +// } BIT; + } TESTMODE; + char wk1[6]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } CFIFO; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } D0FIFO; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } D1FIFO; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :2; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } CFIFOCTR; + char wk2[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :1; +// unsigned short L1RSMENDE:1; +// unsigned short LPMENDE:1; +// unsigned short :1; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE:1; +// } BIT; + } INTENB1; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short INTL:1; +// unsigned short EDGESTS:1; +// } BIT; + } SOFCFG; + union { + unsigned short WORD; +// struct { +// unsigned short HSEB:1; +// unsigned short :5; +// unsigned short REPSEL:2; +// unsigned short :2; +// unsigned short CLKSEL:2; +// unsigned short CDPEN:1; +// unsigned short :1; +// unsigned short PLLRESET:1; +// unsigned short DIRPD:1; +// } BIT; + } PHYSET; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :1; +// unsigned short L1RSMEND:1; +// unsigned short LPMEND:1; +// unsigned short :1; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT:1; +// } BIT; + } INTSTS1; + char wk4[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPEBRDY:10; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPENRDY:10; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPEBEMP:10; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short UFRNM : 3; + unsigned short : 13; +#else + unsigned short : 13; + unsigned short UFRNM : 3; +#endif + } BIT; + } UFRMNUM; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBADDR : 7; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short USBADDR : 7; +#endif + } BIT; + } USBADDR; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short CNTMD:1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk6[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk7[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short CNTMD:1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short BUFSIZE:5; +// unsigned short :2; +// unsigned short BUFNMB:8; +// } BIT; + } PIPEBUF; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :1; +// unsigned short MXPS:11; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk8[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE1TRE; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRNCNT : 16; +#else + unsigned short TRNCNT : 16; +#endif + } BIT; + } PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE2TRE; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRNCNT : 16; +#else + unsigned short TRNCNT : 16; +#endif + } BIT; + } PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE3TRE; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRNCNT : 16; +#else + unsigned short TRNCNT : 16; +#endif + } BIT; + } PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE4TRE; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRNCNT : 16; +#else + unsigned short TRNCNT : 16; +#endif + } BIT; + } PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE5TRE; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRNCNT : 16; +#else + unsigned short TRNCNT : 16; +#endif + } BIT; + } PIPE5TRN; + char wk9[44]; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD5; + char wk10[36]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short HWUPM:1; +// } BIT; + } LPCTRL; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short SUSPENDM:1; +// } BIT; + } LPSTS; + char wk11[60]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PDDETSTS:1; +// unsigned short CHGDETSTS:1; +// unsigned short :3; +// unsigned short VDMSRCE:1; +// unsigned short IDPSINKE:1; +// unsigned short VDPSRCE:1; +// unsigned short IDMSINKE:1; +// unsigned short IDPSRCE:1; +// } BIT; + } BCCTRL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short L1EXTMD:1; +// unsigned short :2; +// unsigned short HIRDTHR:4; +// unsigned short DVSQ:4; +// unsigned short L1NEGOMD:1; +// unsigned short L1RESPMD:2; +// unsigned short L1RESPEN:1; +// } BIT; + } PL1CTRL1; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short RWEMON:1; +// unsigned short HIRDMON:4; +// } BIT; + } PL1CTRL2; + union { + unsigned short WORD; +// struct { +// unsigned short :13; +// unsigned short L1STATUS:2; +// unsigned short L1REQ:1; +// } BIT; + } HL1CTRL1; + union { + unsigned short WORD; +// struct { +// unsigned short BESL:1; +// unsigned short :2; +// unsigned short L1RWE:1; +// unsigned short HIRD:4; +// unsigned short :4; +// unsigned short L1ADDR:4; +// } BIT; + } HL1CTRL2; + char wk13[20]; + union { + unsigned long LONG; +// struct { +// unsigned long :8; +// unsigned long DVBSTSHM:1; +// unsigned long :1; +// unsigned long DOVCBHM:1; +// unsigned long DOVCAHM:1; +// } BIT; + } DPUSR0R; + union { + unsigned long LONG; +// struct { +// unsigned long :8; +// unsigned long DVBSTSH:1; +// unsigned long :1; +// unsigned long DOVCBH:1; +// unsigned long DOVCAH:1; +// unsigned long :12; +// unsigned long DVBSTSHE:1; +// unsigned long :1; +// unsigned long DOVCBHE:1; +// unsigned long DOVCAHE:1; +// } BIT; + } DPUSR1R; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_RAM_RAMERR=18, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMTW0_CMWI0, +IR_CMTW1_CMWI1, +IR_USBA_D0FIFO2,IR_USBA_D1FIFO2, +IR_USB0_D0FIFO0,IR_USB0_D1FIFO0, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1, +IR_QSPI_SPRI=42,IR_QSPI_SPTI, +IR_SDHI_SBFAI, +IR_MMCIF_MBFAI, +IR_SSI0_SSITXI0,IR_SSI0_SSIRXI0, +IR_SSI1_SSIRTI1, +IR_SRC_IDEI=50,IR_SRC_ODFI, +IR_RIIC0_RXI0,IR_RIIC0_TXI0, +IR_RIIC2_RXI2,IR_RIIC2_TXI2, +IR_SCI0_RXI0=58,IR_SCI0_TXI0, +IR_SCI1_RXI1,IR_SCI1_TXI1, +IR_SCI2_RXI2,IR_SCI2_TXI2, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI3_RXI3,IR_SCI3_TXI3, +IR_SCI4_RXI4,IR_SCI4_TXI4, +IR_SCI5_RXI5,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_USBA_USBAR, +IR_IWDT_IWUNI, +IR_WDT_WUNI, +IR_PDC_PCDFI, +IR_SCI7_RXI7,IR_SCI7_TXI7, +IR_SCIFA8_RXIF8,IR_SCIFA8_TXIF8, +IR_SCIFA9_RXIF9,IR_SCIFA9_TXIF9, +IR_SCIFA10_RXIF10,IR_SCIFA10_TXIF10, +IR_ICU_GROUPBE0,IR_ICU_GROUPBL0=110,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_SCIFA11_RXIF11,IR_SCIFA11_TXIF11, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OST, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132, +IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137, +IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142, +IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147, +IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152, +IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157, +IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162, +IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167, +IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172, +IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177, +IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182, +IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187, +IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192, +IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197, +IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202, +IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207, +IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212, +IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217, +IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222, +IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227, +IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232, +IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242, +IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247, +IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252, +IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +}; + +enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USBA_D0FIFO2,DTCE_USBA_D1FIFO2, +DTCE_USB0_D0FIFO0,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI=42,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSI0_SSITXI0,DTCE_SSI0_SSIRXI0, +DTCE_SSI1_SSIRTI1, +DTCE_SRC_IDEI=50,DTCE_SRC_ODFI, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI=97, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCIFA8_RXIF8,DTCE_SCIFA8_TXIF8, +DTCE_SCIFA9_RXIF9,DTCE_SCIFA9_TXIF9, +DTCE_SCIFA10_RXIF10,DTCE_SCIFA10_TXIF10, +DTCE_SCIFA11_RXIF11=114,DTCE_SCIFA11_TXIF11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMTW0_CMWI0=0x03, +IER_CMTW1_CMWI1=0x03, +IER_USBA_D0FIFO2=0x04,IER_USBA_D1FIFO2=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05, +IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05, +IER_SDHI_SBFAI=0x05, +IER_MMCIF_MBFAI=0x05, +IER_SSI0_SSITXI0=0x05,IER_SSI0_SSIRXI0=0x05, +IER_SSI1_SSIRTI1=0x06, +IER_SRC_IDEI=0x06,IER_SRC_ODFI=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06, +IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A, +IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_USBA_USBAR=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_PDC_PCDFI=0x0C, +IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C, +IER_SCIFA8_RXIF8=0x0C,IER_SCIFA8_TXIF8=0x0C, +IER_SCIFA9_RXIF9=0x0C,IER_SCIFA9_TXIF9=0x0C, +IER_SCIFA10_RXIF10=0x0D,IER_SCIFA10_TXIF10=0x0D, +IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_SCIFA11_RXIF11=0x0E,IER_SCIFA11_TXIF11=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OST=0x0F, +IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F, +IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10, +IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11, +IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11, +IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12, +IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13, +IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13, +IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14, +IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14, +IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15, +IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16, +IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16, +IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17, +IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18, +IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18, +IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19, +IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A, +IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B, +IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B, +IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C, +IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D, +IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D, +IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E, +IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F, +IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMTW0_CMWI0=6, +IPR_CMTW1_CMWI1=7, +IPR_USBA_D0FIFO2=32,IPR_USBA_D1FIFO2=33, +IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41, +IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43, +IPR_SDHI_SBFAI=44, +IPR_MMCIF_MBFAI=45, +IPR_SSI0_SSITXI0=46,IPR_SSI0_SSIRXI0=47, +IPR_SSI1_SSIRTI1=48, +IPR_SRC_IDEI=50,IPR_SRC_ODFI=51, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55, +IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81, +IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_USBA_USBAR=94, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_PDC_PCDFI=97, +IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99, +IPR_SCIFA8_RXIF8=100,IPR_SCIFA8_TXIF8=101, +IPR_SCIFA9_RXIF9=102,IPR_SCIFA9_TXIF9=103, +IPR_SCIFA10_RXIF10=104,IPR_SCIFA10_TXIF10=105, +IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_SCIFA11_RXIF11=114,IPR_SCIFA11_TXIF11=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OST=125, +IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127, +IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132, +IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137, +IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142, +IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147, +IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152, +IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157, +IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162, +IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167, +IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172, +IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177, +IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182, +IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187, +IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192, +IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197, +IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202, +IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212, +IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217, +IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222, +IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227, +IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232, +IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242, +IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247, +IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252, +IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USBA_D0FIFO2 IEN0 +#define IEN_USBA_D1FIFO2 IEN1 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SSI0_SSIRXI0 IEN7 +#define IEN_SSI1_SSIRTI1 IEN0 +#define IEN_SRC_IDEI IEN2 +#define IEN_SRC_ODFI IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_USBA_USBAR IEN6 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCIFA8_RXIF8 IEN4 +#define IEN_SCIFA8_TXIF8 IEN5 +#define IEN_SCIFA9_RXIF9 IEN6 +#define IEN_SCIFA9_TXIF9 IEN7 +#define IEN_SCIFA10_RXIF10 IEN0 +#define IEN_SCIFA10_TXIF10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCIFA11_RXIF11 IEN2 +#define IEN_SCIFA11_TXIF11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OST IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USBA_D0FIFO2 32 +#define VECT_USBA_D1FIFO2 33 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_SSI0_SSITXI0 46 +#define VECT_SSI0_SSIRXI0 47 +#define VECT_SSI1_SSIRTI1 48 +#define VECT_SRC_IDEI 50 +#define VECT_SRC_ODFI 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_USBA_USBAR 94 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCIFA8_RXIF8 100 +#define VECT_SCIFA8_TXIF8 101 +#define VECT_SCIFA9_RXIF9 102 +#define VECT_SCIFA9_TXIF9 103 +#define VECT_SCIFA10_RXIF10 104 +#define VECT_SCIFA10_TXIF10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCIFA11_RXIF11 114 +#define VECT_SCIFA11_TXIF11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OST 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPT SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_EDMAC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_USBA SYSTEM.MSTPCRB.BIT.MSTPB12 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCIFA8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCIFA9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCIFA10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCIFA11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_ECCRAM SYSTEM.MSTPCRC.BIT.MSTPC6 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SRC SYSTEM.MSTPCRD.BIT.MSTPD23 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_SSI1 SYSTEM.MSTPCRD.BIT.MSTPD14 + +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI7_TEI7 IS14 +#define IS_SCI7_ERI7 IS15 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRF IS26 +#define IS_CAC_MENDF IS27 +#define IS_CAC_OVFF IS28 +#define IS_DOC_DOPCF IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SRC_PCERI IS0 +#define IS_SRC_OVF IS1 +#define IS_SRC_CEF IS2 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_SSI0_SSIF0 IS17 +#define IS_SSI1_SSIF1 IS18 +#define IS_S12AD0_S12CMPI0 IS20 +#define IS_S12AD1_S12CMPI1 IS22 +#define IS_SCIFA8_TEIF8 IS0 +#define IS_SCIFA8_ERIF8 IS1 +#define IS_SCIFA8_BRIF8 IS2 +#define IS_SCIFA8_DRIF8 IS3 +#define IS_SCIFA9_TEIF9 IS4 +#define IS_SCIFA9_ERIF9 IS5 +#define IS_SCIFA9_BRIF9 IS6 +#define IS_SCIFA9_DRIF9 IS7 +#define IS_SCIFA10_TEIF10 IS8 +#define IS_SCIFA10_ERIF10 IS9 +#define IS_SCIFA10_BRIF10 IS10 +#define IS_SCIFA10_DRIF10 IS11 +#define IS_SCIFA11_TEIF11 IS12 +#define IS_SCIFA11_ERIF11 IS13 +#define IS_SCIFA11_BRIF11 IS14 +#define IS_SCIFA11_DRIF11 IS15 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_EPTPC_MINT IS0 +#define IS_PRPEDMAC_PINT IS1 +#define IS_EDMAC0_EINT0 IS4 +#define IS_EDMAC1_EINT1 IS5 + +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI7_TEI7 EN14 +#define EN_SCI7_ERI7 EN15 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRF EN26 +#define EN_CAC_MENDF EN27 +#define EN_CAC_OVFF EN28 +#define EN_DOC_DOPCF EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SRC_PCERI EN0 +#define EN_SRC_OVF EN1 +#define EN_SRC_CEF EN2 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_SSI0_SSIF0 EN17 +#define EN_SSI1_SSIF1 EN18 +#define EN_S12AD0_S12CMPI0 EN20 +#define EN_S12AD1_S12CMPI1 EN22 +#define EN_SCIFA8_TEIF8 EN0 +#define EN_SCIFA8_ERIF8 EN1 +#define EN_SCIFA8_BRIF8 EN2 +#define EN_SCIFA8_DRIF8 EN3 +#define EN_SCIFA9_TEIF9 EN4 +#define EN_SCIFA9_ERIF9 EN5 +#define EN_SCIFA9_BRIF9 EN6 +#define EN_SCIFA9_DRIF9 EN7 +#define EN_SCIFA10_TEIF10 EN8 +#define EN_SCIFA10_ERIF10 EN9 +#define EN_SCIFA10_BRIF10 EN10 +#define EN_SCIFA10_DRIF10 EN11 +#define EN_SCIFA11_TEIF11 EN12 +#define EN_SCIFA11_ERIF11 EN13 +#define EN_SCIFA11_BRIF11 EN14 +#define EN_SCIFA11_DRIF11 EN15 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_EPTPC_MINT EN0 +#define EN_PRPEDMAC_PINT EN1 +#define EN_EDMAC0_EINT0 EN4 +#define EN_EDMAC1_EINT1 EN5 + +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 +#define CLR_RSPI1_SPII1 CLR18 +#define CLR_RSPI1_SPEI1 CLR19 + +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_CAN2_ERS2 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI7_TEI7 GENBL0 +#define GEN_SCI7_ERI7 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRF GENBL0 +#define GEN_CAC_MENDF GENBL0 +#define GEN_CAC_OVFF GENBL0 +#define GEN_DOC_DOPCF GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SRC_PCERI GENBL1 +#define GEN_SRC_OVF GENBL1 +#define GEN_SRC_CEF GENBL1 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_SSI0_SSIF0 GENBL1 +#define GEN_SSI1_SSIF1 GENBL1 +#define GEN_S12AD0_S12CMPI0 GENBL1 +#define GEN_S12AD1_S12CMPI1 GENBL1 +#define GEN_SCIFA8_TEIF8 GENAL0 +#define GEN_SCIFA8_ERIF8 GENAL0 +#define GEN_SCIFA8_BRIF8 GENAL0 +#define GEN_SCIFA8_DRIF8 GENAL0 +#define GEN_SCIFA9_TEIF9 GENAL0 +#define GEN_SCIFA9_ERIF9 GENAL0 +#define GEN_SCIFA9_BRIF9 GENAL0 +#define GEN_SCIFA9_DRIF9 GENAL0 +#define GEN_SCIFA10_TEIF10 GENAL0 +#define GEN_SCIFA10_ERIF10 GENAL0 +#define GEN_SCIFA10_BRIF10 GENAL0 +#define GEN_SCIFA10_DRIF10 GENAL0 +#define GEN_SCIFA11_TEIF11 GENAL0 +#define GEN_SCIFA11_ERIF11 GENAL0 +#define GEN_SCIFA11_BRIF11 GENAL0 +#define GEN_SCIFA11_DRIF11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_EPTPC_MINT GENAL1 +#define GEN_PRPEDMAC_PINT GENAL1 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_EDMAC1_EINT1 GENAL1 + +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_CAN2_ERS2 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI7_TEI7 GRPBL0 +#define GRP_SCI7_ERI7 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRF GRPBL0 +#define GRP_CAC_MENDF GRPBL0 +#define GRP_CAC_OVFF GRPBL0 +#define GRP_DOC_DOPCF GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SRC_PCERI GRPBL1 +#define GRP_SRC_OVF GRPBL1 +#define GRP_SRC_CEF GRPBL1 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_SSI0_SSIF0 GRPBL1 +#define GRP_SSI1_SSIF1 GRPBL1 +#define GRP_S12AD0_S12CMPI0 GRPBL1 +#define GRP_S12AD1_S12CMPI1 GRPBL1 +#define GRP_SCIFA8_TEIF8 GRPAL0 +#define GRP_SCIFA8_ERIF8 GRPAL0 +#define GRP_SCIFA8_BRIF8 GRPAL0 +#define GRP_SCIFA8_DRIF8 GRPAL0 +#define GRP_SCIFA9_TEIF9 GRPAL0 +#define GRP_SCIFA9_ERIF9 GRPAL0 +#define GRP_SCIFA9_BRIF9 GRPAL0 +#define GRP_SCIFA9_DRIF9 GRPAL0 +#define GRP_SCIFA10_TEIF10 GRPAL0 +#define GRP_SCIFA10_ERIF10 GRPAL0 +#define GRP_SCIFA10_BRIF10 GRPAL0 +#define GRP_SCIFA10_DRIF10 GRPAL0 +#define GRP_SCIFA11_TEIF11 GRPAL0 +#define GRP_SCIFA11_ERIF11 GRPAL0 +#define GRP_SCIFA11_BRIF11 GRPAL0 +#define GRP_SCIFA11_DRIF11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_EPTPC_MINT GRPAL1 +#define GRP_PRPEDMAC_PINT GRPAL1 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_EDMAC1_EINT1 GRPAL1 + +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 +#define GCR_CAN2_ERS2 GCRBE0 +#define GCR_RSPI1_SPII1 GCRAL0 +#define GCR_RSPI1_SPEI1 GCRAL0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define CAN1 (*(volatile struct st_can *)0x91200) +#define CAN2 (*(volatile struct st_can *)0x92200) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw *)0x94280) +#define CRC (*(volatile struct st_crc *)0x88280) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 *)0x821C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ECCRAM (*(volatile struct st_eccram *)0x812C0) +#define EDMAC0 (*(volatile struct st_edmac *)0xC0000) +#define EDMAC1 (*(volatile struct st_edmac *)0xC0200) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define EPTPC (*(volatile struct st_eptpc *)0xC0500) +#define EPTPC0 (*(volatile struct st_eptpc0 *)0xC4800) +#define EPTPC1 (*(volatile struct st_eptpc0 *)0xC4C00) +#define ETHERC0 (*(volatile struct st_etherc *)0xC0100) +#define ETHERC1 (*(volatile struct st_etherc *)0xC0300) +#define EXDMAC (*(volatile struct st_exdmac *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 *)0x82840) +#define FLASH (*(volatile struct st_flash *)0x8C294) +#define GPT (*(volatile struct st_gpt *)0xC2000) +#define GPT0 (*(volatile struct st_gpt0 *)0xC2100) +#define GPT1 (*(volatile struct st_gpt0 *)0xC2180) +#define GPT2 (*(volatile struct st_gpt0 *)0xC2200) +#define GPT3 (*(volatile struct st_gpt0 *)0xC2280) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define MMCIF (*(volatile struct st_mmcif *)0x88500) +#define MPC (*(volatile struct st_mpc *)0x8C100) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 *)0xC1A00) +#define MTU8 (*(volatile struct st_mtu8 *)0xC1298) +#define PDC (*(volatile struct st_pdc *)0xA0500) +#define POE3 (*(volatile struct st_poe *)0x8C4C0) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define PPG0 (*(volatile struct st_ppg0 *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881F0) +#define PTPEDMAC (*(volatile struct st_ptpedmac *)0xC0400) +#define QSPI (*(volatile struct st_qspi *)0x89E00) +#define RAM (*(volatile struct st_ram *)0x81200) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC2 (*(volatile struct st_riic *)0x88340) +#define RSPI0 (*(volatile struct st_rspi *)0xD0100) +#define RSPI1 (*(volatile struct st_rspi *)0xD0120) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 *)0x89100) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci0 *)0x8A0E0) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SCIFA8 (*(volatile struct st_scifa *)0xD0000) +#define SCIFA9 (*(volatile struct st_scifa *)0xD0020) +#define SCIFA10 (*(volatile struct st_scifa *)0xD0040) +#define SCIFA11 (*(volatile struct st_scifa *)0xD0060) +#define SDHI (*(volatile struct st_sdhi *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci0 *)0x8A000) +#define SMCI1 (*(volatile struct st_smci0 *)0x8A020) +#define SMCI2 (*(volatile struct st_smci0 *)0x8A040) +#define SMCI3 (*(volatile struct st_smci0 *)0x8A060) +#define SMCI4 (*(volatile struct st_smci0 *)0x8A080) +#define SMCI5 (*(volatile struct st_smci0 *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci0 *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci0 *)0x8A0E0) +#define SMCI12 (*(volatile struct st_smci0 *)0x8B300) +#define SRC (*(volatile struct st_src *)0x98000) +#define SSI0 (*(volatile struct st_ssi *)0x8A500) +#define SSI1 (*(volatile struct st_ssi *)0x8A540) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 *)0x8810C) +#define TPUA (*(volatile struct st_tpua *)0x88100) +#define USB (*(volatile struct st_usb *)0xA0400) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define USBA (*(volatile struct st_usba *)0xD0400) +#define WDT (*(volatile struct st_wdt *)0x88020) + +#pragma pack() +#endif + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c new file mode 100644 index 000000000..1a79fb545 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c @@ -0,0 +1,253 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Standard includes. */ +#include "string.h" + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas code generator includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set up SCI7 receive buffer and callback function. */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + + /* Enable SCI7 operations. */ + R_SCI7_Start(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/rskrx71mdef.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/rskrx71mdef.h new file mode 100644 index 000000000..4f0e7780f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/rskrx71mdef.h @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : rskrx71mdef.h +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* H/W Platform : RSK+RX71M +* Description : Defines macros relating to the RSK+RX71M user LEDs and switches +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.01.2015 1.00 First Release +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef RSKRX71M_H +#define RSKRX71M_H + + +/* General Values */ +#define LED_ON (0) +#define LED_OFF (1) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Switches */ +#define SW1 (PORT1.PIDR.BIT.B5) +#define SW2 (PORT1.PIDR.BIT.B2) +#define SW3 (PORT0.PIDR.BIT.B7) + +/* LED port settings */ +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED2 (PORT2.PODR.BIT.B6) +#define LED3 (PORT2.PODR.BIT.B7) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Debuglinker b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Debuglinker new file mode 100644 index 000000000..eda4b45c2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Debuglinker @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.HardwareDebuglinker new file mode 100644 index 000000000..ba3cacc8f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.HardwareDebuglinker @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Releaselinker b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Releaselinker new file mode 100644 index 000000000..956c94e44 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.Releaselinker @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.cproject b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.cproject new file mode 100644 index 000000000..36e3679ff --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.cproject @@ -0,0 +1,183 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.info b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.info new file mode 100644 index 000000000..69656f398 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.info @@ -0,0 +1,6 @@ +TOOL_CHAIN=Renesas RXC Toolchain +VERSION=v2.03.00 +TC_INSTALL=C:\devtools\Renesas\RX\2_3_0\ +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.project b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.project new file mode 100644 index 000000000..6861ae509 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/Include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442692745033 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442692745043 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Renesas + + + + 1442747736584 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442747736604 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442747736614 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442747736624 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442747736634 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442747736634 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442747736644 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442747736654 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442747736654 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442747736664 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442747736664 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442747736674 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442747736674 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442747736674 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442747736684 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 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b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,77 @@ +com.renesas.cdt.renesas.Assembler.option.userDefine=-nologo;;; +com.renesas.cdt.renesas.Compiler.option.C=com.renesas.cdt.renesas.Compiler.option.C89 +com.renesas.cdt.renesas.Compiler.option.UserDef=-nologo; +com.renesas.cdt.renesas.Compiler.option.defines=__RX; +com.renesas.cdt.renesas.Compiler.option.incFileDirectories="${TCINSTALL}/include"; +com.renesas.cdt.renesas.Configurator.option.cfgPath="" +com.renesas.cdt.renesas.Configurator.option.rtosName=None +com.renesas.cdt.renesas.Configurator.option.rtosPath="" +com.renesas.cdt.renesas.Configurator.option.rtosVersion=None +com.renesas.cdt.renesas.Linker.option.rom=D\=R;D_1\=R_1;D_2\=R_2; +com.renesas.cdt.renesas.Linker.option.typeOfOutputFileOption=Stype via absolute +com.renesas.cdt.renesas.StandardLibrary.option.complexC99=false +com.renesas.cdt.renesas.StandardLibrary.option.ctypec89=false +com.renesas.cdt.renesas.StandardLibrary.option.fenvC99=false +com.renesas.cdt.renesas.StandardLibrary.option.inttypesC99=false +com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration=C(C89) +com.renesas.cdt.renesas.StandardLibrary.option.mathc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mathfc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mode=com.renesas.cdt.renesas.StandardLibrary.option.buildOnlyWhenOptionsChanged +com.renesas.cdt.renesas.StandardLibrary.option.runtime=true +com.renesas.cdt.renesas.StandardLibrary.option.rxccomplexCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxciosCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxcnewCPP=true +com.renesas.cdt.renesas.StandardLibrary.option.rxcstringCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.stdargc89=false +com.renesas.cdt.renesas.StandardLibrary.option.stdioc89=true +com.renesas.cdt.renesas.StandardLibrary.option.stdlibc89=true +com.renesas.cdt.renesas.StandardLibrary.option.stringc89=true +com.renesas.cdt.renesas.StandardLibrary.option.wcharC99=false +com.renesas.cdt.renesas.StandardLibrary.option.wctypeC99=false +com.renesas.cdt.rxc.Debug.Assembler.option.endian=Little-endian data +com.renesas.cdt.rxc.Debug.Compiler.option.RAM=None +com.renesas.cdt.rxc.Debug.Compiler.option.ROM=None +com.renesas.cdt.rxc.Debug.Compiler.option.address=00000000 +com.renesas.cdt.rxc.Debug.Compiler.option.addressRegister=None +com.renesas.cdt.rxc.Debug.Compiler.option.allocLowerBit=Lower bit +com.renesas.cdt.rxc.Debug.Compiler.option.cpuType=RX700 +com.renesas.cdt.rxc.Debug.Compiler.option.denormalized=false +com.renesas.cdt.rxc.Debug.Compiler.option.endian=Little-endian data +com.renesas.cdt.rxc.Debug.Compiler.option.enumSize=false +com.renesas.cdt.rxc.Debug.Compiler.option.packStructures=false +com.renesas.cdt.rxc.Debug.Compiler.option.patchCode=None +com.renesas.cdt.rxc.Debug.Compiler.option.precisionDouble=Single precision +com.renesas.cdt.rxc.Debug.Compiler.option.registerFastInterrupt=None +com.renesas.cdt.rxc.Debug.Compiler.option.replaceFromIntWithShort=false +com.renesas.cdt.rxc.Debug.Compiler.option.roundTo=Nearest +com.renesas.cdt.rxc.Debug.Compiler.option.saveacc=false +com.renesas.cdt.rxc.Debug.Compiler.option.signBitField=unsigned +com.renesas.cdt.rxc.Debug.Compiler.option.signChar=unsigned +com.renesas.cdt.rxc.Debug.Compiler.option.useDynamic=false +com.renesas.cdt.rxc.Debug.Compiler.option.useTry=false +com.renesas.cdt.rxc.Debug.Compiler.option.widthDivergence=24 bit +com.renesas.cdt.rxc.Debug.StandardLibrary.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.address=00000000 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit=Lower bit +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType=RX700 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.denormalized=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.enumSize=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.packStructures=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble=Single precision +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.replaceFromIntWithShort=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo=Nearest +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.saveacc=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useDynamic=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useTry=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence=24 bit +com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian=Little-endian data +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..e46ec1f5c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/custom.bat b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/makefile.init b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/makefile.init new file mode 100644 index 000000000..6e9134b91 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/makefile.init @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +export INC_RX=C:\devtools\Renesas\RX\2_3_0\include +export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin +export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin +PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..dab3ec04d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,235 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h new file mode 100644 index 000000000..caa49c718 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 60000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { brk(); taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..cb9e57691 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,169 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2407UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set + priority above the kernel's priority, but below the max syscall + priority. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IEN( PERIB, INTB128 ) = 1; + + /* Ensure that the flag is set to 0, otherwise the interrupt will not be + accepted. */ + IR( PERIB, INTB128 ) = 0; + + /* Do the same for TMR2, but to vector 129. */ + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IEN( PERIB, INTB129 ) = 1; + IR( PERIB, INTB129 ) = 0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( Excep_PERIB_INTB128( vect = 128, enable ) ) +void Excep_PERIB_INTB128( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( Excep_PERIB_INTB129( vect = 129, enable ) ) +void Excep_PERIB_INTB129( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c new file mode 100644 index 000000000..5aa053cdf --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -0,0 +1,673 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..460160307 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c @@ -0,0 +1,120 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER24M; + SYSTEM.MOSCWTCR.BYTE = _5C_CGC_MOSCWTCR_VALUE; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + SYSTEM.SCKCR.LONG = _00000002_CGC_PCLKD_DIV_4 | _00000020_CGC_PCLKC_DIV_4 | _00000200_CGC_PCLKB_DIV_4 | + _00001000_CGC_PCLKA_DIV_2 | _00020000_CGC_BCLK_DIV_4 | _00000000_CGC_ICLK_DIV_1 | + _20000000_CGC_FCLK_DIV_4; + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0000_CGC_PLL_SOURCE_MAIN | _1300_CGC_PLL_FREQ_MUL_10_0; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Stop sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Stop sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Wait for sub-clock oscillation stopping */ + while (0U != SYSTEM.OSCOVFSR.BIT.SOOVF); + + /* Set UCLK */ + SYSTEM.SCKCR2.WORD = _0040_CGC_UCLK_DIV_5 | _0001_SCKCR2_BIT0; + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set SDCLK */ + SYSTEM.SCKCR.BIT.PSTOP0 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.LONG; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 0U; +} + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..a5b4f123f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h @@ -0,0 +1,218 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock C (PCLKC) */ +#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */ +#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */ +#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */ +#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */ +#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */ +#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */ +#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 2 (SCKCR2) +*/ +#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */ +#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */ +#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */ +#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */ +#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PLL Clock Source Select (PLLSRCSEL) */ +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ +#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + RTC Control Register 4 (RCR4) +*/ +/* Count source select */ +#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */ +#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _5C_CGC_MOSCWTCR_VALUE (0x5CU) /* Main Clock Oscillator Wait Time */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..979646636 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c new file mode 100644 index 000000000..8a9a69cf4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_dbsct.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W"), + __sectop("L"), __sectop("SU"), + __sectop("C$DSEC"), __sectop("C$BSEC"), + __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT") +}; + +#pragma packoption + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..932b08ff4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,96 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_icu.h" +#include "r_cg_port.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Initialize non-existent pins */ + PORT5.PDR.BYTE = 0x70U; + + /* Set peripheral settings */ + R_CGC_Create(); + R_ICU_Create(); + R_PORT_Create(); + R_SCI7_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.c new file mode 100644 index 000000000..203e97a0c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.c @@ -0,0 +1,214 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_ICU_Create +* Description : This function initializes ICU module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_Create(void) +{ + /* Disable IRQ interrupts */ + ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE | + _00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE; + ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE | _00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE | + _00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE | _00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE; + + /* Disable group interrupts */ + IEN(ICU,GROUPBL0) = 0U; + + /* Set IRQ settings */ + ICU.IRQCR[2].BYTE = _04_ICU_IRQ_EDGE_FALLING; + ICU.IRQCR[5].BYTE = _04_ICU_IRQ_EDGE_FALLING; + + /* Set IRQ2 priority level */ + IPR(ICU,IRQ2) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set IRQ5 priority level */ + IPR(ICU,IRQ5) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set Group BL0 priority level */ + IPR(ICU,GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15; + + /* Enable group BL0 interrupt */ + IEN(ICU,GROUPBL0) = 1U; + + /* Set IRQ2 pin */ + MPC.P12PFS.BYTE = 0x40U; + PORT1.PDR.BYTE &= 0xFBU; + PORT1.PMR.BYTE &= 0xFBU; + + /* Set IRQ5 pin */ + MPC.P15PFS.BYTE = 0x40U; + PORT1.PDR.BYTE &= 0xDFU; + PORT1.PMR.BYTE &= 0xDFU; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ2_Start +* Description : This function enables IRQ2 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ2_Start(void) +{ + /* Enable IRQ2 interrupt */ + IEN(ICU,IRQ2) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ2_Stop +* Description : This function disables IRQ2 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ2_Stop(void) +{ + /* Disable IRQ2 interrupt */ + IEN(ICU,IRQ2) = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ5_Start +* Description : This function enables IRQ5 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ5_Start(void) +{ + /* Enable IRQ5 interrupt */ + IEN(ICU,IRQ5) = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ5_Stop +* Description : This function disables IRQ5 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ5_Stop(void) +{ + /* Disable IRQ5 interrupt */ + IEN(ICU,IRQ5) = 0U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/******************************************************************************* +* Function Name: R_ICU_IRQIsFallingEdge +* Description : This function returns 1 if the specified ICU_IRQ is set to +* falling edge triggered, otherwise 0. +* Arguments : uint8_t irq_no +* Return Value : 1 if falling edge triggered, 0 if not +*******************************************************************************/ +uint8_t R_ICU_IRQIsFallingEdge (const uint8_t irq_no) +{ + uint8_t falling_edge_trig = 0x0; + + if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING) + { + falling_edge_trig = 1; + } + + return falling_edge_trig; + +} + +/******************************************************************************* +* End of function R_ICU_IRQIsFallingEdge +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_IRQSetFallingEdge +* Description : This function sets/clears the falling edge trigger for the +* specified ICU_IRQ. +* Arguments : uint8_t irq_no +* uint8_t set_f_edge, 1 if setting falling edge triggered, 0 if +* clearing +* Return Value : None +*******************************************************************************/ +void R_ICU_IRQSetFallingEdge (const uint8_t irq_no, const uint8_t set_f_edge) +{ + if (1 == set_f_edge) + { + ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING; + } +} + +/****************************************************************************** +* End of function R_ICU_IRQSetFallingEdge +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_IRQSetRisingEdge +* Description : This function sets/clear the rising edge trigger for the +* specified ICU_IRQ. +* Arguments : uint8_t irq_no +* uint8_t set_r_edge, 1 if setting rising edge triggered, 0 if +* clearing +* Return Value : None +*******************************************************************************/ +void R_ICU_IRQSetRisingEdge (const uint8_t irq_no, const uint8_t set_r_edge) +{ + if (1 == set_r_edge) + { + ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING; + } +} + +/****************************************************************************** +* End of function R_ICU_IRQSetRisingEdge +*******************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.h new file mode 100644 index 000000000..bf51e8ea7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu.h @@ -0,0 +1,267 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef ICU_H +#define ICU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Interrupt Request Enable Register 08 (IER08) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_IRQ0_DISABLE (0x00U) /* IRQ0 interrupt request is disabled */ +#define _01_ICU_IRQ0_ENABLE (0x01U) /* IRQ0 interrupt request is enabled */ +#define _00_ICU_IRQ1_DISABLE (0x00U) /* IRQ1 interrupt request is disabled */ +#define _02_ICU_IRQ1_ENABLE (0x02U) /* IRQ1 interrupt request is enabled */ +#define _00_ICU_IRQ2_DISABLE (0x00U) /* IRQ2 interrupt request is disabled */ +#define _04_ICU_IRQ2_ENABLE (0x04U) /* IRQ2 interrupt request is enabled */ +#define _00_ICU_IRQ3_DISABLE (0x00U) /* IRQ3 interrupt request is disabled */ +#define _08_ICU_IRQ3_ENABLE (0x08U) /* IRQ3 interrupt request is enabled */ +#define _00_ICU_IRQ4_DISABLE (0x00U) /* IRQ4 interrupt request is disabled */ +#define _10_ICU_IRQ4_ENABLE (0x10U) /* IRQ4 interrupt request is enabled */ +#define _00_ICU_IRQ5_DISABLE (0x00U) /* IRQ5 interrupt request is disabled */ +#define _20_ICU_IRQ5_ENABLE (0x20U) /* IRQ5 interrupt request is enabled */ +#define _00_ICU_IRQ6_DISABLE (0x00U) /* IRQ6 interrupt request is disabled */ +#define _40_ICU_IRQ6_ENABLE (0x40U) /* IRQ6 interrupt request is enabled */ +#define _00_ICU_IRQ7_DISABLE (0x00U) /* IRQ7 interrupt request is disabled */ +#define _80_ICU_IRQ7_ENABLE (0x80U) /* IRQ7 interrupt request is enabled */ + +/* + Interrupt Request Enable Register 09 (IER09) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_IRQ8_DISABLE (0x00U) /* IRQ8 interrupt request is disabled */ +#define _01_ICU_IRQ8_ENABLE (0x01U) /* IRQ8 interrupt request is enabled */ +#define _00_ICU_IRQ9_DISABLE (0x00U) /* IRQ9 interrupt request is disabled */ +#define _02_ICU_IRQ9_ENABLE (0x02U) /* IRQ9 interrupt request is enabled */ +#define _00_ICU_IRQ10_DISABLE (0x00U) /* IRQ10 interrupt request is disabled */ +#define _04_ICU_IRQ10_ENABLE (0x04U) /* IRQ10 interrupt request is enabled */ +#define _00_ICU_IRQ11_DISABLE (0x00U) /* IRQ11 interrupt request is disabled */ +#define _08_ICU_IRQ11_ENABLE (0x08U) /* IRQ11 interrupt request is enabled */ +#define _00_ICU_IRQ12_DISABLE (0x00U) /* IRQ12 interrupt request is disabled */ +#define _10_ICU_IRQ12_ENABLE (0x10U) /* IRQ12 interrupt request is enabled */ +#define _00_ICU_IRQ13_DISABLE (0x00U) /* IRQ13 interrupt request is disabled */ +#define _20_ICU_IRQ13_ENABLE (0x20U) /* IRQ13 interrupt request is enabled */ +#define _00_ICU_IRQ14_DISABLE (0x00U) /* IRQ14 interrupt request is disabled */ +#define _40_ICU_IRQ14_ENABLE (0x40U) /* IRQ14 interrupt request is enabled */ +#define _00_ICU_IRQ15_DISABLE (0x00U) /* IRQ15 interrupt request is disabled */ +#define _80_ICU_IRQ15_ENABLE (0x80U) /* IRQ15 interrupt request is enabled */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Fast Interrupt Set Register (FIR) +*/ +/* Fast Interrupt Enable (FIEN) */ +#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000U) /* Fast interrupt is disabled */ +#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000U) /* Fast interrupt is enabled */ + +/* + IRQ Control Register i (IRQCRi) (i = 0 to 7) +*/ +/* IRQ Detection Sense Select (IRQMD[1:0]) */ +#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _04_ICU_IRQ_EDGE_FALLING (0x04U) /* Falling edge */ +#define _08_ICU_IRQ_EDGE_RISING (0x08U) /* Rising edge */ +#define _0C_ICU_IRQ_EDGE_BOTH (0x0CU) /* Rising and falling edge */ + +/* + IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) +*/ +/* Digital Filter Enable (FLTEN0n) */ +#define _00_ICU_IRQn_FILTER_DISABLE (0x00U) /* IRQn digital filter is disabled */ +#define _01_ICU_IRQ0_FILTER_ENABLE (0x01U) /* IRQ0 digital filter is enabled */ +#define _02_ICU_IRQ1_FILTER_ENABLE (0x02U) /* IRQ1 digital filter is enabled */ +#define _04_ICU_IRQ2_FILTER_ENABLE (0x04U) /* IRQ2 digital filter is enabled */ +#define _08_ICU_IRQ3_FILTER_ENABLE (0x08U) /* IRQ3 digital filter is enabled */ +#define _10_ICU_IRQ4_FILTER_ENABLE (0x10U) /* IRQ4 digital filter is enabled */ +#define _20_ICU_IRQ5_FILTER_ENABLE (0x20U) /* IRQ5 digital filter is enabled */ +#define _40_ICU_IRQ6_FILTER_ENABLE (0x40U) /* IRQ6 digital filter is enabled */ +#define _80_ICU_IRQ7_FILTER_ENABLE (0x80U) /* IRQ7 digital filter is enabled */ + +/* + IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1) +*/ +/* Digital Filter Enable (FLTEN8~15) */ +#define _01_ICU_IRQ8_FILTER_ENABLE (0x01U) /* IRQ8 digital filter is enabled */ +#define _02_ICU_IRQ9_FILTER_ENABLE (0x02U) /* IRQ9 digital filter is enabled */ +#define _04_ICU_IRQ10_FILTER_ENABLE (0x04U) /* IRQ10 digital filter is enabled */ +#define _08_ICU_IRQ11_FILTER_ENABLE (0x08U) /* IRQ11 digital filter is enabled */ +#define _10_ICU_IRQ12_FILTER_ENABLE (0x10U) /* IRQ12 digital filter is enabled */ +#define _20_ICU_IRQ13_FILTER_ENABLE (0x20U) /* IRQ13 digital filter is enabled */ +#define _40_ICU_IRQ14_FILTER_ENABLE (0x40U) /* IRQ14 digital filter is enabled */ +#define _80_ICU_IRQ15_FILTER_ENABLE (0x80U) /* IRQ15 digital filter is enabled */ + +/* + IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) +*/ +/* IRQn Digital Filter Sampling Clock (FCLKSELn) */ +#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000U) /* IRQ0 sample clock is run at every PCLK cycle */ +#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001U) /* IRQ0 sample clock is run at every PCLK/8 cycle */ +#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002U) /* IRQ0 sample clock is run at every PCLK/32 cycle */ +#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003U) /* IRQ0 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000U) /* IRQ1 sample clock is run at every PCLK cycle */ +#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004U) /* IRQ1 sample clock is run at every PCLK/8 cycle */ +#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008U) /* IRQ1 sample clock is run at every PCLK/32 cycle */ +#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000CU) /* IRQ1 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000U) /* IRQ2 sample clock is run at every PCLK cycle */ +#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010U) /* IRQ2 sample clock is run at every PCLK/8 cycle */ +#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020U) /* IRQ2 sample clock is run at every PCLK/32 cycle */ +#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030U) /* IRQ2 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000U) /* IRQ3 sample clock is run at every PCLK cycle */ +#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040U) /* IRQ3 sample clock is run at every PCLK/8 cycle */ +#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080U) /* IRQ3 sample clock is run at every PCLK/32 cycle */ +#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00C0U) /* IRQ3 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000U) /* IRQ4 sample clock is run at every PCLK cycle */ +#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100U) /* IRQ4 sample clock is run at every PCLK/8 cycle */ +#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200U) /* IRQ4 sample clock is run at every PCLK/32 cycle */ +#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300U) /* IRQ4 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000U) /* IRQ5 sample clock is run at every PCLK cycle */ +#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400U) /* IRQ5 sample clock is run at every PCLK/8 cycle */ +#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800U) /* IRQ5 sample clock is run at every PCLK/32 cycle */ +#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0C00U) /* IRQ5 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000U) /* IRQ6 sample clock is run at every PCLK cycle */ +#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000U) /* IRQ6 sample clock is run at every PCLK/8 cycle */ +#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000U) /* IRQ6 sample clock is run at every PCLK/32 cycle */ +#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000U) /* IRQ6 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000U) /* IRQ7 sample clock is run at every PCLK cycle */ +#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000U) /* IRQ7 sample clock is run at every PCLK/8 cycle */ +#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000U) /* IRQ7 sample clock is run at every PCLK/32 cycle */ +#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xC000U) /* IRQ7 sample clock is run at every PCLK/64 cycle */ + +/* + IRQ Pin Digital Filter Setting Register 0 (IRQFLTC1) +*/ +/* IRQn Digital Filter Sampling Clock (FCLKSEL8~15) */ +#define _0000_ICU_IRQ8_FILTER_PCLK (0x0000U) /* IRQ8 sample clock is run at every PCLK cycle */ +#define _0001_ICU_IRQ8_FILTER_PCLK_8 (0x0001U) /* IRQ8 sample clock is run at every PCLK/8 cycle */ +#define _0002_ICU_IRQ8_FILTER_PCLK_32 (0x0002U) /* IRQ8 sample clock is run at every PCLK/32 cycle */ +#define _0003_ICU_IRQ8_FILTER_PCLK_64 (0x0003U) /* IRQ8 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ9_FILTER_PCLK (0x0000U) /* IRQ9 sample clock is run at every PCLK cycle */ +#define _0004_ICU_IRQ9_FILTER_PCLK_8 (0x0004U) /* IRQ9 sample clock is run at every PCLK/8 cycle */ +#define _0008_ICU_IRQ9_FILTER_PCLK_32 (0x0008U) /* IRQ9 sample clock is run at every PCLK/32 cycle */ +#define _000C_ICU_IRQ9_FILTER_PCLK_64 (0x000CU) /* IRQ9 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ10_FILTER_PCLK (0x0000U) /* IRQ10 sample clock is run at every PCLK cycle */ +#define _0010_ICU_IRQ10_FILTER_PCLK_8 (0x0010U) /* IRQ10 sample clock is run at every PCLK/8 cycle */ +#define _0020_ICU_IRQ10_FILTER_PCLK_32 (0x0020U) /* IRQ10 sample clock is run at every PCLK/32 cycle */ +#define _0030_ICU_IRQ10_FILTER_PCLK_64 (0x0030U) /* IRQ10 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ11_FILTER_PCLK (0x0000U) /* IRQ11 sample clock is run at every PCLK cycle */ +#define _0040_ICU_IRQ11_FILTER_PCLK_8 (0x0040U) /* IRQ11 sample clock is run at every PCLK/8 cycle */ +#define _0080_ICU_IRQ11_FILTER_PCLK_32 (0x0080U) /* IRQ11 sample clock is run at every PCLK/32 cycle */ +#define _00C0_ICU_IRQ11_FILTER_PCLK_64 (0x00C0U) /* IRQ11 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ12_FILTER_PCLK (0x0000U) /* IRQ12 sample clock is run at every PCLK cycle */ +#define _0100_ICU_IRQ12_FILTER_PCLK_8 (0x0100U) /* IRQ12 sample clock is run at every PCLK/8 cycle */ +#define _0200_ICU_IRQ12_FILTER_PCLK_32 (0x0200U) /* IRQ12 sample clock is run at every PCLK/32 cycle */ +#define _0300_ICU_IRQ12_FILTER_PCLK_64 (0x0300U) /* IRQ12 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ13_FILTER_PCLK (0x0000U) /* IRQ13 sample clock is run at every PCLK cycle */ +#define _0400_ICU_IRQ13_FILTER_PCLK_8 (0x0400U) /* IRQ13 sample clock is run at every PCLK/8 cycle */ +#define _0800_ICU_IRQ13_FILTER_PCLK_32 (0x0800U) /* IRQ13 sample clock is run at every PCLK/32 cycle */ +#define _0C00_ICU_IRQ13_FILTER_PCLK_64 (0x0C00U) /* IRQ13 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ14_FILTER_PCLK (0x0000U) /* IRQ14 sample clock is run at every PCLK cycle */ +#define _1000_ICU_IRQ14_FILTER_PCLK_8 (0x1000U) /* IRQ14 sample clock is run at every PCLK/8 cycle */ +#define _2000_ICU_IRQ14_FILTER_PCLK_32 (0x2000U) /* IRQ14 sample clock is run at every PCLK/32 cycle */ +#define _3000_ICU_IRQ14_FILTER_PCLK_64 (0x3000U) /* IRQ14 sample clock is run at every PCLK/64 cycle */ +#define _0000_ICU_IRQ15_FILTER_PCLK (0x0000U) /* IRQ15 sample clock is run at every PCLK cycle */ +#define _4000_ICU_IRQ15_FILTER_PCLK_8 (0x4000U) /* IRQ15 sample clock is run at every PCLK/8 cycle */ +#define _8000_ICU_IRQ15_FILTER_PCLK_32 (0x8000U) /* IRQ15 sample clock is run at every PCLK/32 cycle */ +#define _C000_ICU_IRQ15_FILTER_PCLK_64 (0xC000U) /* IRQ15 sample clock is run at every PCLK/64 cycle */ + + +/* + NMI Pin Interrupt Control Register (NMICR) +*/ +/* NMI Digital Filter Sampling Clock (NMIMD) */ +#define _00_ICU_NMI_EDGE_FALLING (0x00U) /* Falling edge */ +#define _08_ICU_NMI_EDGE_RISING (0x08U) /* Rising edge */ + +/* + NMI Pin Digital Filter Setting Register (NMIFLTC) +*/ +/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */ +#define _00_ICU_NMI_FILTER_PCLK (0x00U) /* NMI sample clock is run at every PCLK cycle */ +#define _01_ICU_NMI_FILTER_PCLK_8 (0x01U) /* NMI sample clock is run at every PCLK/8 cycle */ +#define _02_ICU_NMI_FILTER_PCLK_32 (0x02U) /* NMI sample clock is run at every PCLK/32 cycle */ +#define _03_ICU_NMI_FILTER_PCLK_64 (0x03U) /* NMI sample clock is run at every PCLK/64 cycle */ + +/* + EXDMAC Activation Peripheral Interrupt Select Register (SELEXDR) +*/ +/* EXDMAC0 Activation Peripheral Interrupt Select (SELEXD0) */ +#define _00_ICU_EXDMAC0_SLIBR144 (0x00U) /* Interrupt B selected in SLIBR144 activates EXDMAC0 */ +#define _01_ICU_EXDMAC0_SLIAR208 (0x01U) /* Interrupt B selected in SLIAR208 activates EXDMAC0 */ +/* EXDMAC1 Activation Peripheral Interrupt Select (SELEXD1) */ +#define _00_ICU_EXDMAC1_SLIBR145 (0x00U) /* Interrupt B selected in SLIBR145 activates EXDMAC1 */ +#define _02_ICU_EXDMAC1_SLIAR209 (0x02U) /* Interrupt B selected in SLIAR209 activates EXDMAC1 */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_ICU_Create(void); +void R_ICU_IRQ2_Start(void); +void R_ICU_IRQ2_Stop(void); +void R_ICU_IRQ5_Start(void); +void R_ICU_IRQ5_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ + +/* Function prototypes for detecting and setting the edge trigger of ICU_IRQ */ +uint8_t R_ICU_IRQIsFallingEdge(const uint8_t irq_no); +void R_ICU_IRQSetFallingEdge(const uint8_t irq_no, const uint8_t set_f_edge); +void R_ICU_IRQSetRisingEdge(const uint8_t irq_no, const uint8_t set_r_edge); + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu_user.c new file mode 100644 index 000000000..90be5f36f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_icu_user.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for ICU module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_icu_irq2_interrupt +* Description : This function is IRQ2 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ2 +#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2),fint) +#else +#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2)) +#endif +static void r_icu_irq2_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_icu_irq5_interrupt +* Description : This function is IRQ5 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ5 +#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5),fint) +#else +#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5)) +#endif +static void r_icu_irq5_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c new file mode 100644 index 000000000..a49d7b771 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c @@ -0,0 +1,121 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_intprg.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section IntPRG + +/* Undefined exceptions for supervisor instruction, undefined instruction and floating point exceptions */ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Reserved */ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* NMI */ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* BRK */ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* ICU GROUPBE0 */ +void r_icu_group_be0_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* ICU GROUPBL0 */ +void r_icu_group_bl0_interrupt(void) +{ + if (ICU.GRPBL0.BIT.IS14 == 1U) + { + r_sci7_transmitend_interrupt(); + } + if (ICU.GRPBL0.BIT.IS15 == 1U) + { + r_sci7_receiveerror_interrupt(); + } + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* ICU GROUPBL1 */ +void r_icu_group_bl1_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* ICU GROUPAL0 */ +void r_icu_group_al0_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* ICU GROUPAL1 */ +void r_icu_group_al1_interrupt(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..33a7aabd8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #define __int8_t_defined + typedef signed char int8_t; + typedef signed short int16_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.c new file mode 100644 index 000000000..79935ce3c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + PORT0.PODR.BYTE = _08_Pm3_OUTPUT_1 | _20_Pm5_OUTPUT_1; + PORT2.PODR.BYTE = _02_Pm1_OUTPUT_1 | _40_Pm6_OUTPUT_1 | _80_Pm7_OUTPUT_1; + PORT4.PODR.BYTE = _20_Pm5_OUTPUT_1 | _40_Pm6_OUTPUT_1; + PORT0.DSCR.BYTE |= _08_Pm3_HIDRV_ON | _20_Pm5_HIDRV_ON; + PORT2.DSCR.BYTE |= _02_Pm1_HIDRV_ON | _40_Pm6_HIDRV_ON | _80_Pm7_HIDRV_ON; + PORT0.PDR.BYTE = _08_Pm3_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT; + PORT2.PDR.BYTE = _02_Pm1_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT; + PORT4.PDR.BYTE = _20_Pm5_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.h new file mode 100644 index 000000000..7d586cbf5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Direction Register (PDR) +*/ +/* Pmn Direction Control (B7 - B0) */ +#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */ +#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */ +#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */ +#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */ +#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */ +#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */ +#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */ +#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */ +#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */ +#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */ +#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */ +#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */ +#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */ +#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */ +#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */ +#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */ +#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */ +#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */ +#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */ +#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */ +#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */ +#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */ +#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */ +#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */ + +/* + Port Output Data Register (PODR) +*/ +/* Pmn Output Data Store (B7 - B0) */ +#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */ +#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */ +#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */ +#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */ +#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */ +#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */ +#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */ +#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */ +#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */ +#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */ +#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */ +#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */ +#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */ +#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */ +#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */ +#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */ + +/* + Open Drain Control Register 0 (ODR0) +*/ +/* Pmn Output Type Select (Pm0 to Pm3) */ +#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */ +#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */ +#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* PMOS open-drain output, for PE1 only*/ +#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */ +#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */ + +/* + Open Drain Control Register 1 (ODR1) +*/ +/* Pmn Output Type Select (Pm4 to Pm7) */ +#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */ +#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */ +#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */ +#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */ +#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */ + +/* + Pull-Up Control Register (PCR) +*/ +/* Pmn Input Pull-Up Resistor Control (B7 - B0) */ +#define _00_Pm0_PULLUP_OFF (0x00U) /* Pm0 pull-up resistor not connected */ +#define _01_Pm0_PULLUP_ON (0x01U) /* Pm0 pull-up resistor connected */ +#define _00_Pm1_PULLUP_OFF (0x00U) /* Pm1 pull-up resistor not connected */ +#define _02_Pm1_PULLUP_ON (0x02U) /* Pm1 pull-up resistor connected */ +#define _00_Pm2_PULLUP_OFF (0x00U) /* Pm2 Pull-up resistor not connected */ +#define _04_Pm2_PULLUP_ON (0x04U) /* Pm2 pull-up resistor connected */ +#define _00_Pm3_PULLUP_OFF (0x00U) /* Pm3 pull-up resistor not connected */ +#define _08_Pm3_PULLUP_ON (0x08U) /* Pm3 pull-up resistor connected */ +#define _00_Pm4_PULLUP_OFF (0x00U) /* Pm4 pull-up resistor not connected */ +#define _10_Pm4_PULLUP_ON (0x10U) /* Pm4 pull-up resistor connected */ +#define _00_Pm5_PULLUP_OFF (0x00U) /* Pm5 pull-up resistor not connected */ +#define _20_Pm5_PULLUP_ON (0x20U) /* Pm5 pull-up resistor connected */ +#define _00_Pm6_PULLUP_OFF (0x00U) /* Pm6 pull-up resistor not connected */ +#define _40_Pm6_PULLUP_ON (0x40U) /* Pm6 pull-up resistor connected */ +#define _00_Pm7_PULLUP_OFF (0x00U) /* Pm7 pull-up resistor not connected */ +#define _80_Pm7_PULLUP_ON (0x80U) /* Pm7 pull-up resistor connected */ + +/* + Drive Capacity Control Register (DSCR) +*/ +/* Pmn Drive Capacity Control (B7 - B0) */ +#define _00_Pm0_HIDRV_OFF (0x00U) /* Pm0 Normal drive output */ +#define _01_Pm0_HIDRV_ON (0x01U) /* Pm0 High-drive output */ +#define _00_Pm1_HIDRV_OFF (0x00U) /* Pm1 Normal drive output */ +#define _02_Pm1_HIDRV_ON (0x02U) /* Pm1 High-drive output */ +#define _00_Pm2_HIDRV_OFF (0x00U) /* Pm2 Normal drive output */ +#define _04_Pm2_HIDRV_ON (0x04U) /* Pm2 High-drive output */ +#define _00_Pm3_HIDRV_OFF (0x00U) /* Pm3 Normal drive output */ +#define _08_Pm3_HIDRV_ON (0x08U) /* Pm3 High-drive output */ +#define _00_Pm4_HIDRV_OFF (0x00U) /* Pm4 Normal drive output */ +#define _10_Pm4_HIDRV_ON (0x10U) /* Pm4 High-drive output */ +#define _00_Pm5_HIDRV_OFF (0x00U) /* Pm5 Normal drive output */ +#define _20_Pm5_HIDRV_ON (0x20U) /* Pm5 High-drive output */ +#define _00_Pm6_HIDRV_OFF (0x00U) /* Pm6 Normal drive output */ +#define _40_Pm6_HIDRV_ON (0x40U) /* Pm6 High-drive output */ +#define _00_Pm7_HIDRV_OFF (0x00U) /* Pm7 Normal drive output */ +#define _80_Pm7_HIDRV_ON (0x80U) /* Pm7 High-drive output */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _70_PDR5_DEFAULT (0x70U) /* PDR5 default value */ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c new file mode 100644 index 000000000..dfaa939c5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_port_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for Port module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c new file mode 100644 index 000000000..46b1c4823 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c @@ -0,0 +1,94 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_resetprg.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Reset program. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "r_cg_stacksct.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset_PC(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 /* PSW bit pattern */ +#define FPSW_init 0x00000000 /* FPSW bit base pattern */ + +#pragma section ResetPRG /* output PowerON_Reset_PC to PResetPRG section */ + +#pragma entry PowerON_Reset_PC + +void PowerON_Reset_PC(void) +{ +#ifdef __RXV2 + set_extb(__sectop("EXCEPTVECT")); +#endif + set_intb(__sectop("C$VECT")); + +#ifdef __ROZ /* Initialize FPSW */ +#define _ROUND 0x00000001 /* Let FPSW RMbits=01 (round to zero) */ +#else +#define _ROUND 0x00000000 /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define _DENOM 0x00000100 /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define _DENOM 0x00000000 /* Let FPSW DNbit=0 (denormal as is) */ +#endif + + set_fpsw(FPSW_init | _ROUND | _DENOM); + + _INITSCT(); /* Initialize Sections */ + HardwareSetup(); /* Use Hardware Setup */ + nop(); + set_psw(PSW_init); /* Set Ubit & Ibit for PSW */ + main(); + brk(); +} +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..c972d5f80 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..a998a4337 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c new file mode 100644 index 000000000..4b2528c33 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.c @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +uint8_t * gp_sci7_tx_address; /* SCI7 transmit buffer address */ +uint16_t g_sci7_tx_count; /* SCI7 transmit data number */ +uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_SCI7_Create +* Description : This function initializes SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Create(void) +{ + /* Cancel SCI7 module stop state */ + MSTP(SCI7) = 0U; + + /* Set interrupt priority */ + IPR(SCI7, RXI7) = _0F_SCI_PRIORITY_LEVEL15; + IPR(SCI7, TXI7) = _0F_SCI_PRIORITY_LEVEL15; + + /* Clear the control register */ + SCI7.SCR.BYTE = 0x00U; + + /* Set clock enable */ + SCI7.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + + /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit, and set SPMR */ + SCI7.SIMR1.BIT.IICM = 0U; + SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; + + /* Set control registers */ + SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; + SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | + _00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE; + + /* Set bitrate */ + SCI7.BRR = 0xC2U; + + /* Set RXD7 pin */ + MPC.P92PFS.BYTE = 0x0AU; + PORT9.PMR.BYTE |= 0x04U; + + /* Set TXD7 pin */ + MPC.P90PFS.BYTE = 0x0AU; + PORT9.PODR.BYTE |= 0x01U; + PORT9.PDR.BYTE |= 0x01U; + PORT9.PMR.BYTE |= 0x01U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Start +* Description : This function starts SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Start(void) +{ + /* Clear interrupt flag */ + IR(SCI7, TXI7) = 0U; + IR(SCI7, RXI7) = 0U; + + /* Enable SCI interrupt */ + IEN(SCI7, TXI7) = 1U; + ICU.GENBL0.BIT.EN14 = 1U; + IEN(SCI7, RXI7) = 1U; + ICU.GENBL0.BIT.EN15 = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Stop +* Description : This function stops SCI7. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_SCI7_Stop(void) +{ + /* Set TXD7 pin */ + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TE = 0U; /* Disable serial transmit */ + SCI7.SCR.BIT.RE = 0U; /* Disable serial receive */ + + /* Disable SCI interrupt */ + SCI7.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */ + SCI7.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */ + IR(SCI7, TXI7) = 0U; + IEN(SCI7, TXI7) = 0U; + ICU.GENBL0.BIT.EN14 = 0U; + IR(SCI7, RXI7) = 0U; + IEN(SCI7, RXI7) = 0U; + ICU.GENBL0.BIT.EN15 = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Serial_Receive +* Description : This function receives SCI7 data. +* Arguments : rx_buf - +* receive buffer pointer (Not used when receive data handled by DTC or DMAC) +* rx_num - +* buffer size (Not used when receive data handled by DTC or DMAC) +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + MD_STATUS status = MD_OK; + + if (1U > rx_num) + { + status = MD_ARGERROR; + } + else + { + g_sci7_rx_count = 0U; + g_sci7_rx_length = rx_num; + gp_sci7_rx_address = rx_buf; + SCI7.SCR.BIT.RIE = 1U; + SCI7.SCR.BIT.RE = 1U; + } + + return (status); +} +/*********************************************************************************************************************** +* Function Name: R_SCI7_Serial_Send +* Description : This function transmits SCI7 data. +* Arguments : tx_buf - +* transfer buffer pointer (Not used when transmit data handled by DTC) +* tx_num - +* buffer size (Not used when transmit data handled by DTC or DMAC) +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (1U > tx_num) + { + status = MD_ARGERROR; + } + else + { + gp_sci7_tx_address = tx_buf; + g_sci7_tx_count = tx_num; + + /* Set TXD7 pin */ + PORT9.PMR.BYTE |= 0x01U; + SCI7.SCR.BIT.TIE = 1U; + SCI7.SCR.BIT.TE = 1U; + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h new file mode 100644 index 000000000..7a963b554 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef SCI_H +#define SCI_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* + Serial mode register (SMR) +*/ +/* Clock select (CKS) */ +#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */ +#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */ +#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */ +#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */ +/* Multi-processor Mode (MP) */ +#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */ +#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */ +/* Stop bit length (STOP) */ +#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */ +#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */ +/* Parity mode (PM) */ +#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */ +#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */ +/* Parity enable (PE) */ +#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */ +#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */ +/* Character length (CHR) */ +#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */ +#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */ +/* Communications mode (CM) */ +#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */ +#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */ +/* Base clock pulse (BCP) */ +#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */ +#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */ +#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */ +#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */ +/* Block transfer mode (BLK) */ +#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */ +#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */ +/* GSM mode (GSM) */ +#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */ +#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */ + +/* + Serial control register (SCR) +*/ +/* Clock enable (CKE) */ +#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */ +#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */ +#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */ +#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */ +/* Transmit end interrupt enable (TEIE) */ +#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */ +#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */ +/* Multi-processor interrupt enable (MPIE) */ +#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */ +#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */ +/* Receive enable (RE) */ +#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */ +#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */ +/* Transmit enable (TE) */ +#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */ +#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */ +/* Receive interrupt enable (RIE) */ +#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */ +#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */ +/* Transmit interrupt enable (TIE) */ +#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */ +#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */ +/* Clock enable (CKE) */ +#define _00_SCI_SCK_OUTPUT_DISABLE (0x00U) /* SCK output is disabled */ +#define _01_SCI_SCK_OUTPUT_ENABLE (0x01U) /* SCK output is enabled */ +#define _00_SCI_SCK_OUTPUT_FIX_LOW (0x00U) /* GSM mode SCK fixed to low */ +#define _02_SCI_SCK_OUTPUT_FIX_HIGH (0x02U) /* GSM mode SCK fixed to high */ + +/* + Serial status register (SSR) +*/ +/* Multi-Processor bit transfer */ +#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */ +#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */ +/* Multi-Processor */ +#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */ +#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */ +/* Transmit end flag (TEND) */ +#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */ +#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */ +/* Parity error flag (PER) */ +#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */ +/* Framing error flag (FER) */ +#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */ +/* Error signal status flag (ERS) */ +#define _10_SCI_LOW_ERROR_DETECTED (0x10U) /* A low error signal responded */ +/* Overrun error flag (ORER) */ +#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */ +/* Receive Data Full Flag (RDRF) */ +#define _40_SCI_RECEIVE_DATAFULL (0x40U) /* Data has been received normally, and transferred from + RSR to RDR */ +/* Transmit Data Empty Flag (TDRE) */ +#define _80_SCI_TRANSMIT_DATAEMPTY (0x80U) /* Data is transferred from TDR to TSR */ + +/* + Smart card mode register (SCMR) +*/ +/* Smart card interface mode select (SMIF) */ +#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */ +#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */ +/* Transmitted / received data invert (SINV) */ +#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */ +#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */ +/* Transmitted / received data transfer direction (SDIR) */ +#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */ +#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */ +/* Character length 1 */ +#define _00_SCI_DATA_LENGTH_9 (0x00U) /* Transmit/receive in 9-bit data length */ +#define _10_SCI_DATA_LENGTH_8_OR_7 (0x10U) /* Transmit/receive in 8-bit or 7-bit data length */ +/* Base clock pulse 2 (BCP2) */ +#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */ +#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */ +#define _62_SCI_SCMR_DEFAULT (0x62U) /* Write default value of SCMR */ + +/* + Serial extended mode register (SEMR) +*/ +/* Asynchronous Mode Clock Source Select (ACS0) */ +#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */ +#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */ +/* Bit Modulation Enable (BRME) */ +#define _00_SCI_BIT_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */ +#define _04_SCI_BIT_MODULATION_ENABLE (0x04U) /* Bit rate modulation function is enabled */ +/* Asynchronous mode base clock select (ABCS) */ +#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */ +#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ +/* Digital noise filter function enable (NFEN) */ +#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */ +#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */ +/* Baud Rate Generator Double-Speed Mode Select (BGDM) */ +#define _00_SCI_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */ +#define _40_SCI_BAUDRATE_DOUBLE (0x40U) /* Baud rate generator doubles output frequency */ +/* Asynchronous start bit edge detections select (RXDESEL) */ +#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */ +#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */ + +/* + Noise filter setting register (SNFR) +*/ +/* Noise filter clock select (NFCS) */ +#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */ +#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */ +#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */ +#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */ +#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */ + +/* + I2C mode register 1 (SIMR1) +*/ +/* Simple IIC mode select (IICM) */ +#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */ +#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */ + +/* + I2C mode register 2 (SIMR2) +*/ +/* IIC interrupt mode select (IICINTM) */ +#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */ +#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */ +/* Clock synchronization (IICCSC) */ +#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */ +#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */ +/* ACK transmission data (IICACKT) */ +#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */ +#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */ + +/* + I2C mode register 3 (SIMR3) +*/ +/* Start condition generation (IICSTAREQ) */ +#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */ +#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */ +/* Restart condition generation (IICRSTAREQ) */ +#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */ +#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */ +/* Stop condition generation (IICSTPREQ) */ +#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */ +#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */ +/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */ +#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */ +#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */ +/* SSDA output select (IICSDAS) */ +#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */ +#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */ +#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */ +#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */ +/* SSCL output select (IICSCLS) */ +#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */ +#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */ +#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */ +#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */ + +/* + I2C status register (SISR) +*/ +/* ACK reception data flag (IICACKR) */ +#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */ +#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */ + +/* + SPI mode register (SPMR) +*/ +/* SS pin function enable (SSE) */ +#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */ +#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */ +/* CTS enable (CTSE) */ +#define _00_SCI_RTS (0x00U) /* RTS function is enabled */ +#define _02_SCI_CTS (0x02U) /* CTS function is disabled */ +/* Master slave select (MSS) */ +#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */ +#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */ +/* Mode fault flag (MFF) */ +#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */ +#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */ +/* Clock polarity select (CKPOL) */ +#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */ +#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */ +/* Clock phase select (CKPH) */ +#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */ +#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */ + +/* + Transfer status control value +*/ +/* Simple IIC Transmit Receive Flag */ +#define _80_SCI_IIC_TRANSMISSION (0x80U) +#define _00_SCI_IIC_RECEPTION (0x00U) +/* Simple IIC Start Stop Flag */ +#define _80_SCI_IIC_START_CYCLE (0x80U) +#define _00_SCI_IIC_STOP_CYCLE (0x00U) +/* Multiprocessor Asynchronous Communication Flag */ +#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U) +#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U) + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_SCI7_Create(void); +void R_SCI7_Start(void); +void R_SCI7_Stop(void); +MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num); +MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num); +static void r_sci7_callback_transmitend(void); +static void r_sci7_callback_receiveend(void); +static void r_sci7_callback_receiveerror(void); + +/* Start user code for function. Do not edit comment generated here */ +/* Exported functions used to transmit a number of bytes and wait for completion */ +MD_STATUS R_SCI6_SPIMasterTransmit(uint8_t * const tx_buf, const uint16_t tx_num); +MD_STATUS R_SCI7_AsyncTransmit(uint8_t * const tx_buf, const uint16_t tx_num); + +/* Character is used to receive key presses from PC terminal */ +extern uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +extern volatile uint8_t g_tx_flag; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c new file mode 100644 index 000000000..6f4c8bca6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file implements device driver for SCI module. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */ +extern uint16_t g_sci7_tx_count; /* SCI7 send data number */ +extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ +/* Flag used locally to detect transmission complete */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci6_txdone; +static volatile uint8_t sci7_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI7_TXI7 +#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7),fint) +#else +#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7)) +#endif +static void r_sci7_transmit_interrupt(void) +{ + if (0U < g_sci7_tx_count) + { + SCI7.TDR = *gp_sci7_tx_address; + gp_sci7_tx_address++; + g_sci7_tx_count--; + } + else + { + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TEIE = 1U; + } +} + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmitend_interrupt +* Description : This function is TEI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_transmitend_interrupt(void) +{ + /* Set TXD7 pin */ + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TE = 0U; + SCI7.SCR.BIT.TEIE = 0U; + + r_sci7_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#if FAST_INTERRUPT_VECTOR == VECT_SCI7_RXI7 +#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7),fint) +#else +#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7)) +#endif +static void r_sci7_receive_interrupt(void) +{ + if (g_sci7_rx_length > g_sci7_rx_count) + { + *gp_sci7_rx_address = SCI7.RDR; + gp_sci7_rx_address++; + g_sci7_rx_count++; + + if (g_sci7_rx_length <= g_sci7_rx_count) + { + r_sci7_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receiveerror_interrupt +* Description : This function is ERI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci7_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI7.SSR.BYTE; + err_type &= 0xC7U; + err_type |= 0xC0U; + SCI7.SSR.BYTE = err_type; +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_transmitend +* Description : This function is a callback function when SCI7 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci7_txdone = TRUE; + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveend +* Description : This function is a callback function when SCI7 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if (('c' == g_rx_char) || ('C' == g_rx_char)) + { +//_RB_ g_adc_trigger = TRUE; + } + + /* Set up SCI7 receive buffer and callback function again */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveerror +* Description : This function is a callback function when SCI7 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ + +/******************************************************************************* +* Function Name: R_SCI7_AsyncTransmit +* Description : This function sends SCI7 data and waits for the transmit end flag. +* Arguments : tx_buf - +* transfer buffer pointer +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +*******************************************************************************/ +MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci7_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI7_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci7_txdone) + { + /* Wait */ + } + return (status); +} + +/******************************************************************************* +* End of function R_SCI7_AsyncTransmit +*******************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h new file mode 100644 index 000000000..dea784bde --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_stacksct.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : Setting of Stack area. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _STACKSCT_H +#define _STACKSCT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +#pragma stacksize su = 0x100 +#pragma stacksize si = 0x300 + + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..45c8b7429 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +#define TRUE (1) +#define FALSE (0) + +extern volatile uint8_t g_adc_trigger; + +/* used to stop warnings being generated in r_cg_intprg.c */ +extern void r_sci6_transmitend_interrupt(void); +extern void r_sci7_transmitend_interrupt(void); +extern void r_sci7_receiveerror_interrupt(void); +extern void r_s12ad0_compare_interrupt(void); + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h new file mode 100644 index 000000000..6ac0c9593 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vect.h +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file contains definition of vector. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ +#ifndef _VECT_H +#define _VECT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Undefined */ +#pragma interrupt (r_undefined_exception) +void r_undefined_exception(void); + +/* Reserved */ +#pragma interrupt (r_reserved_exception) +void r_reserved_exception(void); + +/* NMI */ +#pragma interrupt (r_nmi_exception) +void r_nmi_exception(void); + +/* BRK */ +#pragma interrupt (r_brk_exception(vect=0)) +void r_brk_exception(void); + +/* ICU GROUPBE0 */ +#pragma interrupt (r_icu_group_be0_interrupt(vect=106)) +void r_icu_group_be0_interrupt(void); + +/* ICU GROUPBL0 */ +#pragma interrupt (r_icu_group_bl0_interrupt(vect=110)) +void r_icu_group_bl0_interrupt(void); + +/* ICU GROUPBL1 */ +#pragma interrupt (r_icu_group_bl1_interrupt(vect=111)) +void r_icu_group_bl1_interrupt(void); + +/* ICU GROUPAL0 */ +#pragma interrupt (r_icu_group_al0_interrupt(vect=112)) +void r_icu_group_al0_interrupt(void); + +/* ICU GROUPAL1 */ +#pragma interrupt (r_icu_group_al1_interrupt(vect=113)) +void r_icu_group_al1_interrupt(void); + +/*;<> */ +/*;Power On Reset PC */ +extern void PowerON_Reset_PC(void); +/*;<> */ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c new file mode 100644 index 000000000..51085108b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c @@ -0,0 +1,162 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vecttbl.c +* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015] +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* Description : This file initializes the vector table. +* Creation Date: 20/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section C EXCEPTVECT + +void (*const Excpt_Vectors[])(void) = { +/*;0xffffff80 Reserved */ + r_reserved_exception, +/*;0xffffff84 Reserved */ + r_reserved_exception, +/*;0xffffff88 Reserved */ + r_reserved_exception, +/*;0xffffff8c Reserved */ + r_reserved_exception, +/*;0xffffff90 Reserved */ + r_reserved_exception, +/*;0xffffff94 Reserved */ + r_reserved_exception, +/*;0xffffff98 Reserved */ + r_reserved_exception, +/*;0xffffff9c Reserved */ + r_reserved_exception, +/*;0xffffffa0 Reserved */ + r_reserved_exception, +/*;0xffffffa4 Reserved */ + r_reserved_exception, +/*;0xffffffa8 Reserved */ + r_reserved_exception, +/*;0xffffffac Reserved */ + r_reserved_exception, +/*;0xffffffb0 Reserved */ + r_reserved_exception, +/*;0xffffffb4 Reserved */ + r_reserved_exception, +/*;0xffffffb8 Reserved */ + r_reserved_exception, +/*;0xffffffbc Reserved */ + r_reserved_exception, +/*;0xffffffc0 Reserved */ + r_reserved_exception, +/*;0xffffffc4 Reserved */ + r_reserved_exception, +/*;0xffffffc8 Reserved */ + r_reserved_exception, +/*;0xffffffcc Reserved */ + r_reserved_exception, +/*;0xffffffd0 Exception(Supervisor Instruction) */ + r_undefined_exception, +/*;0xffffffd4 Reserved */ + r_reserved_exception, +/*;0xffffffd8 Reserved */ + r_reserved_exception, +/*;0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, +/*;0xffffffe0 Reserved */ + r_reserved_exception, +/*;0xffffffe4 Exception(Floating Point) */ + r_undefined_exception, +/*;0xffffffe8 Reserved */ + r_reserved_exception, +/*;0xffffffec Reserved */ + r_reserved_exception, +/*;0xfffffff0 Reserved */ + r_reserved_exception, +/*;0xfffffff4 Reserved */ + r_reserved_exception, +/*;0xfffffff8 NMI */ + r_nmi_exception, +}; + +#pragma section C RESETVECT +void (*const Reset_Vectors[])(void) = { +/*;<> */ +/*;Power On Reset PC */ + /*(void*)*/ PowerON_Reset_PC +/*;<> */ +}; + +/* MDE register (Single Chip Mode) */ +#pragma address __MDEreg=0x00120064 +#ifdef __BIG + /* Big endian*/ + const unsigned long __MDEreg = 0xFFFFFFF8; +#else + /* Little endian */ + const unsigned long __MDEreg = 0xFFFFFFFF; +#endif + +/* Set option bytes */ +/* OFS0 register */ +#pragma address __OFS0reg = 0x00120068 +const unsigned long __OFS0reg = 0xFFFFFFFF; + +/* OFS1 register */ +#pragma address __OFS1reg = 0x0012006C +const unsigned long __OFS1reg = 0xFFFFFFFF; + +/* Start user code for adding. Do not edit comment generated here */ +/* SPCC register */ +#pragma address __SPCCreg=0x00120040 +const unsigned long __SPCCreg = 0xffffffff; + +/* TMEF register */ +#pragma address __TMEFreg=0x00120048 +const unsigned long __TMEFreg = 0xffffffff; + +/* OSIC register (ID codes) */ +#pragma address __OSISreg=0x00120050 +const unsigned long __OSISreg[4] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, +}; + +/* TMINF register */ +#pragma address __TMINFreg=0x00120060 +const unsigned long __TMINFreg = 0xffffffff; +/* End user code. Do not edit comment generated here */ + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/iodefine.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/iodefine.h new file mode 100644 index 000000000..5c3a0b2b4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/iodefine.h @@ -0,0 +1,17783 @@ +/******************************************************************************** +* +* Device : RX/RX700/RX71M +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register +* +* History : 0.10 (2014-03-22) [Hardware Manual Revision : 0.10] +* : 1.00 (2014-12-08) [Hardware Manual Revision : 1.00] +* +* Note : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2014 Renesas Electronics Corporation. +* +*********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX71M */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX71MIODEFINE_HEADER__ +#define __RX71MIODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short BPHB:2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; + char wk29[894]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BSIZE:2; + unsigned char :3; + unsigned char EXENB:1; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EMODE:1; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BE:1; + } BIT; + } SDAMOD; + char wk30[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SFEN:1; + } BIT; + } SDSELF; + char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short REFW:4; + unsigned short RFC:12; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RFEN:1; + } BIT; + } SDRFEN; + char wk32[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char INIRQ:1; + } BIT; + } SDICR; + char wk33[3]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short PRC:3; + unsigned short ARFC:4; + unsigned short ARFI:4; + } BIT; + } SDIR; + char wk34[26]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MXC:2; + } BIT; + } SDADR; + char wk35[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RAS:3; + unsigned long :2; + unsigned long RCD:2; + unsigned long RP:3; + unsigned long WR:1; + unsigned long :5; + unsigned long CL:3; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short MR:15; + } BIT; + } SDMOD; + char wk36[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SRFST:1; + unsigned char INIST:1; + unsigned char :2; + unsigned char MRSST:1; + } BIT; + } SDSR; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :7; + unsigned long CCLKS:1; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_cmtw { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short STR:1; + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short CCLR:3; + unsigned short :3; + unsigned short CMS:1; + unsigned short :1; + unsigned short OC1IE:1; + unsigned short OC0IE:1; + unsigned short IC1IE:1; + unsigned short IC0IE:1; + unsigned short CMWIE:1; + unsigned short :1; + unsigned short CKS:2; + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short CMWE:1; + unsigned short :1; + unsigned short OC1E:1; + unsigned short OC0E:1; + unsigned short OC1:2; + unsigned short OC0:2; + unsigned short :2; + unsigned short IC1E:1; + unsigned short IC0E:1; + unsigned short IC1:2; + unsigned short IC0:2; + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + } BIT; + } DAADSCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAAMP1:1; + unsigned char DAAMP0:1; + } BIT; + } DAAMPCR; + char wk1[17783]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char AMADSEL1:1; + } BIT; + } DAADUSR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMIS7:1; + unsigned char DMIS6:1; + unsigned char DMIS5:1; + unsigned char DMIS4:1; + } BIT; + } DMIST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_eccram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMOD:2; + } BIT; + } ECCRAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC2ERR:1; + } BIT; + } ECCRAM2STS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1STSEN:1; + } BIT; + } ECCRAM1STSEN; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1ERR:1; + } BIT; + } ECCRAM1STS; +// union { +// unsigned char BYTE; +// struct { +// unsigned char KW:7; +// unsigned char PRCR:1; +// } BIT; +// } ECCRAMPRCR; + unsigned char ECCRAMPRCR; + char wk0[3]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC2EAD:12; + } BIT; + } ECCRAM2ECAD; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC1EAD:12; + } BIT; + } ECCRAM1ECAD; +// union { +// unsigned char BYTE; +// struct { +// unsigned char KW2:7; +// unsigned char PRCR2:1; +// } BIT; +// } ECCRAMPRCR2; + unsigned char ECCRAMPRCR2; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TSTBYP:1; + } BIT; + } ECCRAMETST; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long RABT:1; + unsigned long RFCOF:1; + unsigned long ADE:1; + unsigned long ECI:1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :4; + unsigned long CND:1; + unsigned long DLC:1; + unsigned long CD:1; + unsigned long TRO:1; + unsigned long RMAF:1; + unsigned long :2; + unsigned long RRF:1; + unsigned long RTLF:1; + unsigned long RTSF:1; + unsigned long PRE:1; + unsigned long CERF:1; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long RABTIP:1; + unsigned long RFCOFIP:1; + unsigned long ADEIP:1; + unsigned long ECIIP:1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :4; + unsigned long CNDIP:1; + unsigned long DLCIP:1; + unsigned long CDIP:1; + unsigned long TROIP:1; + unsigned long RMAFIP:1; + unsigned long :2; + unsigned long RRFIP:1; + unsigned long RTLFIP:1; + unsigned long RTSFIP:1; + unsigned long PREIP:1; + unsigned long CERFIP:1; + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RMAFCE:1; + unsigned long :2; + unsigned long RRFCE:1; + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long ELB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char :4; + unsigned char MTU0MD:2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CMT1MD:2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char TMR3MD:2; + unsigned char TMR2MD:2; + unsigned char TMR1MD:2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL3; + union { + unsigned char BYTE; +// struct { +// unsigned char WI:1; +// unsigned char WE:1; +// unsigned char :5; +// unsigned char SEG:1; +// } BIT; + } ELSEGR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR33; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR35; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR36; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR37; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR38; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR41; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR42; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR43; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR44; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR45; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char TPU3MD:2; + unsigned char TPU2MD:2; + unsigned char TPU1MD:2; + unsigned char TPU0MD:2; + } BIT; + } ELOPF; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMTW0MD:2; + } BIT; + } ELOPH; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char GPT1MD:3; + unsigned char :1; + unsigned char GPT0MD:3; + } BIT; + } ELOPI; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char GPT3MD:3; + unsigned char :1; + unsigned char GPT2MD:3; + } BIT; + } ELOPJ; +}; + +struct st_eptpc { + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RESET:1; + } BIT; + } PTRSTR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long SCLKSEL:3; + unsigned long :5; + unsigned long SCLKDIV:3; + } BIT; + } STCSELR; + char wk0[15096]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :10; +// unsigned long CYC5:1; +// unsigned long CYC4:1; +// unsigned long CYC3:1; +// unsigned long CYC2:1; +// unsigned long CYC1:1; +// unsigned long CYC0:1; +// unsigned long :12; +// unsigned long PRC:1; +// unsigned long SY1:1; +// unsigned long SY0:1; +// unsigned long ST:1; +// } BIT; +// } MIESR; + unsigned long MIESR; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long CYC5:1; + unsigned long CYC4:1; + unsigned long CYC3:1; + unsigned long CYC2:1; + unsigned long CYC1:1; + unsigned long CYC0:1; + unsigned long :12; + unsigned long PR:1; + unsigned long SY1:1; + unsigned long SY0:1; + unsigned long ST:1; + } BIT; + } MIEIPR; + char wk1[8]; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPPR; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPACR; + char wk2[40]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :27; +// unsigned long W10D:1; +// unsigned long SYNTOUT:1; +// unsigned long :1; +// unsigned long SYNCOUT:1; +// unsigned long SYNC:1; +// } BIT; +// } STSR; + unsigned long STSR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long W10D:1; + unsigned long SYNTOUT:1; + unsigned long :1; + unsigned long SYNCOUT:1; + unsigned long SYNC:1; + } BIT; + } STIPR; + char wk3[8]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long STCF:2; + } BIT; + } STCFR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ALEN1:1; + unsigned long ALEN0:1; + unsigned long :4; + unsigned long DVTH:4; + unsigned long SYTH:4; + unsigned long W10S:1; + unsigned long :1; + unsigned long CMOD:1; + unsigned long :5; + unsigned long WINT:8; + } BIT; + } STMR; + unsigned long SYNTOR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long IPTSEL5:1; + unsigned long IPTSEL4:1; + unsigned long IPTSEL3:1; + unsigned long IPTSEL2:1; + unsigned long IPTSEL1:1; + unsigned long IPTSEL0:1; + } BIT; + } IPTSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long MINTEN5:1; + unsigned long MINTEN4:1; + unsigned long MINTEN3:1; + unsigned long MINTEN2:1; + unsigned long MINTEN1:1; + unsigned long MINTEN0:1; + } BIT; + } MITSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long ELTDIS5:1; + unsigned long ELTDIS4:1; + unsigned long ELTDIS3:1; + unsigned long ELTDIS2:1; + unsigned long ELTDIS1:1; + unsigned long ELTDIS0:1; + } BIT; + } ELTSELR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SYSEL:1; + } BIT; + } STCHSELR; + char wk5[16]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long STR:1; + } BIT; + } SYNSTARTR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LOAD:1; + } BIT; + } LCIVLDR; + char wk6[8]; + unsigned long SYNTDARU; + unsigned long SYNTDARL; + unsigned long SYNTDBRU; + unsigned long SYNTDBRL; + char wk7[16]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long VALU:16; + } BIT; + } LCIVRU; + unsigned long LCIVRM; + unsigned long LCIVRL; + char wk8[104]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long GW10:1; + } BIT; + } GETW10R; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } PLIMITRU; + unsigned long PLIMITRM; + unsigned long PLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } MLIMITRU; + unsigned long MLIMITRM; + unsigned long MLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long INFO:1; + } BIT; + } GETINFOR; + char wk9[44]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CNTU:16; + } BIT; + } LCCVRU; + unsigned long LCCVRM; + unsigned long LCCVRL; + char wk10[148]; + unsigned long PW10VRU; + unsigned long PW10VRM; + unsigned long PW10VRL; + char wk11[180]; + unsigned long MW10RU; + unsigned long MW10RM; + unsigned long MW10RL; + char wk12[36]; + unsigned long TMSTTRU0; + unsigned long TMSTTRL0; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR0; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR0; + unsigned long TMSTTRU1; + unsigned long TMSTTRL1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR1; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR1; + unsigned long TMSTTRU2; + unsigned long TMSTTRL2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR2; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR2; + unsigned long TMSTTRU3; + unsigned long TMSTTRL3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR3; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR3; + unsigned long TMSTTRU4; + unsigned long TMSTTRL4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR4; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR4; + unsigned long TMSTTRU5; + unsigned long TMSTTRL5; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR5; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR5; + char wk13[28]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } TMSTARTR; + char wk14[128]; +// union { +// unsigned long LONG; +// struct { +// unsigned long :2; +// unsigned long URE1:1; +// unsigned long URE0:1; +// unsigned long :19; +// unsigned long MACE:1; +// unsigned long :4; +// unsigned long OVRE3:1; +// unsigned long OVRE2:1; +// unsigned long OVRE1:1; +// unsigned long OVRE0:1; +// } BIT; +// } PRSR; + unsigned long PRSR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long URE1:1; + unsigned long URE0:1; + unsigned long :19; + unsigned long MACE:1; + unsigned long :4; + unsigned long OVRE3:1; + unsigned long OVRE2:1; + unsigned long OVRE1:1; + unsigned long OVRE0:1; + } BIT; + } PRIPR; + char wk15[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU1; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL1; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long TDIS:2; + } BIT; + } TRNDISR; + char wk16[12]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long FWD1:1; + unsigned long FWD0:1; + unsigned long :7; + unsigned long MOD:1; + } BIT; + } TRNMR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long THVAL:11; + } BIT; + } TRNCTTDR; +}; + +struct st_eptpc0 { +// union { +// unsigned long LONG; +// struct { +// unsigned long :14; +// unsigned long GENDN:1; +// unsigned long RESDN:1; +// unsigned long :1; +// unsigned long INFABT:1; +// unsigned long :1; +// unsigned long RECLP:1; +// unsigned long :5; +// unsigned long DRQOVR:1; +// unsigned long INTDEV:1; +// unsigned long DRPTO:1; +// unsigned long :1; +// unsigned long MPDUD:1; +// unsigned long INTCHG:1; +// unsigned long OFMUD:1; +// } BIT; +// } SYSR; + unsigned long SYSR; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long GENDN:1; + unsigned long RESDN:1; + unsigned long :1; + unsigned long INFABT:1; + unsigned long :1; + unsigned long RECLP:1; + unsigned long :5; + unsigned long DRQOVR:1; + unsigned long INTDEV:1; + unsigned long DRPTO:1; + unsigned long :1; + unsigned long MPDUD:1; + unsigned long INTCHG:1; + unsigned long OFMUD:1; + } BIT; + } SYIPR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } SYMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } SYMACRL; + unsigned long SYLLCCTLR; + unsigned long SYIPADDRR; + char wk1[32]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TRSP:4; + unsigned long VER:4; + } BIT; + } SYSPVRR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long DNUM:8; + } BIT; + } SYDOMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long FLAG15:1; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long FLAG12:1; + unsigned long FLAG11:1; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long FLAG7:1; + unsigned long FLAG6:1; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } ANFR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long FLAG15:1; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long FLAG12:1; + unsigned long FLAG11:1; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long FLAG7:1; + unsigned long FLAG6:1; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } SYNFR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long FLAG15:1; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long FLAG12:1; + unsigned long FLAG11:1; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long FLAG7:1; + unsigned long FLAG6:1; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } DYRQFR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long FLAG15:1; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long FLAG12:1; + unsigned long FLAG11:1; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long FLAG7:1; + unsigned long FLAG6:1; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } DYRPFR; + unsigned long SYCIDRU; + unsigned long SYCIDRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } SYPNUMR; + char wk3[20]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long ANUP:1; + unsigned long STUP:1; + unsigned long BMUP:1; + } BIT; + } SYRVLDR; + char wk4[12]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long PDFUP:3; + unsigned long :1; + unsigned long PDRP:3; + unsigned long :1; + unsigned long PDRQ:3; + unsigned long :1; + unsigned long DRP:3; + unsigned long :1; + unsigned long DRQ:3; + unsigned long :1; + unsigned long FUP:3; + unsigned long :1; + unsigned long SYNC:3; + unsigned long :2; + unsigned long ANCE:2; + } BIT; + } SYRFL1R; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ILL:2; + unsigned long :22; + unsigned long SIG:2; + unsigned long :2; + unsigned long MAN:2; + } BIT; + } SYRFL2R; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long PDRQ:1; + unsigned long :3; + unsigned long DRQ:1; + unsigned long :3; + unsigned long SYNC:1; + unsigned long :3; + unsigned long ANCE:1; + } BIT; + } SYTRENR; + char wk5[4]; + unsigned long MTCIDU; + unsigned long MTCIDL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } MTPID; + char wk6[20]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DREQ:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYTLIR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DRESP:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYRLIR; + unsigned long OFMRU; + unsigned long OFMRL; + unsigned long MPDRU; + unsigned long MPDRL; + char wk7[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long GMPR1:8; + unsigned long :8; + unsigned long GMPR2:8; + } BIT; + } GMPR; + unsigned long GMCQR; + unsigned long GMIDRU; + unsigned long GMIDRL; + union { + unsigned long LONG; + struct { + unsigned long CUTO:16; + unsigned long :8; + unsigned long TSRC:8; + } BIT; + } CUOTSR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long SRMV:16; + } BIT; + } SRR; + char wk8[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PPMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PPMACRL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PDMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PDMACRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TYPE:16; + } BIT; + } PETYPER; + char wk9[12]; + unsigned long PPIPR; + unsigned long PDIPR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long EVTO:8; + } BIT; + } PETOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long GETO:8; + } BIT; + } PGTOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PRTL:8; + } BIT; + } PPTTLR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PDTL:8; + } BIT; + } PDTTLR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EVUPT:16; + } BIT; + } PEUDPR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long GEUPT:16; + } BIT; + } PGUDPR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long EXTPRM:1; + unsigned long :13; + unsigned long ENB:1; + unsigned long PRT:1; + unsigned long SEL:1; + } BIT; + } FFLTR; + char wk10[28]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC0RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC0RL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC1RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC1RL; + char wk11[80]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ASYMU:16; + } BIT; + } DASYMRU; + unsigned long DASYMRL; + union { + unsigned long LONG; + struct { + unsigned long INGP:16; + unsigned long EGP:16; + } BIT; + } TSLATR; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TCMOD:1; + unsigned long :3; + unsigned long FILDIS:1; + unsigned long :3; + unsigned long SBDIS:1; + unsigned long :4; + unsigned long TCYC:8; + } BIT; + } SYCONFR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long FORM1:1; + unsigned long FORM0:1; + } BIT; + } SYFORMR; + unsigned long RSTOUTR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TPC:1; + unsigned long ZPF:1; + unsigned long PFR:1; + unsigned long RXF:1; + unsigned long TXF:1; + unsigned long :3; + unsigned long PRCEF:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long RE:1; + unsigned long TE:1; + unsigned long :1; + unsigned long ILB:1; + unsigned long RTM:1; + unsigned long DM:1; + unsigned long PRM:1; + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long RFL:12; + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFR:1; + unsigned long PSRTO:1; + unsigned long :1; + unsigned long LCHNG:1; + unsigned long MPD:1; + unsigned long ICD:1; + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFSIPR:1; + unsigned long PSRTOIP:1; + unsigned long :1; + unsigned long LCHNGIP:1; + unsigned long MPDIP:1; + unsigned long ICDIP:1; + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long MDI:1; + unsigned long MDO:1; + unsigned long MMD:1; + unsigned long MDC:1; + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LMON:1; + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long RMD:20; + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long IPG:5; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long AP:16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MP:16; + } BIT; + } MPR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPAUSE:8; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TPAUSE:16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TXP:8; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long BCF:16; + } BIT; + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MA:16; + } BIT; + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +}; + +struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +}; + +struct st_flash { + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + char wk1[7806329]; + union { + unsigned char BYTE; + struct { + unsigned char CFAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFAE:1; + unsigned char :2; + unsigned char ECRCT:1; + } BIT; + } FASTAT; + char wk2[3]; + union { + unsigned char BYTE; + struct { + unsigned char CFAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFAEIE:1; + unsigned char :2; + unsigned char ECRCTIE:1; + } BIT; + } FAEINT; + char wk3[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + char wk4[23]; + union { + unsigned long LONG; + struct { + unsigned long FSADDR:32; + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + unsigned long FEADDR:32; + } BIT; + } FEADDR; + char wk5[28]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short FRAMTRAN:1; + unsigned short FCRME:1; + } BIT; + } FCURAME; + char wk6[42]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long FRDY:1; + unsigned long ILGLERR:1; + unsigned long ERSERR:1; + unsigned long PRGERR:1; + unsigned long SUSRDY:1; + unsigned long DBFULL:1; + unsigned long ERSSPD:1; + unsigned long PRGSPD:1; + unsigned long FCUERR:1; + unsigned long FLWEERR:1; + unsigned long :4; + unsigned long FRDTCT:1; + unsigned long FRCRCT:1; + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRYC:1; + } BIT; + } FENTRYR; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short FPROTCN:1; + } BIT; + } FPROTR; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short SUINIT:1; + } BIT; + } FSUINITR; + char wk9[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FLOCKST:1; + } BIT; + } FLKSTAT; + char wk10[15]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + char wk11[30]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PEERRST:8; + } BIT; + } FPESTAT; + char wk12[14]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCDIR:1; + } BIT; + } FBCCNT; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCST:1; + } BIT; + } FBCSTAT; + char wk14[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long PSADR:19; + } BIT; + } FPSADDR; + char wk15[4]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + char wk16[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short PCKA:8; + } BIT; + } FPCKAR; +}; + +struct st_gpt { + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short CST3:1; + unsigned short CST2:1; + unsigned short CST1:1; + unsigned short CST0:1; + } BIT; + } GTSTR; + union { + unsigned short WORD; + struct { + unsigned short NFCS3:2; + unsigned short NFCS2:2; + unsigned short NFCS1:2; + unsigned short NFCS0:2; + unsigned short NFB3EN:1; + unsigned short NFA3EN:1; + unsigned short NFB2EN:1; + unsigned short NFA2EN:1; + unsigned short NFB1EN:1; + unsigned short NFA1EN:1; + unsigned short NFB0EN:1; + unsigned short NFA0EN:1; + } BIT; + } NFCR; + union { + unsigned short WORD; + struct { + unsigned short CPHW3:2; + unsigned short CPHW2:2; + unsigned short CPHW1:2; + unsigned short CPHW0:2; + unsigned short CSHW3:2; + unsigned short CSHW2:2; + unsigned short CSHW1:2; + unsigned short CSHW0:2; + } BIT; + } GTHSCR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short CCSW3:1; + unsigned short CCSW2:1; + unsigned short CCSW1:1; + unsigned short CCSW0:1; + unsigned short CCHW3:2; + unsigned short CCHW2:2; + unsigned short CCHW1:2; + unsigned short CCHW0:2; + } BIT; + } GTHCCR; + union { + unsigned short WORD; + struct { + unsigned short CSHSL3:4; + unsigned short CSHSL2:4; + unsigned short CSHSL1:4; + unsigned short CSHSL0:4; + } BIT; + } GTHSSR; + union { + unsigned short WORD; + struct { + unsigned short CSHPL3:4; + unsigned short CSHPL2:4; + unsigned short CSHPL1:4; + unsigned short CSHPL0:4; + } BIT; + } GTHPSR; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short WP3:1; + unsigned short WP2:1; + unsigned short WP1:1; + unsigned short WP0:1; + } BIT; + } GTWP; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short SYNC3:2; + unsigned short :2; + unsigned short SYNC2:2; + unsigned short :2; + unsigned short SYNC1:2; + unsigned short :2; + unsigned short SYNC0:2; + } BIT; + } GTSYNC; + union { + unsigned short WORD; + struct { + unsigned short GTETRGEN:1; + unsigned short GTENFCS:2; + unsigned short :11; + unsigned short ETINEN:1; + unsigned short ETIPEN:1; + } BIT; + } GTETINT; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short BD33:1; + unsigned short BD32:1; + unsigned short BD31:1; + unsigned short BD30:1; + unsigned short BD23:1; + unsigned short BD22:1; + unsigned short BD21:1; + unsigned short BD20:1; + unsigned short BD13:1; + unsigned short BD12:1; + unsigned short BD11:1; + unsigned short BD10:1; + unsigned short BD03:1; + unsigned short BD02:1; + unsigned short BD01:1; + unsigned short BD00:1; + } BIT; + } GTBDR; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short SWP3:1; + unsigned short SWP2:1; + unsigned short SWP1:1; + unsigned short SWP0:1; + } BIT; + } GTSWP; +}; + +struct st_gpt0 { + union { + unsigned short WORD; + struct { + unsigned short OBHLD:1; + unsigned short OBDFLT:1; + unsigned short GTIOB:6; + unsigned short OAHLD:1; + unsigned short OADFLT:1; + unsigned short GTIOA:6; + } BIT; + } GTIOR; + union { + unsigned short WORD; + struct { + unsigned short ADTRBDEN:1; + unsigned short ADTRBUEN:1; + unsigned short ADTRADEN:1; + unsigned short ADTRAUEN:1; + unsigned short EINT:1; + unsigned short :3; + unsigned short GTINTPR:2; + unsigned short GTINTF:1; + unsigned short GTINTE:1; + unsigned short GTINTD:1; + unsigned short GTINTC:1; + unsigned short GTINTB:1; + unsigned short GTINTA:1; + } BIT; + } GTINTAD; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short CCLR:2; + unsigned short :2; + unsigned short TPCS:2; + unsigned short :5; + unsigned short MD:3; + } BIT; + } GTCR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short ADTDB:1; + unsigned short ADTTB:2; + unsigned short :1; + unsigned short ADTDA:1; + unsigned short ADTTA:2; + unsigned short :1; + unsigned short CCRSWT:1; + unsigned short PR:2; + unsigned short CCRB:2; + unsigned short CCRA:2; + } BIT; + } GTBER; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short UDF:1; + unsigned short UD:1; + } BIT; + } GTUDC; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short ADTBL:1; + unsigned short :1; + unsigned short ADTAL:1; + unsigned short :1; + unsigned short IVTT:3; + unsigned short IVTC:2; + unsigned short ITLF:1; + unsigned short ITLE:1; + unsigned short ITLD:1; + unsigned short ITLC:1; + unsigned short ITLB:1; + unsigned short ITLA:1; + } BIT; + } GTITC; + union { + unsigned short WORD; + struct { + unsigned short TUCF:1; + unsigned short :3; + unsigned short DTEF:1; + unsigned short ITCNT:3; + } BIT; + } GTST; + unsigned short GTCNT; + unsigned short GTCCRA; + unsigned short GTCCRB; + unsigned short GTCCRC; + unsigned short GTCCRD; + unsigned short GTCCRE; + unsigned short GTCCRF; + unsigned short GTPR; + unsigned short GTPBR; + unsigned short GTPDBR; + char wk0[2]; + unsigned short GTADTRA; + unsigned short GTADTBRA; + unsigned short GTADTDBRA; + char wk1[2]; + unsigned short GTADTRB; + unsigned short GTADTBRB; + unsigned short GTADTDBRB; + char wk2[2]; + union { + unsigned short WORD; + struct { + unsigned short OBE:1; + unsigned short OAE:1; + unsigned short :1; + unsigned short SWN:1; + unsigned short :3; + unsigned short NFV:1; + unsigned short NFS:4; + unsigned short NVB:1; + unsigned short NVA:1; + unsigned short NEB:1; + unsigned short NEA:1; + } BIT; + } GTONCR; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TDFER:1; + unsigned short :2; + unsigned short TDBDE:1; + unsigned short TDBUE:1; + unsigned short :3; + unsigned short TDE:1; + } BIT; + } GTDTCR; + unsigned short GTDVU; + unsigned short GTDVD; + unsigned short GTDBU; + unsigned short GTDBD; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short SOS:2; + } BIT; + } GTSOS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short SOTR:1; + } BIT; + } GTSOTR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT2:1; + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN15:1; + unsigned char FLTEN14:1; + unsigned char FLTEN13:1; + unsigned char FLTEN12:1; + unsigned char FLTEN11:1; + unsigned char FLTEN10:1; + unsigned char FLTEN9:1; + unsigned char FLTEN8:1; + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL15:2; + unsigned short FCLKSEL14:2; + unsigned short FCLKSEL13:2; + unsigned short FCLKSEL12:2; + unsigned short FCLKSEL11:2; + unsigned short FCLKSEL10:2; + unsigned short FCLKSEL9:2; + unsigned short FCLKSEL8:2; + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ECCRAMST:1; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ECCRAMEN:1; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + } BIT; + } NMICR; + char wk14[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; + char wk16[107]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBE0; + char wk17[44]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL1; + char wk18[8]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBE0; + char wk19[44]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL1; + char wk20[8]; + union { + unsigned long LONG; + struct { + unsigned long CLR31:1; + unsigned long CLR30:1; + unsigned long CLR29:1; + unsigned long CLR28:1; + unsigned long CLR27:1; + unsigned long CLR26:1; + unsigned long CLR25:1; + unsigned long CLR24:1; + unsigned long CLR23:1; + unsigned long CLR22:1; + unsigned long CLR21:1; + unsigned long CLR20:1; + unsigned long CLR19:1; + unsigned long CLR18:1; + unsigned long CLR17:1; + unsigned long CLR16:1; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCRBE0; + char wk21[124]; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR0; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR1; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR2; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR3; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR4; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR5; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR6; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR7; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR8; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBR9; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIBRA; + char wk22[117]; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR128; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR129; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR130; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR131; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR132; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR133; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR134; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR135; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR136; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR137; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR138; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR139; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR140; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR141; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR142; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR143; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR144; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR145; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR146; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR147; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR148; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR149; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR150; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR151; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR152; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR153; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR154; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR155; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR156; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR157; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR158; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR159; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR160; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR161; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR162; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR163; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR164; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR165; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR166; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR167; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR168; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR169; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR170; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR171; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR172; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR173; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR174; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR175; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR176; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR177; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR178; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR179; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR180; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR181; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR182; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR183; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR184; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR185; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR186; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR187; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR188; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR189; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR190; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR191; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR192; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR193; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR194; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR195; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR196; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR197; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR198; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR199; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR200; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR201; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR202; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR203; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR204; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR205; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR206; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR207; + char wk23[96]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL1; + char wk24[56]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL1; + char wk25[136]; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR0; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR1; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR2; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR3; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR4; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR5; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR6; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR7; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR8; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIAR9; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIARA; + union { + unsigned char BYTE; +// struct { +// unsigned char PIR7:1; +// unsigned char PIR6:1; +// unsigned char PIR5:1; +// unsigned char PIR4:1; +// unsigned char PIR3:1; +// unsigned char PIR2:1; +// unsigned char PIR1:1; +// unsigned char PIR0:1; +// } BIT; + } PIARB; + char wk26[196]; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR208; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR209; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR210; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR211; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR212; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR213; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR214; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR215; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR216; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR217; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR218; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR219; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR220; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR221; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR222; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR223; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR224; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR225; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR226; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR227; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR228; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR229; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR230; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR231; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR232; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR233; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR234; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR235; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR236; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR237; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR238; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR239; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR240; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR241; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR242; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR243; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR244; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR245; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR246; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR247; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR248; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR249; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR250; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR251; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR252; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR253; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR254; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIAR255; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char WPRC:1; + } BIT; + } SLIPRCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SELEXD1:1; + unsigned char SELEXD0:1; + } BIT; + } SELEXDR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + } BIT; + } IWDTCSTPR; +}; + +struct st_mmcif { + union { + unsigned long LONG; +// struct { +// unsigned long :1; +// unsigned long BOOT:1; +// unsigned long CMD:6; +// unsigned long RTYP:2; +// unsigned long RBSY:1; +// unsigned long :1; +// unsigned long WDAT:1; +// unsigned long DWEN:1; +// unsigned long CMLTE:1; +// unsigned long CMD12EN:1; +// unsigned long RIDXC:2; +// unsigned long RCRC7C:2; +// unsigned long :1; +// unsigned long CRC16C:1; +// unsigned long BOOTACK:1; +// unsigned long CRCSTE:1; +// unsigned long TBIT:1; +// unsigned long OPDM:1; +// unsigned long :2; +// unsigned long SBIT:1; +// unsigned long :1; +// unsigned long DATW:2; +// } BIT; + } CECMDSET; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long ARG:32; + } BIT; + } CEARG; + union { + unsigned long LONG; + struct { + unsigned long C12ARG:32; + } BIT; + } CEARGCMD12; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long BREAK:1; + } BIT; + } CECMDCTRL; + union { + unsigned long LONG; + struct { + unsigned long BLKCNT:16; + unsigned long BLKSIZ:16; + } BIT; + } CEBLOCKSET; + union { + unsigned long LONG; + struct { + unsigned long MMCBUSBSY:1; + unsigned long :6; + unsigned long CLKEN:1; + unsigned long :4; + unsigned long CLKDIV:4; + unsigned long :2; + unsigned long SRSPTO:2; + unsigned long SRBSYTO:4; + unsigned long SRWDTO:4; + } BIT; + } CECLKCTRL; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long DMATYP:1; + unsigned long DMAWEN:1; + unsigned long DMAREN:1; + unsigned long :7; + unsigned long ATYP:1; + } BIT; + } CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union { + unsigned long LONG; + struct { + unsigned long RSP12:32; + } BIT; + } CERESPCMD12; + union { + unsigned long LONG; +// struct { +// unsigned long DATA:32; +// } BIT; + } CEDATA; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long SBTCLKDIV:4; + unsigned long SBTACKTO:4; + unsigned long SFSTBTDATTO:4; + unsigned long SBTDATTO:4; + } BIT; + } CEBOOT; + union { + unsigned long LONG; +// struct { +// unsigned long :5; +// unsigned long CMD12DRE:1; +// unsigned long CMD12RBE:1; +// unsigned long CMD12CRE:1; +// unsigned long DTRANE:1; +// unsigned long BUFRE:1; +// unsigned long BUFWEN:1; +// unsigned long BUFREN:1; +// unsigned long :2; +// unsigned long RBSYE:1; +// unsigned long CRSPE:1; +// unsigned long CMDVIO:1; +// unsigned long BUFVIO:1; +// unsigned long :2; +// unsigned long WDATERR:1; +// unsigned long RDATERR:1; +// unsigned long RIDXERR:1; +// unsigned long RSPERR:1; +// unsigned long :3; +// unsigned long CRCSTO:1; +// unsigned long WDATTO:1; +// unsigned long RDATTO:1; +// unsigned long RBSYTO:1; +// unsigned long RSPTO:1; +// } BIT; + } CEINT; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long MCMD12DRE:1; + unsigned long MCMD12RBE:1; + unsigned long MCMD12CRE:1; + unsigned long MDTRANE:1; + unsigned long MBUFRE:1; + unsigned long MBUFWEN:1; + unsigned long MBUFREN:1; + unsigned long :2; + unsigned long MRBSYE:1; + unsigned long MCRSPE:1; + unsigned long MCMDVIO:1; + unsigned long MBUFVIO:1; + unsigned long :2; + unsigned long MWDATERR:1; + unsigned long MRDATERR:1; + unsigned long MRIDXERR:1; + unsigned long MRSPERR:1; + unsigned long :3; + unsigned long MCRCSTO:1; + unsigned long MWDATTO:1; + unsigned long MRDATTO:1; + unsigned long MRBSYTO:1; + unsigned long MRSPTO:1; + } BIT; + } CEINTEN; + union { + unsigned long LONG; + struct { + unsigned long CMDSEQ:1; + unsigned long CMDSIG:1; + unsigned long RSPIDX:6; + unsigned long DATSIG:8; + unsigned long RCVBLK:16; + } BIT; + } CEHOSTSTS1; + union { + unsigned long LONG; + struct { + unsigned long CRCSTE:1; + unsigned long CRC16E:1; + unsigned long AC12CRCE:1; + unsigned long RSPCRC7E:1; + unsigned long CRCSTEBE:1; + unsigned long RDATEBE:1; + unsigned long AC12REBE:1; + unsigned long RSPEBE:1; + unsigned long AC12IDXE:1; + unsigned long RSPIDXE:1; + unsigned long BTACKPATE:1; + unsigned long BTACKEBE:1; + unsigned long :1; + unsigned long CRCST:3; + unsigned long :1; + unsigned long STRDATTO:1; + unsigned long DATBSYTO:1; + unsigned long CRCSTTO:1; + unsigned long AC12BSYTO:1; + unsigned long RSPBSYTO:1; + unsigned long AC12RSPTO:1; + unsigned long STRSPTO:1; + unsigned long BTACKTO:1; + unsigned long FSTBTDATTO:1; + unsigned long BTDATTO:1; + } BIT; + } CEHOSTSTS2; + char wk2[32]; + union { + unsigned long LONG; +// struct { +// unsigned long :17; +// unsigned long CDSIG:1; +// unsigned long CDRISE:1; +// unsigned long CDFALL:1; +// unsigned long :6; +// unsigned long MCDRISE:1; +// unsigned long MCDFALL:1; +// } BIT; + } CEDETECT; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long RESNOUT:1; + unsigned long :1; + unsigned long CLKMAIN:1; + } BIT; + } CEADDMODE; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long SWRST:1; + unsigned long :15; + unsigned long VERSION:16; + } BIT; + } CEVERSION; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char BCLKO:1; + unsigned char ADRHMS2:1; + unsigned char ADRHMS:1; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char SDCLKE:1; + unsigned char DQM1E:1; + unsigned char :1; + unsigned char MDSDE:1; + unsigned char ALES:1; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + char wk1[6]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PHYMODE1:1; + unsigned char PHYMODE0:1; + } BIT; + } PFENET; + char wk2[16]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P56PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P60PFS; + char wk9[5]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P67PFS; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P83PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P96PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P97PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF2PFS; + char wk12[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PF5PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG7PFS; + char wk14[11]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ3PFS; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ5PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MPEN:1; + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long UBAC:3; + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long CLR:1; + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long DRW:1; + unsigned long DMPER:1; + unsigned long IMPER:1; + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long DEA:32; + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long SA:32; + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short S:1; + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short INV:1; + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITI:8; + unsigned long :12; + unsigned long UHACI:3; + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITD:8; + unsigned long :12; + unsigned long UHACD:3; + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4COR:3; + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4CNT:3; + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :2; + unsigned char CST8:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + unsigned char SCH0:1; + unsigned char SCH1:1; + unsigned char SCH2:1; + unsigned char SCH3:1; + unsigned char SCH4:1; + unsigned char :1; + unsigned char SCH6:1; + unsigned char SCH7:1; + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE7D:1; + unsigned char OE7C:1; + unsigned char OE6D:1; + unsigned char OE7B:1; + unsigned char OE7A:1; + unsigned char OE6B:1; + } BIT; + } TOERB; + char wk12[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + unsigned char T6AEN:1; + unsigned char T6ACOR:3; + unsigned char T7VEN:1; + unsigned char T7VCOR:3; + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T6ACNT:3; + unsigned char :1; + unsigned char T7VCNT:3; + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7COR:3; + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7CNT:3; + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST7:1; + unsigned char CST6:1; + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + unsigned char SYNC7:1; + unsigned char SYNC6:1; + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERB; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char TTGE2:1; + unsigned char :5; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PHCKSEL:1; + unsigned char LWA:1; + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR3; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR4; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_mtu6 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char CE0A:1; + unsigned char CE0B:1; + unsigned char CE0C:1; + unsigned char CE0D:1; + unsigned char CE1A:1; + unsigned char CE1B:1; + unsigned char CE2A:1; + unsigned char CE2B:1; + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR6; +}; + +struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT7AE:1; + unsigned short DT7AE:1; + unsigned short UT7BE:1; + unsigned short DT7BE:1; + unsigned short ITA6AE:1; + unsigned short ITA7VE:1; + unsigned short ITB6AE:1; + unsigned short ITB7VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR7; +}; + +struct st_mtu8 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR8; + char wk0[871]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +}; + +struct st_pdc { + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long EDS:1; + unsigned long PCKDIV:3; + unsigned long PCKOE:1; + unsigned long HERIE:1; + unsigned long VERIE:1; + unsigned long UDRIE:1; + unsigned long OVIE:1; + unsigned long FEIE:1; + unsigned long DFIE:1; + unsigned long PRST:1; + unsigned long HPS:1; + unsigned long VPS:1; + unsigned long PCKE:1; + } BIT; + } PCCR0; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long PCE:1; + } BIT; + } PCCR1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long HERF:1; + unsigned long VERF:1; + unsigned long UDRF:1; + unsigned long OVRF:1; + unsigned long FEF:1; + unsigned long FEMPF:1; + unsigned long FBSY:1; + } BIT; + } PCSR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long HSYNC:1; + unsigned long VSYNC:1; + } BIT; + } PCMONR; + union { + unsigned long LONG; + } PCDR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long VSZ:12; + unsigned long :4; + unsigned long VST:12; + } BIT; + } VCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long HSZ:12; + unsigned long :4; + unsigned long HST:12; + } BIT; + } HCR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short :6; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE4F:1; + unsigned short :3; + unsigned short PIE2:1; + unsigned short :6; + unsigned short POE4M:2; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short OSF2:1; + unsigned short :5; + unsigned short OCE2:1; + unsigned short OIE2:1; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE3:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char GPT23HIZ:1; + unsigned char GPT01HIZ:1; + unsigned char MTUCH0HIZ:1; + unsigned char MTUCH67HIZ:1; + unsigned char MTUCH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MTU0DZE:1; + unsigned char MTU0CZE:1; + unsigned char MTU0BZE:1; + unsigned char MTU0AZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short MTU3BDZE:1; + unsigned short MTU4ACZE:1; + unsigned short MTU4BDZE:1; + unsigned short :5; + unsigned short MTU6BDZE:1; + unsigned short MTU7ACZE:1; + unsigned short MTU7BDZE:1; + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short GPT3ABZE:1; + unsigned short GPT2ABZE:1; + unsigned short :6; + unsigned short GPT1ABZE:1; + unsigned short GPT0ABZE:1; + } BIT; + } POECR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short IC5ADDMT67ZE:1; + unsigned short IC4ADDMT67ZE:1; + unsigned short IC3ADDMT67ZE:1; + unsigned short :1; + unsigned short IC1ADDMT67ZE:1; + unsigned short :3; + unsigned short IC5ADDMT34ZE:1; + unsigned short IC4ADDMT34ZE:1; + unsigned short IC3ADDMT34ZE:1; + unsigned short IC2ADDMT34ZE:1; + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short IC5ADDMT0ZE:1; + unsigned short IC4ADDMT0ZE:1; + unsigned short :1; + unsigned short IC2ADDMT0ZE:1; + unsigned short IC1ADDMT0ZE:1; + } BIT; + } POECR5; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IC4ADDGPT23ZE:1; + unsigned short IC3ADDGPT23ZE:1; + unsigned short IC2ADDGPT23ZE:1; + unsigned short IC1ADDGPT23ZE:1; + unsigned short :3; + unsigned short IC5ADDGPT01ZE:1; + unsigned short :1; + unsigned short IC3ADDGPT01ZE:1; + unsigned short IC2ADDGPT01ZE:1; + unsigned short IC1ADDGPT01ZE:1; + } BIT; + } POECR6; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE10F:1; + unsigned short :2; + unsigned short POE10E:1; + unsigned short PIE4:1; + unsigned short :6; + unsigned short POE10M:2; + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE11F:1; + unsigned short :2; + unsigned short POE11E:1; + unsigned short PIE5:1; + unsigned short :6; + unsigned short POE11M:2; + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OLSEN:1; + unsigned short :1; + unsigned short OLSG2B:1; + unsigned short OLSG2A:1; + unsigned short OLSG1B:1; + unsigned short OLSG1A:1; + unsigned short OLSG0B:1; + unsigned short OLSG0A:1; + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short OSTSTF:1; + unsigned short :2; + unsigned short OSTSTE:1; + } BIT; + } ICSR6; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char G0BSEL:4; + unsigned char G0ASEL:4; + } BIT; + } G0SELR; + union { + unsigned char BYTE; + struct { + unsigned char G1BSEL:4; + unsigned char G1ASEL:4; + } BIT; + } G1SELR; + union { + unsigned char BYTE; + struct { + unsigned char G2BSEL:4; + unsigned char G2ASEL:4; + } BIT; + } G2SELR; + union { + unsigned char BYTE; + struct { + unsigned char G3BSEL:4; + unsigned char G3ASEL:4; + } BIT; + } G3SELR; + union { + unsigned char BYTE; + struct { + unsigned char M0BSEL:4; + unsigned char M0ASEL:4; + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M0DSEL:4; + unsigned char M0CSEL:4; + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + unsigned char M3DSEL:4; + unsigned char M3BSEL:4; + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + unsigned char M4CSEL:4; + unsigned char M4ASEL:4; + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M4DSEL:4; + unsigned char M4BSEL:4; + } BIT; + } M4SELR2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char M4G2SEL:1; + unsigned char M4G1SEL:1; + unsigned char M3G0SEL:1; + } BIT; + } MGSELR; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :3; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :2; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PCR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +}; + +struct st_ptpedmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + unsigned long TDLAR; + char wk3[4]; + unsigned long RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long :1; + unsigned long RFCOF:1; + unsigned long ADE:1; + unsigned long :1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :7; + unsigned long MACE:1; + unsigned long RPORT:1; + unsigned long :2; + unsigned long PVER:1; + unsigned long TYPE:4; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long :1; + unsigned long RFCOFIP:1; + unsigned long ADEIP:1; + unsigned long :1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :7; + unsigned long MACEIP:1; + unsigned long RPORTIP:1; + unsigned long :2; + unsigned long PVERIP:1; + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPORTCE:1; + unsigned long :2; + unsigned long PVERCE:1; + unsigned long TYPECE:4; + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long ELB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + unsigned long RBWAR; + unsigned long RDFAR; + char wk14[4]; + unsigned long TBRAR; + unsigned long TDFAR; +}; + +struct st_qspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char :1; + unsigned char MSTR:1; + unsigned char :1; + unsigned char SPSSLIE:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SSLP:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char IO3FV:1; + unsigned char IO2FV:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRFF:1; + unsigned char TREND:1; + unsigned char SPTEF:1; + unsigned char SPSSLF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSC:2; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSS:2; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPBR7:1; + unsigned char SPBR6:1; + unsigned char SPBR5:1; + unsigned char SPBR4:1; + unsigned char SPBR3:1; + unsigned char SPBR2:1; + unsigned char SPBR1:1; + unsigned char SPBR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char TXDMY:1; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned char BYTE; + struct { + unsigned char TXRST:1; + unsigned char RXRST:1; + unsigned char TXTRG:2; + unsigned char TXTRGEX:1; + unsigned char RXTRG:3; + } BIT; + } SPBFCR; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TXBC:6; + unsigned short :2; + unsigned short RXBC:6; + } BIT; + } SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +}; + +struct st_ram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMODE:2; + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RAMERR:1; + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char RAMPRCR:1; + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long READ:16; + unsigned long :3; + } BIT; + } RAMECAD; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char :1; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SCKASE:1; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ENB:8; + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RCKSEL:1; + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RFC:1; + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + unsigned short RFC:16; + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk21[13]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP0:8; + } BIT; + } BCNT0CP0; + }; + char wk22[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP0:8; + } BIT; + } BCNT1CP0; + }; + char wk23[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP0:8; + } BIT; + } BCNT2CP0; + }; + char wk24[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP0:8; + } BIT; + } BCNT3CP0; + }; + char wk25[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk26[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP1:8; + } BIT; + } BCNT0CP1; + }; + char wk27[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP1:8; + } BIT; + } BCNT1CP1; + }; + char wk28[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP1:8; + } BIT; + } BCNT2CP1; + }; + char wk29[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP1:8; + } BIT; + } BCNT3CP1; + }; + char wk30[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk31[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP2:8; + } BIT; + } BCNT0CP2; + }; + char wk32[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP2:8; + } BIT; + } BCNT1CP2; + }; + char wk33[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP2:8; + } BIT; + } BCNT2CP2; + }; + char wk34[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNCP2:8; + } BIT; + } BCNT3CP2; + }; + char wk35[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short ANSA0:16; + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short ADS0:16; + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :5; + unsigned char ADC:2; + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned short ANSB0:16; + } BIT; + } ADANSB0; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short AD:12; + } BIT; + } ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[48]; + unsigned char ADSSTR0; + char wk8[5]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SHANS:3; + unsigned short SSTSH:8; + } BIT; + } ADSHCR; + char wk9[11]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk9a[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHMD:1; + } BIT; + } ADSHMSR; + char wk10[3]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short :13; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk11[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk12[8]; + union { + unsigned char BYTE; + struct { + unsigned char CMPIE:1; + unsigned char WCMPE:1; + } BIT; + } ADCMPCR; + char wk13[3]; + union { + unsigned short WORD; + struct { + unsigned short CMPS0:16; + } BIT; + } ADCMPANSR0; + char wk14[2]; + union { + unsigned short WORD; + struct { + unsigned short CMPL0:16; + } BIT; + } ADCMPLR0; + char wk15[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short CMPF0:16; + } BIT; + } ADCMPSR0; +}; + +struct st_s12ad1 { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short ANSA0:16; + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSA1:5; + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + unsigned short ADS0:16; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ADS1:5; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :5; + unsigned char ADC:2; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short EXOEN:1; + unsigned short EXSEL:2; + unsigned short :1; + unsigned short OCSB:1; + unsigned short TSSB:1; + unsigned short OCSA:1; + unsigned short TSSA:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + unsigned short ANSB0:16; + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSB1:5; + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[22]; + unsigned char ADSSTR0; + unsigned char ADSSTRL; + char wk3[14]; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + char wk4[1]; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk5[5]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short :13; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[8]; + union { + unsigned char BYTE; + struct { + unsigned char CMPIE:1; + unsigned char WCMPE:1; + } BIT; + } ADCMPCR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPSOC:1; + unsigned char CMPSTS:1; + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPLOC:1; + unsigned char CMPLTS:1; + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + unsigned short CMPS0:16; + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPS1:5; + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + unsigned short CMPL0:16; + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPL1:5; + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short CMPF0:16; + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPF1:5; + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPFOC:1; + unsigned char CMPFTS:1; + } BIT; + } ADCMPSER; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_scifa { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CM:1; + unsigned short CHR:1; + unsigned short PE:1; + unsigned short PM:1; + unsigned short STOP:1; + unsigned short :1; + unsigned short CKS:2; + } BIT; + } SMR; +// unsigned char BRR; + union { + unsigned char BRR; + unsigned char MDDR; + }; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TIE:1; + unsigned short RIE:1; + unsigned short TE:1; + unsigned short RE:1; + unsigned short REIE:1; + unsigned short TEIE:1; + unsigned short CKE:2; + } BIT; + } SCR; + unsigned char FTDR; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ER:1; + unsigned short TEND:1; + unsigned short TDFE:1; + unsigned short BRK:1; + unsigned short FER:1; + unsigned short PER:1; + unsigned short RDF:1; + unsigned short DR:1; + } BIT; + } FSR; + unsigned char FRDR; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short RSTRG:3; + unsigned short RTRG:2; + unsigned short TTRG:2; + unsigned short MCE:1; + unsigned short TFRST:1; + unsigned short RFRST:1; + unsigned short LOOP:1; + } BIT; + } FCR; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short T:5; + unsigned short :3; + unsigned short R:5; + } BIT; + } FDR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short RTS2IO:1; + unsigned short RTS2DT:1; + unsigned short CTS2IO:1; + unsigned short CTS2DT:1; + unsigned short SCKIO:1; + unsigned short SCKDT:1; + unsigned short SPB2IO:1; + unsigned short SPB2DT:1; + } BIT; + } SPTR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short PER:4; + unsigned short :2; + unsigned short FER:4; + unsigned short :1; + unsigned short ORER:1; + } BIT; + } LSR; + union { + unsigned char BYTE; + struct { + unsigned char BGDM:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char MDDRS:1; + unsigned char DIR:1; + unsigned char NFEN:1; + unsigned char :1; + unsigned char ABCS0:1; + } BIT; + } SEMR; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short RTRGS:1; + unsigned short :2; + unsigned short RFTC:5; + unsigned short TTRGS:1; + unsigned short :2; + unsigned short TFTC:5; + } BIT; + } FTCR; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long SDBLKCNTEN:1; + unsigned long :7; + unsigned long STP:1; + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long SDD3INM:1; + unsigned long SDD3RMM:1; + unsigned long :3; + unsigned long SDCDINM:1; + unsigned long SDCDRMM:1; + unsigned long ACENDM:1; + unsigned long :1; + unsigned long RSPENDM:1; + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILAM:1; + unsigned long :5; + unsigned long BWEM:1; + unsigned long BREM:1; + unsigned long :1; + unsigned long RSPTOM:1; + unsigned long ILRM:1; + unsigned long ILWM:1; + unsigned long DTTOM:1; + unsigned long ENDEM:1; + unsigned long CRCEM:1; + unsigned long CMDEM:1; + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long CLKCTRLEN:1; + unsigned long CLKEN:1; + unsigned long CLKSEL:8; + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long LEN:10; + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long WIDTH:1; + unsigned long :7; + unsigned long TOP:4; + unsigned long CTOP:4; + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CRCTK:3; + unsigned long CRCTKE:1; + unsigned long RDCRCE:1; + unsigned long RSPCRCE1:1; + unsigned long RSPCRCE0:1; + unsigned long :2; + unsigned long CRCLENE:1; + unsigned long RDLENE:1; + unsigned long RSPLENE1:1; + unsigned long RSPLENE0:1; + unsigned long CMDE1:1; + unsigned long CMDE0:1; + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long CRCBSYTO:1; + unsigned long CRCTO:1; + unsigned long RDTO:1; + unsigned long BSYTO1:1; + unsigned long BSYTO0:1; + unsigned long RSPTO1:1; + unsigned long RSPTO0:1; + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long C52PUB:1; + unsigned long IOABT:1; + unsigned long :5; + unsigned long RWREQ:1; + unsigned long :1; + unsigned long INTEN:1; + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWTM:1; + unsigned long EXPUB52M:1; + unsigned long :13; + unsigned long IOIRQM:1; + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long DMAEN:1; + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SDRST:1; + } BIT; + } SDRST; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CPRM:1; + unsigned long CLKRAT:1; + unsigned long :2; + unsigned long IP2:4; + unsigned long IP1:8; + } BIT; + } SDVER; + char wk10[24]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long BRSWP:1; + unsigned long BWSWP:1; + } BIT; + } SDSWAP; +}; + +struct st_smci0 { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_src { + union { + unsigned long LONG; + } SRCFCTR[5552]; + char wk0[2352]; + union { + unsigned long LONG; + } SRCID; + union { + unsigned long LONG; + } SRCOD; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short IED:1; + unsigned short IEN:1; + unsigned short :6; + unsigned short IFTRG:2; + } BIT; + } SRCIDCTRL; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short OCH:1; + unsigned short OED:1; + unsigned short OEN:1; + unsigned short :6; + unsigned short OFTRG:2; + } BIT; + } SRCODCTRL; + union { + unsigned short WORD; + struct { + unsigned short FICRAE:1; + unsigned short :1; + unsigned short CEEN:1; + unsigned short SRCEN:1; + unsigned short UDEN:1; + unsigned short OVEN:1; + unsigned short FL:1; + unsigned short CL:1; + unsigned short IFS:4; + unsigned short :1; + unsigned short OFS:3; + } BIT; + } SRCCTRL; + union { + unsigned short WORD; + struct { + unsigned short OFDN:5; + unsigned short IFDN:4; + unsigned short :1; + unsigned short CEF:1; + unsigned short FLF:1; + unsigned short UDF:1; + unsigned short OVF:1; + unsigned short IINT:1; + unsigned short OINT:1; + } BIT; + } SRCSTAT; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CKS:1; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long CHNL:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long SCKD:1; + unsigned long SWSD:1; + unsigned long SCKP:1; + unsigned long SWSP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :18; + unsigned long TCHNO:2; + unsigned long TSWNO:1; + unsigned long RCHNO:2; + unsigned long RSWNO:1; + unsigned long IDST:1; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :8; + unsigned long TTRG:2; + unsigned long RTRG:2; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TDC:4; + unsigned long :7; + unsigned long TDE:1; + unsigned long :4; + unsigned long RDC:4; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long CONT:1; + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short UBTS:1; + } BIT; + } MDSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SBYRAME:1; + unsigned short ECCRAME:1; + unsigned short :5; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long MSTPA27:1; + unsigned long :2; + unsigned long MSTPA24:1; + unsigned long :4; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long MSTPA16:1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long :1; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long :1; + unsigned long MSTPA7:1; + unsigned long :1; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :2; + unsigned long MSTPA1:1; + unsigned long MSTPA0:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long MSTPB27:1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long MSTPB24:1; + unsigned long MSTPB23:1; + unsigned long MSTPB22:1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long MSTPB15:1; + unsigned long MSTPB14:1; + unsigned long :1; + unsigned long MSTPB12:1; + unsigned long :2; + unsigned long MSTPB9:1; + unsigned long MSTPB8:1; + unsigned long :1; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + unsigned long :1; + unsigned long MSTPB2:1; + unsigned long MSTPB1:1; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long MSTPC25:1; + unsigned long MSTPC24:1; + unsigned long MSTPC23:1; + unsigned long :3; + unsigned long MSTPC19:1; + unsigned long :1; + unsigned long MSTPC17:1; + unsigned long :9; + unsigned long MSTPC7:1; + unsigned long MSTPC6:1; + unsigned long :5; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MSTPD23:1; + unsigned long :1; + unsigned long MSTPD21:1; + unsigned long :1; + unsigned long MSTPD19:1; + unsigned long :3; + unsigned long MSTPD15:1; + unsigned long MSTPD14:1; + unsigned long :6; + unsigned long MSTPD7:1; + unsigned long MSTPD6:1; + unsigned long MSTPD5:1; + unsigned long MSTPD4:1; + unsigned long MSTPD3:1; + unsigned long MSTPD2:1; + unsigned long MSTPD1:1; + unsigned long MSTPD0:1; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long PSTOP0:1; + unsigned long :2; + unsigned long BCK:4; + unsigned long PCKA:4; + unsigned long PCKB:4; + unsigned long PCKC:4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short UCK:4; + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :3; + unsigned short PLLSRCSEL:1; + unsigned short :2; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk3[5]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char HCFRQ:2; + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ILCOVF:1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char SOOVF:1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk7[94]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char MSTS:8; + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + unsigned char SSTS:8; + } BIT; + } SOSCWTCR; + char wk8[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk9[1]; + unsigned short SWRR; + char wk10[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk11[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short :1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk12a[25104]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MEMWAIT:1; + } BIT; + } MEMWAIT; + char wk12b[23660]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char :4; + unsigned char DEEPCUT:2; + } BIT; + } DPSBYCR; + char wk13[1]; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7E:1; + unsigned char DIRQ6E:1; + unsigned char DIRQ5E:1; + unsigned char DIRQ4E:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15E:1; + unsigned char DIRQ14E:1; + unsigned char DIRQ13E:1; + unsigned char DIRQ12E:1; + unsigned char DIRQ11E:1; + unsigned char DIRQ10E:1; + unsigned char DIRQ9E:1; + unsigned char DIRQ8E:1; + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIE:1; + unsigned char DRIICCIE:1; + unsigned char DRIICDIE:1; + unsigned char DNMIE:1; + unsigned char DRTCAIE:1; + unsigned char DRTCIIE:1; + unsigned char DLVD2IE:1; + unsigned char DLVD1IE:1; + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIE:1; + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7F:1; + unsigned char DIRQ6F:1; + unsigned char DIRQ5F:1; + unsigned char DIRQ4F:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15F:1; + unsigned char DIRQ14F:1; + unsigned char DIRQ13F:1; + unsigned char DIRQ12F:1; + unsigned char DIRQ11F:1; + unsigned char DIRQ10F:1; + unsigned char DIRQ9F:1; + unsigned char DIRQ8F:1; + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIF:1; + unsigned char DRIICCIF:1; + unsigned char DRIICDIF:1; + unsigned char DNMIF:1; + unsigned char DRTCAIF:1; + unsigned char DRTCIIF:1; + unsigned char DLVD2IF:1; + unsigned char DLVD1IF:1; + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIF:1; + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7EG:1; + unsigned char DIRQ6EG:1; + unsigned char DIRQ5EG:1; + unsigned char DIRQ4EG:1; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15EG:1; + unsigned char DIRQ14EG:1; + unsigned char DIRQ13EG:1; + unsigned char DIRQ12EG:1; + unsigned char DIRQ11EG:1; + unsigned char DIRQ10EG:1; + unsigned char DIRQ9EG:1; + unsigned char DIRQ8EG:1; + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DRIICCEG:1; + unsigned char DRIICDEG:1; + unsigned char DNMIEG:1; + unsigned char :2; + unsigned char DLVD2EG:1; + unsigned char DLVD1EG:1; + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIEG:1; + } BIT; + } DPSIEGR3; + char wk14[2]; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :3; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV2:2; + unsigned char :3; + unsigned char MOFXIN:1; + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HOCOPCNT:1; + } BIT; + } HOCOPCR; + char wk16[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2LVL:4; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk17[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char LVD1FSAMP:2; + unsigned char :1; + unsigned char LVD1CMPE:1; + unsigned char LVD1DFDIS:1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char LVD2FSAMP:2; + unsigned char :1; + unsigned char LVD2CMPE:1; + unsigned char LVD2DFDIS:1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk18[4]; + unsigned char DPSBKR[32]; +}; + +struct st_temps { + union { + unsigned char BYTE; + struct { + unsigned char TSEN:1; + unsigned char :2; + unsigned char TSOE:1; + } BIT; + } TSCR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpua { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBSTS0:1; + unsigned long :1; + unsigned long DOVCB0:1; + unsigned long DOVCA0:1; + unsigned long :2; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :11; + unsigned long FIXPHY0:1; + unsigned long DRPD0:1; + unsigned long :1; + unsigned long RPUE0:1; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBINT0:1; + unsigned long :1; + unsigned long DOVRCRB0:1; + unsigned long DOVRCRA0:1; + unsigned long :2; + unsigned long DMINT0:1; + unsigned long DPINT0:1; + unsigned long :8; + unsigned long DVBSE0:1; + unsigned long :1; + unsigned long DOVRCRBE0:1; + unsigned long DOVRCRAE0:1; + unsigned long :2; + unsigned long DMINTE0:1; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :3; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short :3; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short SOFEA:1; + unsigned short :2; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD5; + char wk16[20]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long SLEWF01:1; + unsigned long SLEWF00:1; + unsigned long SLEWR01:1; + unsigned long SLEWR00:1; + } BIT; + } PHYSLEW; +}; + +struct st_usba { + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short CNEN:1; +// unsigned short HSE:1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short :3; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short BWAIT:4; +// } BIT; + } BUSWAIT; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short SOFEA:1; + unsigned short :2; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short PLLLOCK:1; + } BIT; + } PLLSTA; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk0[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short UTST:4; +// } BIT; + } TESTMODE; + char wk1[6]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } CFIFO; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } D0FIFO; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + } D1FIFO; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :2; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } CFIFOCTR; + char wk2[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short MBW:2; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :1; +// unsigned short DTLN:12; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :1; +// unsigned short L1RSMENDE:1; +// unsigned short LPMENDE:1; +// unsigned short :1; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE:1; +// } BIT; + } INTENB1; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short INTL:1; +// unsigned short EDGESTS:1; +// } BIT; + } SOFCFG; + union { + unsigned short WORD; +// struct { +// unsigned short HSEB:1; +// unsigned short :5; +// unsigned short REPSEL:2; +// unsigned short :2; +// unsigned short CLKSEL:2; +// unsigned short CDPEN:1; +// unsigned short :1; +// unsigned short PLLRESET:1; +// unsigned short DIRPD:1; +// } BIT; + } PHYSET; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :1; +// unsigned short L1RSMEND:1; +// unsigned short LPMEND:1; +// unsigned short :1; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT:1; +// } BIT; + } INTSTS1; + char wk4[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPEBRDY:10; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPENRDY:10; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPEBEMP:10; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short :13; + unsigned short UFRNM:3; + } BIT; + } UFRMNUM; + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short CNTMD:1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk6[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk7[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short CNTMD:1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short BUFSIZE:5; +// unsigned short :2; +// unsigned short BUFNMB:8; +// } BIT; + } PIPEBUF; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :1; +// unsigned short MXPS:11; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk8[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE1TRE; + union { + unsigned short WORD; + struct { + unsigned short TRNCNT:16; + } BIT; + } PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE2TRE; + union { + unsigned short WORD; + struct { + unsigned short TRNCNT:16; + } BIT; + } PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE3TRE; + union { + unsigned short WORD; + struct { + unsigned short TRNCNT:16; + } BIT; + } PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE4TRE; + union { + unsigned short WORD; + struct { + unsigned short TRNCNT:16; + } BIT; + } PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// } BIT; + } PIPE5TRE; + union { + unsigned short WORD; + struct { + unsigned short TRNCNT:16; + } BIT; + } PIPE5TRN; + char wk9[44]; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short UPPHUB:4; +// unsigned short HUBPORT:3; +// unsigned short USBSPD:2; +// } BIT; + } DEVADD5; + char wk10[36]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short HWUPM:1; +// } BIT; + } LPCTRL; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short SUSPENDM:1; +// } BIT; + } LPSTS; + char wk11[60]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PDDETSTS:1; +// unsigned short CHGDETSTS:1; +// unsigned short :3; +// unsigned short VDMSRCE:1; +// unsigned short IDPSINKE:1; +// unsigned short VDPSRCE:1; +// unsigned short IDMSINKE:1; +// unsigned short IDPSRCE:1; +// } BIT; + } BCCTRL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :1; +// unsigned short L1EXTMD:1; +// unsigned short :2; +// unsigned short HIRDTHR:4; +// unsigned short DVSQ:4; +// unsigned short L1NEGOMD:1; +// unsigned short L1RESPMD:2; +// unsigned short L1RESPEN:1; +// } BIT; + } PL1CTRL1; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short RWEMON:1; +// unsigned short HIRDMON:4; +// } BIT; + } PL1CTRL2; + union { + unsigned short WORD; +// struct { +// unsigned short :13; +// unsigned short L1STATUS:2; +// unsigned short L1REQ:1; +// } BIT; + } HL1CTRL1; + union { + unsigned short WORD; +// struct { +// unsigned short BESL:1; +// unsigned short :2; +// unsigned short L1RWE:1; +// unsigned short HIRD:4; +// unsigned short :4; +// unsigned short L1ADDR:4; +// } BIT; + } HL1CTRL2; + char wk13[20]; + union { + unsigned long LONG; +// struct { +// unsigned long :8; +// unsigned long DVBSTSHM:1; +// unsigned long :1; +// unsigned long DOVCBHM:1; +// unsigned long DOVCAHM:1; +// } BIT; + } DPUSR0R; + union { + unsigned long LONG; +// struct { +// unsigned long :8; +// unsigned long DVBSTSH:1; +// unsigned long :1; +// unsigned long DOVCBH:1; +// unsigned long DOVCAH:1; +// unsigned long :12; +// unsigned long DVBSTSHE:1; +// unsigned long :1; +// unsigned long DOVCBHE:1; +// unsigned long DOVCAHE:1; +// } BIT; + } DPUSR1R; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_RAM_RAMERR=18, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMTW0_CMWI0, +IR_CMTW1_CMWI1, +IR_USBA_D0FIFO2,IR_USBA_D1FIFO2, +IR_USB0_D0FIFO0,IR_USB0_D1FIFO0, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1, +IR_QSPI_SPRI=42,IR_QSPI_SPTI, +IR_SDHI_SBFAI, +IR_MMCIF_MBFAI, +IR_SSI0_SSITXI0,IR_SSI0_SSIRXI0, +IR_SSI1_SSIRTI1, +IR_SRC_IDEI=50,IR_SRC_ODFI, +IR_RIIC0_RXI0,IR_RIIC0_TXI0, +IR_RIIC2_RXI2,IR_RIIC2_TXI2, +IR_SCI0_RXI0=58,IR_SCI0_TXI0, +IR_SCI1_RXI1,IR_SCI1_TXI1, +IR_SCI2_RXI2,IR_SCI2_TXI2, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI3_RXI3,IR_SCI3_TXI3, +IR_SCI4_RXI4,IR_SCI4_TXI4, +IR_SCI5_RXI5,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_USBA_USBAR, +IR_IWDT_IWUNI, +IR_WDT_WUNI, +IR_PDC_PCDFI, +IR_SCI7_RXI7,IR_SCI7_TXI7, +IR_SCIFA8_RXIF8,IR_SCIFA8_TXIF8, +IR_SCIFA9_RXIF9,IR_SCIFA9_TXIF9, +IR_SCIFA10_RXIF10,IR_SCIFA10_TXIF10, +IR_ICU_GROUPBE0,IR_ICU_GROUPBL0=110,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_SCIFA11_RXIF11,IR_SCIFA11_TXIF11, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OST, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132, +IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137, +IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142, +IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147, +IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152, +IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157, +IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162, +IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167, +IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172, +IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177, +IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182, +IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187, +IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192, +IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197, +IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202, +IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207, +IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212, +IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217, +IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222, +IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227, +IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232, +IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242, +IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247, +IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252, +IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +}; + +enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USBA_D0FIFO2,DTCE_USBA_D1FIFO2, +DTCE_USB0_D0FIFO0,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI=42,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSI0_SSITXI0,DTCE_SSI0_SSIRXI0, +DTCE_SSI1_SSIRTI1, +DTCE_SRC_IDEI=50,DTCE_SRC_ODFI, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI=97, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCIFA8_RXIF8,DTCE_SCIFA8_TXIF8, +DTCE_SCIFA9_RXIF9,DTCE_SCIFA9_TXIF9, +DTCE_SCIFA10_RXIF10,DTCE_SCIFA10_TXIF10, +DTCE_SCIFA11_RXIF11=114,DTCE_SCIFA11_TXIF11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMTW0_CMWI0=0x03, +IER_CMTW1_CMWI1=0x03, +IER_USBA_D0FIFO2=0x04,IER_USBA_D1FIFO2=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05, +IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05, +IER_SDHI_SBFAI=0x05, +IER_MMCIF_MBFAI=0x05, +IER_SSI0_SSITXI0=0x05,IER_SSI0_SSIRXI0=0x05, +IER_SSI1_SSIRTI1=0x06, +IER_SRC_IDEI=0x06,IER_SRC_ODFI=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06, +IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A, +IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_USBA_USBAR=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_PDC_PCDFI=0x0C, +IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C, +IER_SCIFA8_RXIF8=0x0C,IER_SCIFA8_TXIF8=0x0C, +IER_SCIFA9_RXIF9=0x0C,IER_SCIFA9_TXIF9=0x0C, +IER_SCIFA10_RXIF10=0x0D,IER_SCIFA10_TXIF10=0x0D, +IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_SCIFA11_RXIF11=0x0E,IER_SCIFA11_TXIF11=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OST=0x0F, +IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F, +IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10, +IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11, +IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11, +IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12, +IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13, +IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13, +IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14, +IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14, +IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15, +IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16, +IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16, +IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17, +IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18, +IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18, +IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19, +IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A, +IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B, +IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B, +IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C, +IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D, +IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D, +IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E, +IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F, +IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMTW0_CMWI0=6, +IPR_CMTW1_CMWI1=7, +IPR_USBA_D0FIFO2=32,IPR_USBA_D1FIFO2=33, +IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41, +IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43, +IPR_SDHI_SBFAI=44, +IPR_MMCIF_MBFAI=45, +IPR_SSI0_SSITXI0=46,IPR_SSI0_SSIRXI0=47, +IPR_SSI1_SSIRTI1=48, +IPR_SRC_IDEI=50,IPR_SRC_ODFI=51, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55, +IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81, +IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_USBA_USBAR=94, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_PDC_PCDFI=97, +IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99, +IPR_SCIFA8_RXIF8=100,IPR_SCIFA8_TXIF8=101, +IPR_SCIFA9_RXIF9=102,IPR_SCIFA9_TXIF9=103, +IPR_SCIFA10_RXIF10=104,IPR_SCIFA10_TXIF10=105, +IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_SCIFA11_RXIF11=114,IPR_SCIFA11_TXIF11=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OST=125, +IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127, +IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132, +IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137, +IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142, +IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147, +IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152, +IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157, +IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162, +IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167, +IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172, +IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177, +IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182, +IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187, +IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192, +IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197, +IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202, +IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212, +IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217, +IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222, +IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227, +IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232, +IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242, +IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247, +IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252, +IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USBA_D0FIFO2 IEN0 +#define IEN_USBA_D1FIFO2 IEN1 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SSI0_SSIRXI0 IEN7 +#define IEN_SSI1_SSIRTI1 IEN0 +#define IEN_SRC_IDEI IEN2 +#define IEN_SRC_ODFI IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_USBA_USBAR IEN6 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCIFA8_RXIF8 IEN4 +#define IEN_SCIFA8_TXIF8 IEN5 +#define IEN_SCIFA9_RXIF9 IEN6 +#define IEN_SCIFA9_TXIF9 IEN7 +#define IEN_SCIFA10_RXIF10 IEN0 +#define IEN_SCIFA10_TXIF10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCIFA11_RXIF11 IEN2 +#define IEN_SCIFA11_TXIF11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OST IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USBA_D0FIFO2 32 +#define VECT_USBA_D1FIFO2 33 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_SSI0_SSITXI0 46 +#define VECT_SSI0_SSIRXI0 47 +#define VECT_SSI1_SSIRTI1 48 +#define VECT_SRC_IDEI 50 +#define VECT_SRC_ODFI 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_USBA_USBAR 94 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCIFA8_RXIF8 100 +#define VECT_SCIFA8_TXIF8 101 +#define VECT_SCIFA9_RXIF9 102 +#define VECT_SCIFA9_TXIF9 103 +#define VECT_SCIFA10_RXIF10 104 +#define VECT_SCIFA10_TXIF10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCIFA11_RXIF11 114 +#define VECT_SCIFA11_TXIF11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OST 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPT SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPT3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_EDMAC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_USBA SYSTEM.MSTPCRB.BIT.MSTPB12 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCIFA8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCIFA9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCIFA10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCIFA11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_ECCRAM SYSTEM.MSTPCRC.BIT.MSTPC6 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SRC SYSTEM.MSTPCRD.BIT.MSTPD23 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_SSI1 SYSTEM.MSTPCRD.BIT.MSTPD14 + +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI7_TEI7 IS14 +#define IS_SCI7_ERI7 IS15 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRF IS26 +#define IS_CAC_MENDF IS27 +#define IS_CAC_OVFF IS28 +#define IS_DOC_DOPCF IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SRC_PCERI IS0 +#define IS_SRC_OVF IS1 +#define IS_SRC_CEF IS2 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_SSI0_SSIF0 IS17 +#define IS_SSI1_SSIF1 IS18 +#define IS_S12AD0_S12CMPI0 IS20 +#define IS_S12AD1_S12CMPI1 IS22 +#define IS_SCIFA8_TEIF8 IS0 +#define IS_SCIFA8_ERIF8 IS1 +#define IS_SCIFA8_BRIF8 IS2 +#define IS_SCIFA8_DRIF8 IS3 +#define IS_SCIFA9_TEIF9 IS4 +#define IS_SCIFA9_ERIF9 IS5 +#define IS_SCIFA9_BRIF9 IS6 +#define IS_SCIFA9_DRIF9 IS7 +#define IS_SCIFA10_TEIF10 IS8 +#define IS_SCIFA10_ERIF10 IS9 +#define IS_SCIFA10_BRIF10 IS10 +#define IS_SCIFA10_DRIF10 IS11 +#define IS_SCIFA11_TEIF11 IS12 +#define IS_SCIFA11_ERIF11 IS13 +#define IS_SCIFA11_BRIF11 IS14 +#define IS_SCIFA11_DRIF11 IS15 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_EPTPC_MINT IS0 +#define IS_PRPEDMAC_PINT IS1 +#define IS_EDMAC0_EINT0 IS4 +#define IS_EDMAC1_EINT1 IS5 + +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI7_TEI7 EN14 +#define EN_SCI7_ERI7 EN15 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRF EN26 +#define EN_CAC_MENDF EN27 +#define EN_CAC_OVFF EN28 +#define EN_DOC_DOPCF EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SRC_PCERI EN0 +#define EN_SRC_OVF EN1 +#define EN_SRC_CEF EN2 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_SSI0_SSIF0 EN17 +#define EN_SSI1_SSIF1 EN18 +#define EN_S12AD0_S12CMPI0 EN20 +#define EN_S12AD1_S12CMPI1 EN22 +#define EN_SCIFA8_TEIF8 EN0 +#define EN_SCIFA8_ERIF8 EN1 +#define EN_SCIFA8_BRIF8 EN2 +#define EN_SCIFA8_DRIF8 EN3 +#define EN_SCIFA9_TEIF9 EN4 +#define EN_SCIFA9_ERIF9 EN5 +#define EN_SCIFA9_BRIF9 EN6 +#define EN_SCIFA9_DRIF9 EN7 +#define EN_SCIFA10_TEIF10 EN8 +#define EN_SCIFA10_ERIF10 EN9 +#define EN_SCIFA10_BRIF10 EN10 +#define EN_SCIFA10_DRIF10 EN11 +#define EN_SCIFA11_TEIF11 EN12 +#define EN_SCIFA11_ERIF11 EN13 +#define EN_SCIFA11_BRIF11 EN14 +#define EN_SCIFA11_DRIF11 EN15 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_EPTPC_MINT EN0 +#define EN_PRPEDMAC_PINT EN1 +#define EN_EDMAC0_EINT0 EN4 +#define EN_EDMAC1_EINT1 EN5 + +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 +#define CLR_RSPI1_SPII1 CLR18 +#define CLR_RSPI1_SPEI1 CLR19 + +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_CAN2_ERS2 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI7_TEI7 GENBL0 +#define GEN_SCI7_ERI7 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRF GENBL0 +#define GEN_CAC_MENDF GENBL0 +#define GEN_CAC_OVFF GENBL0 +#define GEN_DOC_DOPCF GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SRC_PCERI GENBL1 +#define GEN_SRC_OVF GENBL1 +#define GEN_SRC_CEF GENBL1 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_SSI0_SSIF0 GENBL1 +#define GEN_SSI1_SSIF1 GENBL1 +#define GEN_S12AD0_S12CMPI0 GENBL1 +#define GEN_S12AD1_S12CMPI1 GENBL1 +#define GEN_SCIFA8_TEIF8 GENAL0 +#define GEN_SCIFA8_ERIF8 GENAL0 +#define GEN_SCIFA8_BRIF8 GENAL0 +#define GEN_SCIFA8_DRIF8 GENAL0 +#define GEN_SCIFA9_TEIF9 GENAL0 +#define GEN_SCIFA9_ERIF9 GENAL0 +#define GEN_SCIFA9_BRIF9 GENAL0 +#define GEN_SCIFA9_DRIF9 GENAL0 +#define GEN_SCIFA10_TEIF10 GENAL0 +#define GEN_SCIFA10_ERIF10 GENAL0 +#define GEN_SCIFA10_BRIF10 GENAL0 +#define GEN_SCIFA10_DRIF10 GENAL0 +#define GEN_SCIFA11_TEIF11 GENAL0 +#define GEN_SCIFA11_ERIF11 GENAL0 +#define GEN_SCIFA11_BRIF11 GENAL0 +#define GEN_SCIFA11_DRIF11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_EPTPC_MINT GENAL1 +#define GEN_PRPEDMAC_PINT GENAL1 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_EDMAC1_EINT1 GENAL1 + +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_CAN2_ERS2 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI7_TEI7 GRPBL0 +#define GRP_SCI7_ERI7 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRF GRPBL0 +#define GRP_CAC_MENDF GRPBL0 +#define GRP_CAC_OVFF GRPBL0 +#define GRP_DOC_DOPCF GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SRC_PCERI GRPBL1 +#define GRP_SRC_OVF GRPBL1 +#define GRP_SRC_CEF GRPBL1 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_SSI0_SSIF0 GRPBL1 +#define GRP_SSI1_SSIF1 GRPBL1 +#define GRP_S12AD0_S12CMPI0 GRPBL1 +#define GRP_S12AD1_S12CMPI1 GRPBL1 +#define GRP_SCIFA8_TEIF8 GRPAL0 +#define GRP_SCIFA8_ERIF8 GRPAL0 +#define GRP_SCIFA8_BRIF8 GRPAL0 +#define GRP_SCIFA8_DRIF8 GRPAL0 +#define GRP_SCIFA9_TEIF9 GRPAL0 +#define GRP_SCIFA9_ERIF9 GRPAL0 +#define GRP_SCIFA9_BRIF9 GRPAL0 +#define GRP_SCIFA9_DRIF9 GRPAL0 +#define GRP_SCIFA10_TEIF10 GRPAL0 +#define GRP_SCIFA10_ERIF10 GRPAL0 +#define GRP_SCIFA10_BRIF10 GRPAL0 +#define GRP_SCIFA10_DRIF10 GRPAL0 +#define GRP_SCIFA11_TEIF11 GRPAL0 +#define GRP_SCIFA11_ERIF11 GRPAL0 +#define GRP_SCIFA11_BRIF11 GRPAL0 +#define GRP_SCIFA11_DRIF11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_EPTPC_MINT GRPAL1 +#define GRP_PRPEDMAC_PINT GRPAL1 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_EDMAC1_EINT1 GRPAL1 + +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 +#define GCR_CAN2_ERS2 GCRBE0 +#define GCR_RSPI1_SPII1 GCRAL0 +#define GCR_RSPI1_SPEI1 GCRAL0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000) +#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200) +#define CAN1 (*(volatile struct st_can __evenaccess *)0x91200) +#define CAN2 (*(volatile struct st_can __evenaccess *)0x92200) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw __evenaccess *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw __evenaccess *)0x94280) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define DA (*(volatile struct st_da __evenaccess *)0x88040) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 __evenaccess *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 __evenaccess *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 __evenaccess *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 __evenaccess *)0x821C0) +#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define ECCRAM (*(volatile struct st_eccram __evenaccess *)0x812C0) +#define EDMAC0 (*(volatile struct st_edmac __evenaccess *)0xC0000) +#define EDMAC1 (*(volatile struct st_edmac __evenaccess *)0xC0200) +#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100) +#define EPTPC (*(volatile struct st_eptpc __evenaccess *)0xC0500) +#define EPTPC0 (*(volatile struct st_eptpc0 __evenaccess *)0xC4800) +#define EPTPC1 (*(volatile struct st_eptpc0 __evenaccess *)0xC4C00) +#define ETHERC0 (*(volatile struct st_etherc __evenaccess *)0xC0100) +#define ETHERC1 (*(volatile struct st_etherc __evenaccess *)0xC0300) +#define EXDMAC (*(volatile struct st_exdmac __evenaccess *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 __evenaccess *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 __evenaccess *)0x82840) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x8C294) +#define GPT (*(volatile struct st_gpt __evenaccess *)0xC2000) +#define GPT0 (*(volatile struct st_gpt0 __evenaccess *)0xC2100) +#define GPT1 (*(volatile struct st_gpt0 __evenaccess *)0xC2180) +#define GPT2 (*(volatile struct st_gpt0 __evenaccess *)0xC2200) +#define GPT3 (*(volatile struct st_gpt0 __evenaccess *)0xC2280) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define MMCIF (*(volatile struct st_mmcif __evenaccess *)0x88500) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100) +#define MPU (*(volatile struct st_mpu __evenaccess *)0x86400) +#define MTU (*(volatile struct st_mtu __evenaccess *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 __evenaccess *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 __evenaccess *)0xC1A00) +#define MTU8 (*(volatile struct st_mtu8 __evenaccess *)0xC1298) +#define PDC (*(volatile struct st_pdc __evenaccess *)0xA0500) +#define POE3 (*(volatile struct st_poe __evenaccess *)0x8C4C0) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006) +#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007) +#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008) +#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F) +#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0) +#define PTPEDMAC (*(volatile struct st_ptpedmac __evenaccess *)0xC0400) +#define QSPI (*(volatile struct st_qspi __evenaccess *)0x89E00) +#define RAM (*(volatile struct st_ram __evenaccess *)0x81200) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RIIC2 (*(volatile struct st_riic __evenaccess *)0x88340) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0xD0100) +#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0xD0120) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 __evenaccess *)0x89100) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 __evenaccess *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 __evenaccess *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci0 __evenaccess *)0x8A0E0) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SCIFA8 (*(volatile struct st_scifa __evenaccess *)0xD0000) +#define SCIFA9 (*(volatile struct st_scifa __evenaccess *)0xD0020) +#define SCIFA10 (*(volatile struct st_scifa __evenaccess *)0xD0040) +#define SCIFA11 (*(volatile struct st_scifa __evenaccess *)0xD0060) +#define SDHI (*(volatile struct st_sdhi __evenaccess *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci0 __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci0 __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci0 __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci0 __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci0 __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci0 __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci0 __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci0 __evenaccess *)0x8A0E0) +#define SMCI12 (*(volatile struct st_smci0 __evenaccess *)0x8B300) +#define SRC (*(volatile struct st_src __evenaccess *)0x98000) +#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500) +#define SSI1 (*(volatile struct st_ssi __evenaccess *)0x8A540) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPS (*(volatile struct st_temps __evenaccess *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C) +#define TPUA (*(volatile struct st_tpua __evenaccess *)0x88100) +#define USB (*(volatile struct st_usb __evenaccess *)0xA0400) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define USBA (*(volatile struct st_usba __evenaccess *)0xD0400) +#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020) +#pragma bit_order +#pragma packoption +#endif diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c new file mode 100644 index 000000000..9cb47b35f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c @@ -0,0 +1,250 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas code generator includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set up SCI7 receive buffer and callback function. */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + + /* Enable SCI7 operations. */ + R_SCI7_Start(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/rskrx71mdef.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/rskrx71mdef.h new file mode 100644 index 000000000..4f0e7780f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/rskrx71mdef.h @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : rskrx71mdef.h +* Device(s) : R5F571MLCxFC +* Tool-Chain : CCRX +* H/W Platform : RSK+RX71M +* Description : Defines macros relating to the RSK+RX71M user LEDs and switches +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.01.2015 1.00 First Release +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef RSKRX71M_H +#define RSKRX71M_H + + +/* General Values */ +#define LED_ON (0) +#define LED_OFF (1) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Switches */ +#define SW1 (PORT1.PIDR.BIT.B5) +#define SW2 (PORT1.PIDR.BIT.B2) +#define SW3 (PORT0.PIDR.BIT.B7) + +/* LED port settings */ +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED2 (PORT2.PODR.BIT.B6) +#define LED3 (PORT2.PODR.BIT.B7) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif + -- 2.39.5