From f35cb12511f5e0fe608adfab38ed44a29e9578ab Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 23 Oct 2015 10:50:53 -0600 Subject: [PATCH] ARM: tegra: error check Tegra210 XUSB padctl waits Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 25 +++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 6022f1614b..9ec93e7c4c 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n"); value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); @@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) break; } - + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n"); value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); @@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n"); value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); @@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n"); value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); @@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) break; } - + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n"); value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); -- 2.39.5