From f3716894c6c2ab0e16bdb073d79e4df855897c10 Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Fri, 16 Oct 2015 10:46:35 +0200 Subject: [PATCH] armv7a: fix debug messages regarding cache on/off state Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3028 Reviewed-by: Paul Fertser Tested-by: jenkins --- src/target/armv7a_cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index da617b81..89e85025 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -35,7 +35,7 @@ static int armv7a_l1_d_cache_sanity_check(struct target *target) /* check that cache data is on at target halt */ if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { - LOG_DEBUG("l1 data cache is not enabled"); + LOG_DEBUG("data cache is not enabled"); return ERROR_TARGET_INVALID; } @@ -53,7 +53,7 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target) /* check that cache data is on at target halt */ if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { - LOG_DEBUG("l1 data cache is not enabled"); + LOG_DEBUG("instruction cache is not enabled"); return ERROR_TARGET_INVALID; } -- 2.39.5