From f48b9d91ed179b35580c3468eed2a77a4c0e6d08 Mon Sep 17 00:00:00 2001 From: richardbarry Date: Sat, 27 Aug 2011 14:22:36 +0000 Subject: [PATCH] Remove some large files from the repository that don't need to be there. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1566 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../SDK/SDK_Export/hw/system.html | 12 - .../SDK/SDK_Export/hw/system_main.html | 6004 ---------------- .../SDK/SDK_Export/hw/system_mainNF.html | 6014 ----------------- .../SDK/SDK_Export/hw/system_toc.html | 73 - .../__xps/MCB_DDR3/tcl.log | 563 -- .../implementation/system_summary.html | 565 -- 6 files changed, 13231 deletions(-) delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log delete mode 100644 Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html deleted file mode 100644 index 1dda8a75f..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html +++ /dev/null @@ -1,12 +0,0 @@ - - - - -XPS Project Report - -XPS Project Report - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html deleted file mode 100644 index 8d96d046d..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html +++ /dev/null @@ -1,6004 +0,0 @@ - - - - -XPS Project Report - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Printable Version
-
Overview
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI Ethernet
1  AXI DMA Engine
1  AXI Interrupt Controller
1  AXI Timer/Counter
- - - - - - - - - - - - - - -
Specifics
GeneratedSat Aug 27 15:05:44 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
-
-
- - -
Block DiagramTOP
-
BlockDiagram -
- - - -
External PortsTOP
-
- - - - - - -
- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
-SHARED -RESETI1RESET RESET 
-ETHERNET -ETHERNET_MII_TX_CLKI1ETHERNET_MII_TX_CLK
-ETHERNET -ETHERNET_RXDI0:7ETHERNET_RXD
-ETHERNET -ETHERNET_RX_CLKI1ETHERNET_RX_CLK
-ETHERNET -ETHERNET_RX_DVI1ETHERNET_RX_DV
-ETHERNET -ETHERNET_RX_ERI1ETHERNET_RX_ER
-ETHERNET -ETHERNET_MDIOIO1ETHERNET_MDIO
-ETHERNET -ETHERNET_MDCO1ETHERNET_MDC
-ETHERNET -ETHERNET_PHY_RST_NO1ETHERNET_PHY_RST_N
-ETHERNET -ETHERNET_TXDO0:7ETHERNET_TXD
-ETHERNET -ETHERNET_TX_CLKO1ETHERNET_TX_CLK
-ETHERNET -ETHERNET_TX_ENO1ETHERNET_TX_EN
-ETHERNET -ETHERNET_TX_ERO1ETHERNET_TX_ER
-LEDs_4Bits -LEDs_4Bits_TRI_OO0:3LEDs_4Bits_TRI_O
-MCB_DDR3 -mcbx_dram_dqIO0:15mcbx_dram_dq
-MCB_DDR3 -mcbx_dram_dqsIO1mcbx_dram_dqs
-MCB_DDR3 -mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
-MCB_DDR3 -mcbx_dram_udqsIO1mcbx_dram_udqs
-MCB_DDR3 -mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
-MCB_DDR3 -rzqIO1rzq
-MCB_DDR3 -zioIO1zio
-MCB_DDR3 -mcbx_dram_addrO0:12mcbx_dram_addr
-MCB_DDR3 -mcbx_dram_baO0:2mcbx_dram_ba
-MCB_DDR3 -mcbx_dram_cas_nO1mcbx_dram_cas_n
-MCB_DDR3 -mcbx_dram_ckeO1mcbx_dram_cke
-MCB_DDR3 -mcbx_dram_clkO1mcbx_dram_clk
-MCB_DDR3 -mcbx_dram_clk_nO1mcbx_dram_clk_n
-MCB_DDR3 -mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
-MCB_DDR3 -mcbx_dram_ldmO1mcbx_dram_ldm
-MCB_DDR3 -mcbx_dram_odtO1mcbx_dram_odt
-MCB_DDR3 -mcbx_dram_ras_nO1mcbx_dram_ras_n
-MCB_DDR3 -mcbx_dram_udmO1mcbx_dram_udm
-MCB_DDR3 -mcbx_dram_we_nO1mcbx_dram_we_n
-Push_Buttons_4Bits -Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -RS232_Uart_1_sinI1RS232_Uart_1_sin
-RS232_Uart_1 -RS232_Uart_1_soutO1RS232_Uart_1_sout
-clock_generator_0 -CLK_NI1CLK CLK 
-clock_generator_0 -CLK_PI1CLK CLK 
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ProcessorsTOP
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-microblaze_0 -   MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
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microblaze_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_08 Peripherals.
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
M_AXI_DCMASTERAXIaxi4_02 Peripherals.
M_AXI_ICMASTERAXIaxi4_02 Peripherals.
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
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-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV0
C_USE_HW_MUL1
C_USE_FPU0
C_UNALIGNED_EXCEPTIONS0
C_ILL_OPCODE_EXCEPTION0
C_M_AXI_I_BUS_EXCEPTION0
C_M_AXI_D_BUS_EXCEPTION0
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION0
C_FPU_EXCEPTION0
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL0
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE1
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE16384
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE1
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE16384
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-

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DebuggersTOP
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- - -
- - - - - - - - - -
-debug_module -   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
CoreVersionDocumentation
mdm2.00.bIP
-

-
debug_module IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x7480FFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
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NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
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Interrupt ControllersTOP
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-microblaze_0_intc -   AXI Interrupt Controller
intc core attached to the AXI

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- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
-

-
microblaze_0_intc IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-Interrupt Priorities
PrioritySIGMODULE
0ETHERNET_INTERRUPTETHERNET
1ETHERNET_dma_mm2s_introutETHERNET_dma
2ETHERNET_dma_s2mm_introutETHERNET_dma
3Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
4RS232_Uart_1_InterruptRS232_Uart_1
5axi_timer_0_Interruptaxi_timer_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
BussesTOP
-
- - - - - - - - -
- - - - - - - - - -
-axi4_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DC
microblaze_0MASTERM_AXI_IC
ETHERNET_dmaMASTERM_AXI_SG
ETHERNET_dmaMASTERM_AXI_MM2S
ETHERNET_dmaMASTERM_AXI_S2MM
MCB_DDR3SLAVES0_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi4lite_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4lite_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
ETHERNETSLAVES_AXI
ETHERNET_dmaSLAVES_AXI_LITE
microblaze_0_intcSLAVES_AXI
axi_timer_0SLAVES_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_dlmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_dlmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_ilmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_ilmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
MemorysTOP
-
- - -
- - - - - - - - - -
-microblaze_0_bram_block -   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
-

-
microblaze_0_bram_block IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
-

-
- - - - - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Memory ControllersTOP
-
- - - - - - -
- - - - - - - - - -
-MCB_DDR3 -   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
-

-
MCB_DDR3 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_02 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0x80000000
C_S0_AXI_HIGHADDR0x807FFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY0
C_S0_AXI_ENABLE_AP0
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSmicroblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_d_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_d_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_i_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_i_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
PeripheralsTOP
-
- - - - - - - - - - - - -
- - - - - - - - - -
-ETHERNET -   AXI Ethernet
AXI Ethernet MAC

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_ethernet2.01.aIP
-

-
ETHERNET IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MDIOIO1ETHERNET_MDIO
1MDCO1ETHERNET_MDC
2GMII_TX_ERO1ETHERNET_TX_ER
3GMII_TXDO1ETHERNET_TXD
4GMII_TX_ENO1ETHERNET_TX_EN
5MII_TX_CLKI1ETHERNET_MII_TX_CLK
6GMII_TX_CLKO1ETHERNET_TX_CLK
7GMII_RXDI1ETHERNET_RXD
8GMII_RX_ERI1ETHERNET_RX_ER
9GMII_RX_CLKI1ETHERNET_RX_CLK
10GMII_RX_DVI1ETHERNET_RX_DV
11PHY_RST_NO1ETHERNET_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13GTX_CLKI1clk_125_0000MHz
14REF_CLKI1clk_200_0000MHzPLL0
15AXI_STR_TXD_ACLKI1clk_100_0000MHzPLL0
16AXI_STR_TXC_ACLKI1clk_100_0000MHzPLL0
17AXI_STR_RXD_ACLKI1clk_100_0000MHzPLL0
18AXI_STR_RXS_ACLKI1clk_100_0000MHzPLL0
19AXI_STR_TXD_ARESETNI1AXI_STR_TXD_ARESETN
20AXI_STR_TXC_ARESETNI1AXI_STR_TXC_ARESETN
21AXI_STR_RXD_ARESETNI1AXI_STR_RXD_ARESETN
22AXI_STR_RXS_ARESETNI1AXI_STR_RXS_ARESETN
23INTERRUPTO1ETHERNET_INTERRUPT
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
AXI_STR_RXSINITIATORAXISETHERNET_dma_rxsETHERNET_dma
AXI_STR_RXDINITIATORAXISETHERNET_dma_rxdETHERNET_dma
S_AXISLAVEAXIaxi4lite_08 Peripherals.
AXI_STR_TXDTARGETAXISETHERNET_dma_txdETHERNET_dma
AXI_STR_TXCTARGETAXISETHERNET_dma_txcETHERNET_dma
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH32
C_AXI_STR_TXD_TDATA_WIDTH32
C_AXI_STR_RXS_TDATA_WIDTH32
C_AXI_STR_RXD_TDATA_WIDTH32
C_AXI_STR_TXC_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_RX
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x41240000
C_HIGHADDR0x4127FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH4
C_TRANSA
C_PHYADDR0B00001
C_INCLUDE_IO1
C_TYPE1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_PHY_TYPE1
C_HALFDUP0
C_TXMEM4096
C_RXMEM4096
C_TXCSUM0
C_RXCSUM0
C_TXVLAN_TRAN0
C_RXVLAN_TRAN0
C_TXVLAN_TAG0
C_RXVLAN_TAG0
C_TXVLAN_STRP0
C_RXVLAN_STRP0
C_MCAST_EXTEND0
C_STATS0
C_AVB0
C_SIMULATION0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-ETHERNET_dma -   AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_dma3.00.aIP
-

-
ETHERNET_dma IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0s_axi_lite_aclkI1clk_100_0000MHzPLL0
1m_axi_sg_aclkI1clk_100_0000MHzPLL0
2m_axi_mm2s_aclkI1clk_100_0000MHzPLL0
3m_axi_s2mm_aclkI1clk_100_0000MHzPLL0
4mm2s_prmry_reset_out_nO1AXI_STR_TXD_ARESETN
5mm2s_cntrl_reset_out_nO1AXI_STR_TXC_ARESETN
6s2mm_prmry_reset_out_nO1AXI_STR_RXD_ARESETN
7s2mm_sts_reset_out_nO1AXI_STR_RXS_ARESETN
8mm2s_introutO1ETHERNET_dma_mm2s_introut
9s2mm_introutO1ETHERNET_dma_s2mm_introut
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXIS_MM2SINITIATORAXISETHERNET_dma_txdETHERNET
M_AXIS_CNTRLINITIATORAXISETHERNET_dma_txcETHERNET
M_AXI_SGMASTERAXIaxi4_02 Peripherals.
M_AXI_MM2SMASTERAXIaxi4_02 Peripherals.
M_AXI_S2MMMASTERAXIaxi4_02 Peripherals.
S_AXI_LITESLAVEAXIaxi4lite_08 Peripherals.
S_AXIS_STSTARGETAXISETHERNET_dma_rxsETHERNET
S_AXIS_S2MMTARGETAXISETHERNET_dma_rxdETHERNET
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_LITE_ADDR_WIDTH32
C_S_AXI_LITE_DATA_WIDTH32
C_DLYTMR_RESOLUTION1250
C_PRMRY_IS_ACLK_ASYNC0
C_SG_INCLUDE_DESC_QUEUE1
C_SG_INCLUDE_STSCNTRL_STRM1
C_SG_USE_STSAPP_LENGTH1
C_SG_LENGTH_WIDTH16
C_M_AXI_SG_ADDR_WIDTH32
C_M_AXI_SG_DATA_WIDTH32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH32
C_S_AXIS_S2MM_STS_TDATA_WIDTH32
C_INCLUDE_MM2S1
C_INCLUDE_MM2S_DRE1
C_MM2S_BURST_SIZE16
C_M_AXI_MM2S_ADDR_WIDTH32
C_M_AXI_MM2S_DATA_WIDTH32
C_M_AXIS_MM2S_TDATA_WIDTH32
C_INCLUDE_S2MM1
C_INCLUDE_S2MM_DRE1
C_S2MM_BURST_SIZE16
C_M_AXI_S2MM_ADDR_WIDTH32
C_M_AXI_S2MM_DATA_WIDTH32
C_S_AXIS_S2MM_TDATA_WIDTH32
C_FAMILYvirtex6
C_BASEADDR0x41E00000
C_HIGHADDR0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ100000000
C_M_AXI_SG_ACLK_FREQ_HZ100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ100000000
C_S_AXI_LITE_PROTOCOLAXI4LITE
C_S_AXI_LITE_SUPPORTS_READ1
C_S_AXI_LITE_SUPPORTS_WRITE1
C_M_AXI_SG_PROTOCOLAXI4
C_M_AXI_SG_SUPPORTS_THREADS0
C_M_AXI_SG_THREAD_ID_WIDTH1
C_M_AXI_SG_SUPPORTS_NARROW_BURST0
C_M_AXI_SG_SUPPORTS_READ1
C_M_AXI_SG_SUPPORTS_WRITE1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_M_AXI_MM2S_PROTOCOLAXI4
C_M_AXI_MM2S_SUPPORTS_THREADS0
C_M_AXI_MM2S_THREAD_ID_WIDTH1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST0
C_M_AXI_MM2S_SUPPORTS_READ1
C_M_AXI_MM2S_SUPPORTS_WRITE0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH512
C_M_AXI_S2MM_PROTOCOLAXI4
C_M_AXI_S2MM_SUPPORTS_THREADS0
C_M_AXI_S2MM_THREAD_ID_WIDTH1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST0
C_M_AXI_S2MM_SUPPORTS_WRITE1
C_M_AXI_S2MM_SUPPORTS_READ0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH512
C_M_AXIS_MM2S_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER1
C_INTERCONNECT_M_AXI_SG_W_REGISTER1
C_INTERCONNECT_M_AXI_SG_R_REGISTER1
C_INTERCONNECT_M_AXI_SG_B_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-LEDs_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
-

-
LEDs_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
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NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-Push_Buttons_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
-

-
Push_Buttons_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-RS232_Uart_1 -   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
-

-
RS232_Uart_1 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
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NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi_timer_0 -   AXI Timer/Counter
Timer counter with AXI interface

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
-

-
axi_timer_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
 
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NameValue
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
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-

- - -
IPTOP
-
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- - - - - - - - - -
-clock_generator_0 -   Clock Generator
Clock generator for processor system.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
-

-
clock_generator_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT5O1clk_50_0000MHzPLL0
4CLKOUT3O1clk_125_0000MHz
5CLKOUT4O1clk_200_0000MHzPLL0
6CLKOUT0O1clk_600_0000MHzPLL0_nobuf
7CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
8LOCKEDO1proc_sys_reset_0_Dcm_locked
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ125000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPNONE
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ200000000
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPPLL0
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ50000000
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPPLL0
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-proc_sys_reset_0 -   Processor System Reset Module
Reset management module

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
-

-
proc_sys_reset_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Timing InformationTOP
-

- - - -
Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -
-
- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html deleted file mode 100644 index a178f79c0..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html +++ /dev/null @@ -1,6014 +0,0 @@ - - - - -XPS Project Report - - - - - - - -
TABLE OF CONTENTS
-
Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
Memory
   microblaze_0_bram_block
Memory Controllers
   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
Peripherals
   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
IP
   clock_generator_0
   proc_sys_reset_0
Timing Information -
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - -
OverviewTOC
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Resources Used
1  MicroBlaze
2  AXI Interconnect
2  Local Memory Bus (LMB) 1.0
1  Block RAM (BRAM) Block
2  LMB BRAM Controller
1  AXI S6 Memory Controller(DDR/DDR2/DDR3)
1  Processor System Reset Module
1  Clock Generator
1  MicroBlaze Debug Module (MDM)
1  AXI UART (Lite)
2  AXI General Purpose IO
1  AXI Ethernet
1  AXI DMA Engine
1  AXI Interrupt Controller
1  AXI Timer/Counter
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Specifics
GeneratedSat Aug 27 15:05:44 2011
EDK Version13.1
Device Familyspartan6
Devicexc6slx45tfgg484-3
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Block DiagramTOC
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BlockDiagram -
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External PortsTOC
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- These are the external ports defined in the MHS file. -
-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
-SHARED -RESETI1RESET RESET 
-ETHERNET -ETHERNET_MII_TX_CLKI1ETHERNET_MII_TX_CLK
-ETHERNET -ETHERNET_RXDI0:7ETHERNET_RXD
-ETHERNET -ETHERNET_RX_CLKI1ETHERNET_RX_CLK
-ETHERNET -ETHERNET_RX_DVI1ETHERNET_RX_DV
-ETHERNET -ETHERNET_RX_ERI1ETHERNET_RX_ER
-ETHERNET -ETHERNET_MDIOIO1ETHERNET_MDIO
-ETHERNET -ETHERNET_MDCO1ETHERNET_MDC
-ETHERNET -ETHERNET_PHY_RST_NO1ETHERNET_PHY_RST_N
-ETHERNET -ETHERNET_TXDO0:7ETHERNET_TXD
-ETHERNET -ETHERNET_TX_CLKO1ETHERNET_TX_CLK
-ETHERNET -ETHERNET_TX_ENO1ETHERNET_TX_EN
-ETHERNET -ETHERNET_TX_ERO1ETHERNET_TX_ER
-LEDs_4Bits -LEDs_4Bits_TRI_OO0:3LEDs_4Bits_TRI_O
-MCB_DDR3 -mcbx_dram_dqIO0:15mcbx_dram_dq
-MCB_DDR3 -mcbx_dram_dqsIO1mcbx_dram_dqs
-MCB_DDR3 -mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
-MCB_DDR3 -mcbx_dram_udqsIO1mcbx_dram_udqs
-MCB_DDR3 -mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
-MCB_DDR3 -rzqIO1rzq
-MCB_DDR3 -zioIO1zio
-MCB_DDR3 -mcbx_dram_addrO0:12mcbx_dram_addr
-MCB_DDR3 -mcbx_dram_baO0:2mcbx_dram_ba
-MCB_DDR3 -mcbx_dram_cas_nO1mcbx_dram_cas_n
-MCB_DDR3 -mcbx_dram_ckeO1mcbx_dram_cke
-MCB_DDR3 -mcbx_dram_clkO1mcbx_dram_clk
-MCB_DDR3 -mcbx_dram_clk_nO1mcbx_dram_clk_n
-MCB_DDR3 -mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
-MCB_DDR3 -mcbx_dram_ldmO1mcbx_dram_ldm
-MCB_DDR3 -mcbx_dram_odtO1mcbx_dram_odt
-MCB_DDR3 -mcbx_dram_ras_nO1mcbx_dram_ras_n
-MCB_DDR3 -mcbx_dram_udmO1mcbx_dram_udm
-MCB_DDR3 -mcbx_dram_we_nO1mcbx_dram_we_n
-Push_Buttons_4Bits -Push_Buttons_4Bits_TRI_II0:3Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -RS232_Uart_1_sinI1RS232_Uart_1_sin
-RS232_Uart_1 -RS232_Uart_1_soutO1RS232_Uart_1_sout
-clock_generator_0 -CLK_NI1CLK CLK 
-clock_generator_0 -CLK_PI1CLK CLK 
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ProcessorsTOC
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-microblaze_0 -   MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
CoreVersionDocumentation
microblaze8.10.aIP
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microblaze_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MB_RESETI1proc_sys_reset_0_MB_Reset
1CLKI1clk_100_0000MHzPLL0
2INTERRUPTI1microblaze_0_interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXI_DPMASTERAXIaxi4lite_08 Peripherals.
DLMBMASTERLMBmicroblaze_0_dlmbmicroblaze_0_d_bram_ctrl
ILMBMASTERLMBmicroblaze_0_ilmbmicroblaze_0_i_bram_ctrl
M_AXI_DCMASTERAXIaxi4_02 Peripherals.
M_AXI_ICMASTERAXIaxi4_02 Peripherals.
DEBUGTARGETXIL_MBDEBUG3microblaze_0_debugdebug_module
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_SCO0
C_FREQ0
C_DATA_SIZE32
C_DYNAMIC_BUS_SIZING1
C_FAMILYvirtex5
C_INSTANCEmicroblaze
C_FAULT_TOLERANT0
C_ECC_USE_CE_EXCEPTION0
C_ENDIANNESS0
C_AREA_OPTIMIZED0
C_OPTIMIZATION0
C_INTERCONNECT2
C_STREAM_INTERCONNECT0
C_DPLB_DWIDTH32
C_DPLB_NATIVE_DWIDTH32
C_DPLB_BURST_EN0
C_DPLB_P2P0
C_IPLB_DWIDTH32
C_IPLB_NATIVE_DWIDTH32
C_IPLB_BURST_EN0
C_IPLB_P2P0
C_M_AXI_DP_SUPPORTS_THREADS0
C_M_AXI_DP_THREAD_ID_WIDTH1
C_M_AXI_DP_SUPPORTS_READ1
C_M_AXI_DP_SUPPORTS_WRITE1
C_M_AXI_DP_SUPPORTS_NARROW_BURST0
C_M_AXI_DP_DATA_WIDTH32
C_M_AXI_DP_ADDR_WIDTH32
C_M_AXI_DP_PROTOCOLAXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING1
C_M_AXI_IP_SUPPORTS_THREADS0
C_M_AXI_IP_THREAD_ID_WIDTH1
C_M_AXI_IP_SUPPORTS_READ1
C_M_AXI_IP_SUPPORTS_WRITE0
C_M_AXI_IP_SUPPORTS_NARROW_BURST0
C_M_AXI_IP_DATA_WIDTH32
C_M_AXI_IP_ADDR_WIDTH32
C_M_AXI_IP_PROTOCOLAXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING1
C_D_AXI0
C_D_PLB0
C_D_LMB1
C_I_AXI0
C_I_PLB0
C_I_LMB1
C_USE_MSR_INSTR1
C_USE_PCMP_INSTR1
C_USE_BARREL1
C_USE_DIV0
C_USE_HW_MUL1
C_USE_FPU0
C_UNALIGNED_EXCEPTIONS0
C_ILL_OPCODE_EXCEPTION0
C_M_AXI_I_BUS_EXCEPTION0
C_M_AXI_D_BUS_EXCEPTION0
C_IPLB_BUS_EXCEPTION0
C_DPLB_BUS_EXCEPTION0
C_DIV_ZERO_EXCEPTION0
C_FPU_EXCEPTION0
C_FSL_EXCEPTION0
C_USE_STACK_PROTECTION0
C_PVR0
C_PVR_USER10x00
C_PVR_USER20x00000000
C_DEBUG_ENABLED1
C_NUMBER_OF_PC_BRK7
C_NUMBER_OF_RD_ADDR_BRK2
C_NUMBER_OF_WR_ADDR_BRK2
C_INTERRUPT_IS_EDGE0
C_EDGE_IS_POSITIVE1
C_RESET_MSR0x00000000
C_OPCODE_0x0_ILLEGAL0
C_FSL_LINKS0
C_FSL_DATA_SIZE32
C_USE_EXTENDED_FSL_INSTR0
C_M0_AXIS_PROTOCOLGENERIC
C_S0_AXIS_PROTOCOLGENERIC
C_M1_AXIS_PROTOCOLGENERIC
C_S1_AXIS_PROTOCOLGENERIC
C_M2_AXIS_PROTOCOLGENERIC
C_S2_AXIS_PROTOCOLGENERIC
C_M3_AXIS_PROTOCOLGENERIC
C_S3_AXIS_PROTOCOLGENERIC
C_M4_AXIS_PROTOCOLGENERIC
C_S4_AXIS_PROTOCOLGENERIC
C_M5_AXIS_PROTOCOLGENERIC
C_S5_AXIS_PROTOCOLGENERIC
C_M6_AXIS_PROTOCOLGENERIC
C_S6_AXIS_PROTOCOLGENERIC
C_M7_AXIS_PROTOCOLGENERIC
C_S7_AXIS_PROTOCOLGENERIC
C_M8_AXIS_PROTOCOLGENERIC
C_S8_AXIS_PROTOCOLGENERIC
C_M9_AXIS_PROTOCOLGENERIC
C_S9_AXIS_PROTOCOLGENERIC
C_M10_AXIS_PROTOCOLGENERIC
C_S10_AXIS_PROTOCOLGENERIC
C_M11_AXIS_PROTOCOLGENERIC
C_S11_AXIS_PROTOCOLGENERIC
C_M12_AXIS_PROTOCOLGENERIC
C_S12_AXIS_PROTOCOLGENERIC
C_M13_AXIS_PROTOCOLGENERIC
C_S13_AXIS_PROTOCOLGENERIC
C_M14_AXIS_PROTOCOLGENERIC
C_S14_AXIS_PROTOCOLGENERIC
C_M15_AXIS_PROTOCOLGENERIC
C_S15_AXIS_PROTOCOLGENERIC
C_M0_AXIS_DATA_WIDTH32
C_S0_AXIS_DATA_WIDTH32
C_M1_AXIS_DATA_WIDTH32
C_S1_AXIS_DATA_WIDTH32
C_M2_AXIS_DATA_WIDTH32
C_S2_AXIS_DATA_WIDTH32
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_M3_AXIS_DATA_WIDTH32
C_S3_AXIS_DATA_WIDTH32
C_M4_AXIS_DATA_WIDTH32
C_S4_AXIS_DATA_WIDTH32
C_M5_AXIS_DATA_WIDTH32
C_S5_AXIS_DATA_WIDTH32
C_M6_AXIS_DATA_WIDTH32
C_S6_AXIS_DATA_WIDTH32
C_M7_AXIS_DATA_WIDTH32
C_S7_AXIS_DATA_WIDTH32
C_M8_AXIS_DATA_WIDTH32
C_S8_AXIS_DATA_WIDTH32
C_M9_AXIS_DATA_WIDTH32
C_S9_AXIS_DATA_WIDTH32
C_M10_AXIS_DATA_WIDTH32
C_S10_AXIS_DATA_WIDTH32
C_M11_AXIS_DATA_WIDTH32
C_S11_AXIS_DATA_WIDTH32
C_M12_AXIS_DATA_WIDTH32
C_S12_AXIS_DATA_WIDTH32
C_M13_AXIS_DATA_WIDTH32
C_S13_AXIS_DATA_WIDTH32
C_M14_AXIS_DATA_WIDTH32
C_S14_AXIS_DATA_WIDTH32
C_M15_AXIS_DATA_WIDTH32
C_S15_AXIS_DATA_WIDTH32
C_ICACHE_BASEADDR0xC0000000
C_ICACHE_HIGHADDR0xC7FFFFFF
C_USE_ICACHE1
C_ALLOW_ICACHE_WR1
C_ADDR_TAG_BITS17
C_CACHE_BYTE_SIZE16384
C_ICACHE_USE_FSL1
C_ICACHE_LINE_LEN4
C_ICACHE_ALWAYS_USED1
C_ICACHE_INTERFACE0
C_ICACHE_VICTIMS0
C_ICACHE_STREAMS0
C_ICACHE_FORCE_TAG_LUTRAM0
C_ICACHE_DATA_WIDTH0
C_M_AXI_IC_SUPPORTS_THREADS0
C_M_AXI_IC_THREAD_ID_WIDTH1
C_M_AXI_IC_SUPPORTS_READ1
C_M_AXI_IC_SUPPORTS_WRITE0
C_M_AXI_IC_SUPPORTS_NARROW_BURST0
C_M_AXI_IC_DATA_WIDTH32
C_M_AXI_IC_ADDR_WIDTH32
C_M_AXI_IC_PROTOCOLAXI4
C_M_AXI_IC_USER_VALUE0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS1
C_M_AXI_IC_AWUSER_WIDTH5
C_M_AXI_IC_ARUSER_WIDTH5
C_M_AXI_IC_WUSER_WIDTH1
C_M_AXI_IC_RUSER_WIDTH1
C_M_AXI_IC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING2
C_DCACHE_BASEADDR0xC0000000
C_DCACHE_HIGHADDR0xC7FFFFFF
C_USE_DCACHE1
C_ALLOW_DCACHE_WR1
C_DCACHE_ADDR_TAG17
C_DCACHE_BYTE_SIZE16384
C_DCACHE_USE_FSL1
C_DCACHE_LINE_LEN4
C_DCACHE_ALWAYS_USED1
C_DCACHE_INTERFACE0
C_DCACHE_USE_WRITEBACK0
C_DCACHE_VICTIMS0
C_DCACHE_FORCE_TAG_LUTRAM0
C_DCACHE_DATA_WIDTH0
C_M_AXI_DC_SUPPORTS_THREADS0
C_M_AXI_DC_THREAD_ID_WIDTH1
C_M_AXI_DC_SUPPORTS_READ1
C_M_AXI_DC_SUPPORTS_WRITE1
C_M_AXI_DC_SUPPORTS_NARROW_BURST0
C_M_AXI_DC_DATA_WIDTH32
C_M_AXI_DC_ADDR_WIDTH32
C_M_AXI_DC_PROTOCOLAXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS0
C_M_AXI_DC_USER_VALUE0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS1
C_M_AXI_DC_AWUSER_WIDTH5
C_M_AXI_DC_ARUSER_WIDTH5
C_M_AXI_DC_WUSER_WIDTH1
C_M_AXI_DC_RUSER_WIDTH1
C_M_AXI_DC_BUSER_WIDTH1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING32
C_USE_MMU0
C_MMU_DTLB_SIZE4
C_MMU_ITLB_SIZE2
C_MMU_TLB_ACCESS3
C_MMU_ZONES16
C_MMU_PRIVILEGED_INSTR0
C_USE_INTERRUPT0
C_USE_EXT_BRK0
C_USE_EXT_NM_BRK0
C_USE_BRANCH_TARGET_CACHE0
C_BRANCH_TARGET_CACHE_SIZE0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER1
C_INTERCONNECT_M_AXI_DC_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER1
C_INTERCONNECT_M_AXI_DP_W_REGISTER1
C_INTERCONNECT_M_AXI_DP_R_REGISTER1
C_INTERCONNECT_M_AXI_DP_B_REGISTER1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER1
C_INTERCONNECT_M_AXI_DC_R_REGISTER1
C_INTERCONNECT_M_AXI_DC_B_REGISTER1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER1
C_INTERCONNECT_M_AXI_IC_W_REGISTER1
C_INTERCONNECT_M_AXI_IC_R_REGISTER1
C_INTERCONNECT_M_AXI_IC_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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DebuggersTOC
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-debug_module -   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
CoreVersionDocumentation
mdm2.00.bIP
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debug_module IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1Debug_SYS_RstO1proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
MBDEBUG_0INITIATORXIL_MBDEBUG3microblaze_0_debugmicroblaze_0
S_AXISLAVEAXIaxi4lite_08 Peripherals.
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_FAMILYvirtex6
C_JTAG_CHAIN2
C_INTERCONNECT2
C_BASEADDR0x74800000
C_HIGHADDR0x7480FFFF
C_SPLB_AWIDTH32
C_SPLB_DWIDTH32
C_SPLB_P2P0
C_SPLB_MID_WIDTH3
C_SPLB_NUM_MASTERS8
C_SPLB_NATIVE_DWIDTH32
 
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NameValue
C_SPLB_SUPPORT_BURSTS0
C_MB_DBG_PORTS1
C_USE_UART1
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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Interrupt ControllersTOC
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-microblaze_0_intc -   AXI Interrupt Controller
intc core attached to the AXI

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IP Specs
CoreVersionDocumentation
axi_intc1.01.aIP
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microblaze_0_intc IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0IRQO1microblaze_0_interrupt
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2INTRI1ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-Interrupt Priorities
PrioritySIGMODULE
0ETHERNET_INTERRUPTETHERNET
1ETHERNET_dma_mm2s_introutETHERNET_dma
2ETHERNET_dma_s2mm_introutETHERNET_dma
3Push_Buttons_4Bits_IP2INTC_IrptPush_Buttons_4Bits
4RS232_Uart_1_InterruptRS232_Uart_1
5axi_timer_0_Interruptaxi_timer_0
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_FAMILYvirtex6
C_BASEADDR0x41200000
C_HIGHADDR0x4120FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_NUM_INTR_INPUTS2
C_KIND_OF_INTR0xFFFFFFFF
C_KIND_OF_EDGE0xFFFFFFFF
C_KIND_OF_LVL0xFFFFFFFF
C_HAS_IPR1
C_HAS_SIE1
 
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NameValue
C_HAS_CIE1
C_HAS_IVR1
C_IRQ_IS_LEVEL1
C_IRQ_ACTIVE1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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BussesTOC
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- - - - - - - - -
- - - - - - - - - -
-axi4_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0interconnect_aclkI1clk_100_0000MHzPLL0
1INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DC
microblaze_0MASTERM_AXI_IC
ETHERNET_dmaMASTERM_AXI_SG
ETHERNET_dmaMASTERM_AXI_MM2S
ETHERNET_dmaMASTERM_AXI_S2MM
MCB_DDR3SLAVES0_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE1
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi4lite_0 -   AXI Interconnect
AXI4 Memory-Mapped Interconnect

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_interconnect1.02.aIP
-

-
axi4lite_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0INTERCONNECT_ARESETNI1proc_sys_reset_0_Interconnect_aresetn
1INTERCONNECT_ACLKI1clk_50_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERM_AXI_DP
debug_moduleSLAVES_AXI
RS232_Uart_1SLAVES_AXI
LEDs_4BitsSLAVES_AXI
Push_Buttons_4BitsSLAVES_AXI
ETHERNETSLAVES_AXI
ETHERNET_dmaSLAVES_AXI_LITE
microblaze_0_intcSLAVES_AXI
axi_timer_0SLAVES_AXI
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYrtl
C_BASEFAMILYrtl
C_NUM_SLAVE_SLOTS1
C_NUM_MASTER_SLOTS1
C_AXI_ID_WIDTH1
C_AXI_ADDR_WIDTH32
C_AXI_DATA_MAX_WIDTH32
C_S_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH32
C_S_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT0b0000000000000000
C_S_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC0b0000000000000000
C_M_AXI_ACLK_RATIO0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC0b0000000000000000
C_INTERCONNECT_ACLK_RATIO1
C_S_AXI_SUPPORTS_WRITE0b1111111111111111
C_S_AXI_SUPPORTS_READ0b1111111111111111
C_M_AXI_SUPPORTS_WRITE0b1111111111111111
C_M_AXI_SUPPORTS_READ0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS0
C_AXI_AWUSER_WIDTH1
C_AXI_ARUSER_WIDTH1
C_AXI_WUSER_WIDTH1
C_AXI_RUSER_WIDTH1
C_AXI_BUSER_WIDTH1
C_AXI_CONNECTIVITY0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_READ_ACCEPTANCE0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE0b1111111111111111
C_S_AXI_READ_FIFO_DELAY0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE0b1111111111111111
C_M_AXI_READ_FIFO_DELAY0b0000000000000000
C_S_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER0
C_INTERCONNECT_CONNECTIVITY_MODE0
C_USE_CTRL_PORT0
C_USE_INTERRUPT1
C_RANGE_CHECK2
C_S_AXI_CTRL_PROTOCOLAXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_BASEADDR0xFFFFFFFF
C_HIGHADDR0x00000000
C_DEBUG0
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_dlmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_dlmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERDLMB
microblaze_0_d_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_ilmb -   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_v102.00.aIP
-

-
microblaze_0_ilmb IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
1LMB_CLKI1clk_100_0000MHzPLL0
Bus Connections
INSTANCEINTERFACE TYPEINTERFACE NAME
microblaze_0MASTERILMB
microblaze_0_i_bram_ctrlSLAVESLMB
-

-
- - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_LMB_NUM_SLAVES4
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_EXT_RESET_HIGH1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
MemorysTOC
-
- - -
- - - - - - - - - -
-microblaze_0_bram_block -   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
bram_block1.00.aIP
-

-
microblaze_0_bram_block IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
PORTATARGETXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_i_bram_ctrl
PORTBTARGETXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_d_bram_ctrl
-

-
- - - - - - - - - - - - - - - - - - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_MEMSIZE2048
C_PORT_DWIDTH32
C_PORT_AWIDTH32
C_NUM_WE4
C_FAMILYvirtex2
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Memory ControllersTOC
-
- - - - - - -
- - - - - - - - - -
-MCB_DDR3 -   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_s6_ddrx1.02.aIP
-

-
MCB_DDR3 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0mcbx_dram_clkO1mcbx_dram_clk
1mcbx_dram_clk_nO1mcbx_dram_clk_n
2mcbx_dram_ckeO1mcbx_dram_cke
3mcbx_dram_odtO1mcbx_dram_odt
4mcbx_dram_ras_nO1mcbx_dram_ras_n
5mcbx_dram_cas_nO1mcbx_dram_cas_n
6mcbx_dram_we_nO1mcbx_dram_we_n
7mcbx_dram_udmO1mcbx_dram_udm
8mcbx_dram_ldmO1mcbx_dram_ldm
9mcbx_dram_baO1mcbx_dram_ba
10mcbx_dram_addrO1mcbx_dram_addr
11mcbx_dram_ddr3_rstO1mcbx_dram_ddr3_rst
12mcbx_dram_dqIO1mcbx_dram_dq
13mcbx_dram_dqsIO1mcbx_dram_dqs
14mcbx_dram_dqs_nIO1mcbx_dram_dqs_n
15mcbx_dram_udqsIO1mcbx_dram_udqs
16mcbx_dram_udqs_nIO1mcbx_dram_udqs_n
17rzqIO1rzq
18zioIO1zio
19s0_axi_aclkI1clk_100_0000MHzPLL0
20ui_clkI1clk_100_0000MHzPLL0
21sysclk_2xI1clk_600_0000MHzPLL0_nobuf
22sysclk_2x_180I1clk_600_0000MHz180PLL0_nobuf
23SYS_RSTI1proc_sys_reset_0_BUS_STRUCT_RESET
24PLL_LOCKI1proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S0_AXISLAVEAXIaxi4_02 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_MCB_LOCMEMC3
C_MCB_RZQ_LOCK7
C_MCB_ZIO_LOCR7
C_MCB_PERFORMANCESTANDARD
C_BYPASS_CORE_UCF0
C_S0_AXI_BASEADDR0x80000000
C_S0_AXI_HIGHADDR0x807FFFFF
C_S1_AXI_BASEADDR0xFFFFFFFF
C_S1_AXI_HIGHADDR0x00000000
C_S2_AXI_BASEADDR0xFFFFFFFF
C_S2_AXI_HIGHADDR0x00000000
C_S3_AXI_BASEADDR0xFFFFFFFF
C_S3_AXI_HIGHADDR0x00000000
C_S4_AXI_BASEADDR0xFFFFFFFF
C_S4_AXI_HIGHADDR0x00000000
C_S5_AXI_BASEADDR0xFFFFFFFF
C_S5_AXI_HIGHADDR0x00000000
C_MEM_TYPEDDR3
C_MEM_PARTNOMT41J64M16XX-187E
C_MEM_BASEPARTNONOT_SET
C_NUM_DQ_PINS16
C_MEM_ADDR_WIDTH13
C_MEM_BANKADDR_WIDTH3
C_MEM_NUM_COL_BITS10
C_MEM_TRAS-1
C_MEM_TRCD-1
C_MEM_TREFI-1
C_MEM_TRFC-1
C_MEM_TRP-1
C_MEM_TWR-1
C_MEM_TRTP-1
C_MEM_TWTR-1
C_PORT_CONFIGB32_B32_B32_B32
C_SKIP_IN_TERM_CAL0
C_SKIP_IN_TERM_CAL_VALUENONE
C_MEMCLK_PERIOD0
C_MEM_ADDR_ORDERROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT512
C_MEM_CAS_LATENCY6
C_SIMULATIONFALSE
C_MEM_DDR1_2_ODSFULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODSCLASS_II
C_MEM_DDR2_RTT150OHMS
C_MEM_DDR2_DIFF_DQS_ENYES
C_MEM_DDR2_3_PA_SRFULL
C_MEM_DDR2_3_HIGH_TEMP_SRNORMAL
C_MEM_DDR3_CAS_WR_LATENCY5
C_MEM_DDR3_CAS_LATENCY6
C_MEM_DDR3_ODSDIV6
C_MEM_DDR3_RTTDIV4
C_MEM_DDR3_AUTO_SRENABLED
C_MEM_MOBILE_PA_SRFULL
C_MEM_MDDR_ODSFULL
C_ARB_ALGORITHM0
C_ARB_NUM_TIME_SLOTS12
C_ARB_TIME_SLOT_00b000000000001010011
C_ARB_TIME_SLOT_10b000000001010011000
C_ARB_TIME_SLOT_20b000000010011000001
C_ARB_TIME_SLOT_30b000000011000001010
C_ARB_TIME_SLOT_40b000000000001010011
C_ARB_TIME_SLOT_50b000000001010011000
C_ARB_TIME_SLOT_60b000000010011000001
C_ARB_TIME_SLOT_70b000000011000001010
C_ARB_TIME_SLOT_80b000000000001010011
C_ARB_TIME_SLOT_90b000000001010011000
C_ARB_TIME_SLOT_100b000000010011000001
C_ARB_TIME_SLOT_110b000000011000001010
C_S0_AXI_ENABLE1
C_S0_AXI_PROTOCOLAXI4
C_S0_AXI_ID_WIDTH4
C_S0_AXI_ADDR_WIDTH32
C_S0_AXI_DATA_WIDTH32
C_S0_AXI_SUPPORTS_READ1
C_S0_AXI_SUPPORTS_WRITE1
C_S0_AXI_SUPPORTS_NARROW_BURST1
C_S0_AXI_REG_EN00x00000
C_S0_AXI_REG_EN10x01000
C_S0_AXI_STRICT_COHERENCY0
C_S0_AXI_ENABLE_AP0
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE4
C_S1_AXI_ENABLE0
C_S1_AXI_PROTOCOLAXI4
C_S1_AXI_ID_WIDTH4
C_S1_AXI_ADDR_WIDTH32
C_S1_AXI_DATA_WIDTH32
C_S1_AXI_SUPPORTS_READ1
C_S1_AXI_SUPPORTS_WRITE1
C_S1_AXI_SUPPORTS_NARROW_BURST1
C_S1_AXI_REG_EN00x00000
C_S1_AXI_REG_EN10x01000
C_S1_AXI_STRICT_COHERENCY1
C_S1_AXI_ENABLE_AP0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE4
C_S2_AXI_ENABLE0
C_S2_AXI_PROTOCOLAXI4
C_S2_AXI_ID_WIDTH4
C_S2_AXI_ADDR_WIDTH32
C_S2_AXI_DATA_WIDTH32
C_S2_AXI_SUPPORTS_READ1
C_S2_AXI_SUPPORTS_WRITE1
C_S2_AXI_SUPPORTS_NARROW_BURST1
C_S2_AXI_REG_EN00x00000
C_S2_AXI_REG_EN10x01000
C_S2_AXI_STRICT_COHERENCY1
C_S2_AXI_ENABLE_AP0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE4
C_S3_AXI_ENABLE0
C_S3_AXI_PROTOCOLAXI4
C_S3_AXI_ID_WIDTH4
C_S3_AXI_ADDR_WIDTH32
C_S3_AXI_DATA_WIDTH32
C_S3_AXI_SUPPORTS_READ1
C_S3_AXI_SUPPORTS_WRITE1
C_S3_AXI_SUPPORTS_NARROW_BURST1
C_S3_AXI_REG_EN00x00000
C_S3_AXI_REG_EN10x01000
C_S3_AXI_STRICT_COHERENCY1
C_S3_AXI_ENABLE_AP0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE4
C_S4_AXI_ENABLE0
C_S4_AXI_PROTOCOLAXI4
C_S4_AXI_ID_WIDTH4
C_S4_AXI_ADDR_WIDTH32
C_S4_AXI_DATA_WIDTH32
C_S4_AXI_SUPPORTS_READ1
C_S4_AXI_SUPPORTS_WRITE1
C_S4_AXI_SUPPORTS_NARROW_BURST1
C_S4_AXI_REG_EN00x00000
C_S4_AXI_REG_EN10x01000
C_S4_AXI_STRICT_COHERENCY1
C_S4_AXI_ENABLE_AP0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE4
C_S5_AXI_ENABLE0
C_S5_AXI_PROTOCOLAXI4
C_S5_AXI_ID_WIDTH4
C_S5_AXI_ADDR_WIDTH32
C_S5_AXI_DATA_WIDTH32
C_S5_AXI_SUPPORTS_READ1
C_S5_AXI_SUPPORTS_WRITE1
C_S5_AXI_SUPPORTS_NARROW_BURST1
C_S5_AXI_REG_EN00x00000
C_S5_AXI_REG_EN10x01000
C_S5_AXI_STRICT_COHERENCY1
C_S5_AXI_ENABLE_AP0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE4
C_MCB_USE_EXTERNAL_BUFPLL0
C_SYS_RST_PRESENT0
C_INTERCONNECT_S0_AXI_MASTERSmicroblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER1
C_INTERCONNECT_S0_AXI_AR_REGISTER1
C_INTERCONNECT_S0_AXI_W_REGISTER1
C_INTERCONNECT_S0_AXI_R_REGISTER1
C_INTERCONNECT_S0_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_d_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_d_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_d_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_dlmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-microblaze_0_i_bram_ctrl -   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
lmb_bram_if_cntlr3.00.aIP
-

-
microblaze_0_i_bram_ctrl IP Image - - - - - - - - - - - - - - - - - - - - - -
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
BRAM_PORTINITIATORXIL_BRAMmicroblaze_0_i_bram_ctrl_2_microblaze_0_bram_blockmicroblaze_0_bram_block
SLMBSLAVELMBmicroblaze_0_ilmbmicroblaze_0
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_BASEADDR0x00000000
C_HIGHADDR0x00001FFF
C_FAMILYvirtex5
C_MASK0x00800000
C_LMB_AWIDTH32
C_LMB_DWIDTH32
C_ECC0
C_INTERCONNECT0
C_FAULT_INJECT0
C_CE_FAILING_REGISTERS0
C_UE_FAILING_REGISTERS0
C_ECC_STATUS_REGISTERS0
C_ECC_ONOFF_REGISTER0
C_ECC_ONOFF_RESET_VALUE1
C_CE_COUNTER_WIDTH0
C_WRITE_ACCESS2
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_SPLB_CTRL_BASEADDR0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR0x00000000
C_SPLB_CTRL_AWIDTH32
C_SPLB_CTRL_DWIDTH32
C_SPLB_CTRL_P2P0
C_SPLB_CTRL_MID_WIDTH1
C_SPLB_CTRL_NUM_MASTERS1
C_SPLB_CTRL_SUPPORT_BURSTS0
C_SPLB_CTRL_NATIVE_DWIDTH32
C_SPLB_CTRL_CLK_FREQ_HZ100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ100000000
C_S_AXI_CTRL_BASEADDR0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR0x00000000
C_S_AXI_CTRL_ADDR_WIDTH32
C_S_AXI_CTRL_DATA_WIDTH32
C_S_AXI_CTRL_PROTOCOLAXI4LITE
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
PeripheralsTOC
-
- - - - - - - - - - - - -
- - - - - - - - - -
-ETHERNET -   AXI Ethernet
AXI Ethernet MAC

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_ethernet2.01.aIP
-

-
ETHERNET IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0MDIOIO1ETHERNET_MDIO
1MDCO1ETHERNET_MDC
2GMII_TX_ERO1ETHERNET_TX_ER
3GMII_TXDO1ETHERNET_TXD
4GMII_TX_ENO1ETHERNET_TX_EN
5MII_TX_CLKI1ETHERNET_MII_TX_CLK
6GMII_TX_CLKO1ETHERNET_TX_CLK
7GMII_RXDI1ETHERNET_RXD
8GMII_RX_ERI1ETHERNET_RX_ER
9GMII_RX_CLKI1ETHERNET_RX_CLK
10GMII_RX_DVI1ETHERNET_RX_DV
11PHY_RST_NO1ETHERNET_PHY_RST_N
12S_AXI_ACLKI1clk_50_0000MHzPLL0
13GTX_CLKI1clk_125_0000MHz
14REF_CLKI1clk_200_0000MHzPLL0
15AXI_STR_TXD_ACLKI1clk_100_0000MHzPLL0
16AXI_STR_TXC_ACLKI1clk_100_0000MHzPLL0
17AXI_STR_RXD_ACLKI1clk_100_0000MHzPLL0
18AXI_STR_RXS_ACLKI1clk_100_0000MHzPLL0
19AXI_STR_TXD_ARESETNI1AXI_STR_TXD_ARESETN
20AXI_STR_TXC_ARESETNI1AXI_STR_TXC_ARESETN
21AXI_STR_RXD_ARESETNI1AXI_STR_RXD_ARESETN
22AXI_STR_RXS_ARESETNI1AXI_STR_RXS_ARESETN
23INTERRUPTO1ETHERNET_INTERRUPT
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
AXI_STR_RXSINITIATORAXISETHERNET_dma_rxsETHERNET_dma
AXI_STR_RXDINITIATORAXISETHERNET_dma_rxdETHERNET_dma
S_AXISLAVEAXIaxi4lite_08 Peripherals.
AXI_STR_TXDTARGETAXISETHERNET_dma_txdETHERNET_dma
AXI_STR_TXCTARGETAXISETHERNET_dma_txcETHERNET_dma
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH32
C_AXI_STR_TXD_TDATA_WIDTH32
C_AXI_STR_RXS_TDATA_WIDTH32
C_AXI_STR_RXD_TDATA_WIDTH32
C_AXI_STR_TXC_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOLXIL_AXI_STREAM_ETH_AVB_RX
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x41240000
C_HIGHADDR0x4127FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_S_AXI_ID_WIDTH4
C_TRANSA
C_PHYADDR0B00001
C_INCLUDE_IO1
C_TYPE1
 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_PHY_TYPE1
C_HALFDUP0
C_TXMEM4096
C_RXMEM4096
C_TXCSUM0
C_RXCSUM0
C_TXVLAN_TRAN0
C_RXVLAN_TRAN0
C_TXVLAN_TAG0
C_RXVLAN_TAG0
C_TXVLAN_STRP0
C_RXVLAN_STRP0
C_MCAST_EXTEND0
C_STATS0
C_AVB0
C_SIMULATION0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC0
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-ETHERNET_dma -   AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_dma3.00.aIP
-

-
ETHERNET_dma IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0s_axi_lite_aclkI1clk_100_0000MHzPLL0
1m_axi_sg_aclkI1clk_100_0000MHzPLL0
2m_axi_mm2s_aclkI1clk_100_0000MHzPLL0
3m_axi_s2mm_aclkI1clk_100_0000MHzPLL0
4mm2s_prmry_reset_out_nO1AXI_STR_TXD_ARESETN
5mm2s_cntrl_reset_out_nO1AXI_STR_TXC_ARESETN
6s2mm_prmry_reset_out_nO1AXI_STR_RXD_ARESETN
7s2mm_sts_reset_out_nO1AXI_STR_RXS_ARESETN
8mm2s_introutO1ETHERNET_dma_mm2s_introut
9s2mm_introutO1ETHERNET_dma_s2mm_introut
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
M_AXIS_MM2SINITIATORAXISETHERNET_dma_txdETHERNET
M_AXIS_CNTRLINITIATORAXISETHERNET_dma_txcETHERNET
M_AXI_SGMASTERAXIaxi4_02 Peripherals.
M_AXI_MM2SMASTERAXIaxi4_02 Peripherals.
M_AXI_S2MMMASTERAXIaxi4_02 Peripherals.
S_AXI_LITESLAVEAXIaxi4lite_08 Peripherals.
S_AXIS_STSTARGETAXISETHERNET_dma_rxsETHERNET
S_AXIS_S2MMTARGETAXISETHERNET_dma_rxdETHERNET
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_LITE_ADDR_WIDTH32
C_S_AXI_LITE_DATA_WIDTH32
C_DLYTMR_RESOLUTION1250
C_PRMRY_IS_ACLK_ASYNC0
C_SG_INCLUDE_DESC_QUEUE1
C_SG_INCLUDE_STSCNTRL_STRM1
C_SG_USE_STSAPP_LENGTH1
C_SG_LENGTH_WIDTH16
C_M_AXI_SG_ADDR_WIDTH32
C_M_AXI_SG_DATA_WIDTH32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH32
C_S_AXIS_S2MM_STS_TDATA_WIDTH32
C_INCLUDE_MM2S1
C_INCLUDE_MM2S_DRE1
C_MM2S_BURST_SIZE16
C_M_AXI_MM2S_ADDR_WIDTH32
C_M_AXI_MM2S_DATA_WIDTH32
C_M_AXIS_MM2S_TDATA_WIDTH32
C_INCLUDE_S2MM1
C_INCLUDE_S2MM_DRE1
C_S2MM_BURST_SIZE16
C_M_AXI_S2MM_ADDR_WIDTH32
C_M_AXI_S2MM_DATA_WIDTH32
C_S_AXIS_S2MM_TDATA_WIDTH32
C_FAMILYvirtex6
C_BASEADDR0x41E00000
C_HIGHADDR0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ100000000
C_M_AXI_SG_ACLK_FREQ_HZ100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ100000000
C_S_AXI_LITE_PROTOCOLAXI4LITE
C_S_AXI_LITE_SUPPORTS_READ1
C_S_AXI_LITE_SUPPORTS_WRITE1
C_M_AXI_SG_PROTOCOLAXI4
C_M_AXI_SG_SUPPORTS_THREADS0
C_M_AXI_SG_THREAD_ID_WIDTH1
C_M_AXI_SG_SUPPORTS_NARROW_BURST0
C_M_AXI_SG_SUPPORTS_READ1
C_M_AXI_SG_SUPPORTS_WRITE1
 
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NameValue
C_M_AXI_MM2S_PROTOCOLAXI4
C_M_AXI_MM2S_SUPPORTS_THREADS0
C_M_AXI_MM2S_THREAD_ID_WIDTH1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST0
C_M_AXI_MM2S_SUPPORTS_READ1
C_M_AXI_MM2S_SUPPORTS_WRITE0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH512
C_M_AXI_S2MM_PROTOCOLAXI4
C_M_AXI_S2MM_SUPPORTS_THREADS0
C_M_AXI_S2MM_THREAD_ID_WIDTH1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST0
C_M_AXI_S2MM_SUPPORTS_WRITE1
C_M_AXI_S2MM_SUPPORTS_READ0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH512
C_M_AXIS_MM2S_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOLXIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOLXIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER1
C_INTERCONNECT_M_AXI_SG_W_REGISTER1
C_INTERCONNECT_M_AXI_SG_R_REGISTER1
C_INTERCONNECT_M_AXI_SG_B_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
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-

-
- - - - - - - - - -
-LEDs_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
-

-
LEDs_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_OO1LEDs_4Bits_TRI_O
1S_AXI_ACLKI1clk_50_0000MHzPLL0
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
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-
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
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NameValue
C_FAMILYvirtex6
C_BASEADDR0x40020000
C_HIGHADDR0x4002FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS0
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT0
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-Push_Buttons_4Bits -   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_gpio1.01.aIP
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-
Push_Buttons_4Bits IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0GPIO_IO_II1Push_Buttons_4Bits_TRI_I
1S_AXI_ACLKI1clk_50_0000MHzPLL0
2IP2INTC_IrptO1Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_BASEADDR0x40000000
C_HIGHADDR0x4000FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_GPIO_WIDTH4
C_GPIO2_WIDTH32
C_ALL_INPUTS1
C_ALL_INPUTS_20
C_INTERRUPT_PRESENT1
C_DOUT_DEFAULT0x00000000
 
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NameValue
C_TRI_DEFAULT0xFFFFFFFF
C_IS_DUAL0
C_DOUT_DEFAULT_20x00000000
C_TRI_DEFAULT_20xFFFFFFFF
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-RS232_Uart_1 -   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_uartlite1.01.aIP
-

-
RS232_Uart_1 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0TXO1RS232_Uart_1_sout
1RXI1RS232_Uart_1_sin
2S_AXI_ACLKI1clk_50_0000MHzPLL0
3InterruptO1RS232_Uart_1_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_S_AXI_ACLK_FREQ_HZ100000000
C_BASEADDR0x40600000
C_HIGHADDR0x4060FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
C_BAUDRATE115200
C_DATA_BITS8
 
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NameValue
C_USE_PARITY0
C_ODD_PARITY1
C_S_AXI_PROTOCOLAXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER1
C_INTERCONNECT_S_AXI_AR_REGISTER1
C_INTERCONNECT_S_AXI_W_REGISTER1
C_INTERCONNECT_S_AXI_R_REGISTER1
C_INTERCONNECT_S_AXI_B_REGISTER1
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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-axi_timer_0 -   AXI Timer/Counter
Timer counter with AXI interface

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
axi_timer1.01.aIP
-

-
axi_timer_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0S_AXI_ACLKI1clk_50_0000MHzPLL0
1InterruptO1axi_timer_0_Interrupt
Bus Interfaces
 NAME  TYPE BUSSTDBUSConnected To
S_AXISLAVEAXIaxi4lite_08 Peripherals.
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - -
NameValue
C_S_AXI_PROTOCOLAXI4LITE
C_FAMILYvirtex6
C_COUNT_WIDTH32
C_ONE_TIMER_ONLY0
C_TRIG0_ASSERT1
C_TRIG1_ASSERT1
 
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NameValue
C_GEN0_ASSERT1
C_GEN1_ASSERT1
C_BASEADDR0x41C00000
C_HIGHADDR0x41C0FFFF
C_S_AXI_ADDR_WIDTH32
C_S_AXI_DATA_WIDTH32
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
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-

- - -
IPTOC
-
- - - - -
- - - - - - - - - -
-clock_generator_0 -   Clock Generator
Clock generator for processor system.

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
clock_generator4.01.aIP
-

-
clock_generator_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0RSTI1RESET
1CLKINI1CLK
2CLKOUT2O1clk_100_0000MHzPLL0
3CLKOUT5O1clk_50_0000MHzPLL0
4CLKOUT3O1clk_125_0000MHz
5CLKOUT4O1clk_200_0000MHzPLL0
6CLKOUT0O1clk_600_0000MHzPLL0_nobuf
7CLKOUT1O1clk_600_0000MHz180PLL0_nobuf
8LOCKEDO1proc_sys_reset_0_Dcm_locked
-

-
- - - - - - - -
Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameValue
C_FAMILYvirtex6
C_DEVICENOT_SET
C_PACKAGENOT_SET
C_SPEEDGRADENOT_SET
C_CLKIN_FREQ200000000
C_CLKOUT0_FREQ600000000
C_CLKOUT0_PHASE0
C_CLKOUT0_GROUPPLL0
C_CLKOUT0_BUFFALSE
C_CLKOUT0_VARIABLE_PHASEFALSE
C_CLKOUT1_FREQ600000000
C_CLKOUT1_PHASE180
C_CLKOUT1_GROUPPLL0
C_CLKOUT1_BUFFALSE
C_CLKOUT1_VARIABLE_PHASEFALSE
C_CLKOUT2_FREQ100000000
C_CLKOUT2_PHASE0
C_CLKOUT2_GROUPPLL0
C_CLKOUT2_BUFTRUE
C_CLKOUT2_VARIABLE_PHASEFALSE
C_CLKOUT3_FREQ125000000
C_CLKOUT3_PHASE0
C_CLKOUT3_GROUPNONE
C_CLKOUT3_BUFTRUE
C_CLKOUT3_VARIABLE_PHASEFALSE
C_CLKOUT4_FREQ200000000
C_CLKOUT4_PHASE0
C_CLKOUT4_GROUPPLL0
C_CLKOUT4_BUFTRUE
C_CLKOUT4_VARIABLE_PHASEFALSE
C_CLKOUT5_FREQ50000000
C_CLKOUT5_PHASE0
C_CLKOUT5_GROUPPLL0
C_CLKOUT5_BUFTRUE
C_CLKOUT5_VARIABLE_PHASEFALSE
C_CLKOUT6_FREQ0
C_CLKOUT6_PHASE0
C_CLKOUT6_GROUPNONE
C_CLKOUT6_BUFTRUE
C_CLKOUT6_VARIABLE_PHASEFALSE
C_CLKOUT7_FREQ0
C_CLKOUT7_PHASE0
C_CLKOUT7_GROUPNONE
C_CLKOUT7_BUFTRUE
C_CLKOUT7_VARIABLE_PHASEFALSE
C_CLKOUT8_FREQ0
C_CLKOUT8_PHASE0
C_CLKOUT8_GROUPNONE
 
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NameValue
C_CLKOUT8_BUFTRUE
C_CLKOUT8_VARIABLE_PHASEFALSE
C_CLKOUT9_FREQ0
C_CLKOUT9_PHASE0
C_CLKOUT9_GROUPNONE
C_CLKOUT9_BUFTRUE
C_CLKOUT9_VARIABLE_PHASEFALSE
C_CLKOUT10_FREQ0
C_CLKOUT10_PHASE0
C_CLKOUT10_GROUPNONE
C_CLKOUT10_BUFTRUE
C_CLKOUT10_VARIABLE_PHASEFALSE
C_CLKOUT11_FREQ0
C_CLKOUT11_PHASE0
C_CLKOUT11_GROUPNONE
C_CLKOUT11_BUFTRUE
C_CLKOUT11_VARIABLE_PHASEFALSE
C_CLKOUT12_FREQ0
C_CLKOUT12_PHASE0
C_CLKOUT12_GROUPNONE
C_CLKOUT12_BUFTRUE
C_CLKOUT12_VARIABLE_PHASEFALSE
C_CLKOUT13_FREQ0
C_CLKOUT13_PHASE0
C_CLKOUT13_GROUPNONE
C_CLKOUT13_BUFTRUE
C_CLKOUT13_VARIABLE_PHASEFALSE
C_CLKOUT14_FREQ0
C_CLKOUT14_PHASE0
C_CLKOUT14_GROUPNONE
C_CLKOUT14_BUFTRUE
C_CLKOUT14_VARIABLE_PHASEFALSE
C_CLKOUT15_FREQ0
C_CLKOUT15_PHASE0
C_CLKOUT15_GROUPNONE
C_CLKOUT15_BUFTRUE
C_CLKOUT15_VARIABLE_PHASEFALSE
C_CLKFBIN_FREQ0
C_CLKFBIN_DESKEWNONE
C_CLKFBOUT_FREQ0
C_CLKFBOUT_PHASE0
C_CLKFBOUT_GROUPNONE
C_CLKFBOUT_BUFTRUE
C_PSDONE_GROUPNONE
C_EXT_RESET_HIGH1
C_CLK_PRIMITIVE_FEEDBACK_BUFFALSE
C_CLK_GENUPDATE
 
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
- - - - - - - - - -
-proc_sys_reset_0 -   Processor System Reset Module
Reset management module

-
- - - - - - - - - - -
IP Specs
CoreVersionDocumentation
proc_sys_reset3.00.aIP
-

-
proc_sys_reset_0 IP Image - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#NAMEDIR[LSB:MSB]SIGNAL
0Ext_Reset_InI1RESET
1MB_ResetO1proc_sys_reset_0_MB_Reset
2Slowest_sync_clkI1clk_50_0000MHzPLL0
3Interconnect_aresetnO1proc_sys_reset_0_Interconnect_aresetn
4Dcm_lockedI1proc_sys_reset_0_Dcm_locked
5MB_Debug_Sys_RstI1proc_sys_reset_0_MB_Debug_Sys_Rst
6BUS_STRUCT_RESETO1proc_sys_reset_0_BUS_STRUCT_RESET
-

-
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Parameters
- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -
NameValue
C_SUBFAMILYlx
C_EXT_RST_WIDTH4
C_AUX_RST_WIDTH4
C_EXT_RESET_HIGH1
C_AUX_RESET_HIGH1
C_NUM_BUS_RST1
C_NUM_PERP_RST1
C_NUM_INTERCONNECT_ARESETN1
C_NUM_PERP_ARESETN1
C_FAMILYvirtex5
- - - - -
Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -
-
-

-
-
-

- - -
Timing InformationTOC
-

- - - -
Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -
-
- - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html deleted file mode 100644 index 88f408ceb..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html +++ /dev/null @@ -1,73 +0,0 @@ - - - - -Table of Contents - - - - -
-Overview
Block Diagram
External Ports
- Processor -
-   microblaze_0
- Debuggers -
-   debug_module
- Interrupt Controllers -
-   microblaze_0_intc
- Busses -
-   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
- Memory -
-   microblaze_0_bram_block
- Memory Controllers -
-   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
- Peripherals -
-   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
- IP -
-   clock_generator_0
   proc_sys_reset_0
Timing Information
-
- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log deleted file mode 100644 index 5855e82bc..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log +++ /dev/null @@ -1,563 +0,0 @@ -========================================================================= -Time: Sat Aug 27 15:05:27 GMT Daylight Time 2011 -Running: run_batch_mode 96334104 -{COLLECTING: INSTANCE MCB_DDR3 } -{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} -{COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_AW_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_AR_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_W_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_R_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_B_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S0_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S0_AXI_AXI_VER 1.02.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S1_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S1_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S1_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S1_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S2_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S2_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S2_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S2_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S3_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S3_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S3_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S3_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S4_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S4_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S4_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S4_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S5_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S5_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S5_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S5_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_MCB_LOC MEMC3 OPTIONAL MEMC3 } -{COLLECTING: C_MCB_RZQ_LOC K7 OPTIONAL STRING NOT_SET K7} -{COLLECTING: C_MCB_ZIO_LOC R7 OPTIONAL STRING NOT_SET R7} -{COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD } -{COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 } -{COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000} -{COLLECTING: C_S0_AXI_HIGHADDR 0x807FFFFF OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x807FFFFF} -{COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S2_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S3_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S3_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S4_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 } -{COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E} -{COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET } -{COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 } -{COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 } -{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 } -{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 } -{COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRFC -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRP -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TWR -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 } -{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE } -{COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 } -{COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN } -{COLLECTING: C_MEM_TZQINIT_MAXCNT 512 UPDATE INTEGER 512 } -{COLLECTING: C_MEM_CAS_LATENCY 6 UPDATE INTEGER 6 } -{COLLECTING: C_SIMULATION FALSE OPTIONAL STRING FALSE } -{COLLECTING: C_MEM_DDR1_2_ODS FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } -{COLLECTING: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } -{COLLECTING: C_MEM_DDR2_RTT 150OHMS OPTIONAL STRING 150OHMS } -{COLLECTING: C_MEM_DDR2_DIFF_DQS_EN YES OPTIONAL STRING YES } -{COLLECTING: C_MEM_DDR2_3_PA_SR FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL OPTIONAL STRING NORMAL } -{COLLECTING: C_MEM_DDR3_CAS_WR_LATENCY 5 UPDATE INTEGER 5 } -{COLLECTING: C_MEM_DDR3_CAS_LATENCY 6 UPDATE INTEGER 6 } -{COLLECTING: C_MEM_DDR3_ODS DIV6 OPTIONAL STRING DIV6 } -{COLLECTING: C_MEM_DDR3_RTT DIV4 OPTIONAL STRING DIV4 } -{COLLECTING: C_MEM_DDR3_AUTO_SR ENABLED OPTIONAL STRING ENABLED } -{COLLECTING: C_MEM_MOBILE_PA_SR FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_MDDR_ODS FULL OPTIONAL STRING FULL } -{COLLECTING: C_ARB_ALGORITHM 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_ARB_NUM_TIME_SLOTS 12 OPTIONAL INTEGER 12 } -{COLLECTING: C_ARB_TIME_SLOT_0 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_1 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_2 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_3 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_ARB_TIME_SLOT_4 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_5 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_6 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_7 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_ARB_TIME_SLOT_8 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 } -{COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S0_AXI_ID_WIDTH 3 UPDATE INTEGER 4 } -{COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } -{COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S0_AXI_STRICT_COHERENCY 0 OPTIONAL_UPDATE INTEGER 1 0} -{COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S1_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S1_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S1_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } -{COLLECTING: C_S1_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S1_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S1_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S2_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S2_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S2_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S2_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S2_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S2_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S2_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S2_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S3_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S3_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S3_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S3_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S3_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S3_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S3_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S3_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S4_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S4_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S4_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S4_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S4_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S4_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S4_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S4_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S5_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S5_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S5_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S5_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S5_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S5_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S5_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S5_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_MCB_USE_EXTERNAL_BUFPLL 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_SYS_RST_PRESENT 1 UPDATE INTEGER 0 } -{COLLECTING: HW_VER 1.02.a } -{SENDING PARAMETER: C_ARB_ALGORITHM : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_ARB_NUM_TIME_SLOTS : 12 INTEGER OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_0 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_1 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_2 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_3 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_4 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_5 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_6 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_7 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_8 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_9 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_10 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_11 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_BYPASS_CORE_UCF : 0 {} OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_ACLK_RATIO : 100000000 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AR_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_W_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_MCB_LOC : MEMC3 {} OPTIONAL} -{SENDING PARAMETER: C_MCB_PERFORMANCE : STANDARD STRING OPTIONAL} -{SENDING PARAMETER: C_MCB_RZQ_LOC : K7 STRING OPTIONAL} -{SENDING PARAMETER: C_MCB_USE_EXTERNAL_BUFPLL : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_MCB_ZIO_LOC : R7 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_ADDR_ORDER : ROW_BANK_COLUMN STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_ADDR_WIDTH : 13 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_BANKADDR_WIDTH : 3 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_BASEPARTNO : NOT_SET STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_CAS_LATENCY : 6 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR1_2_ODS : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_3_HIGH_TEMP_SR : NORMAL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_3_PA_SR : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_DIFF_DQS_EN : YES STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_RTT : 150OHMS STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_AUTO_SR : ENABLED STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_CAS_LATENCY : 6 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR3_CAS_WR_LATENCY : 5 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR3_ODS : DIV6 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_RTT : DIV4 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_MDDR_ODS : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_MOBILE_PA_SR : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_NUM_COL_BITS : 10 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_PARTNO : MT41J64M16XX-187E STRING REQUIRE} -{SENDING PARAMETER: C_MEM_TRAS : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRCD : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TREFI : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRFC : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRP : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRTP : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TWR : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TWTR : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TYPE : DDR3 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_TZQINIT_MAXCNT : 512 INTEGER UPDATE} -{SENDING PARAMETER: C_MEMCLK_PERIOD : 0 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_NUM_DQ_PINS : 16 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_PORT_CONFIG : B32_B32_B32_B32 STRING OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S0_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S0_AXI_AXI_VER : 1.02.a {} CONSTANT} -{SENDING PARAMETER: C_S0_AXI_BASEADDR : 0x80000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x807FFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 3 INTEGER UPDATE} -{SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 0 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S1_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S1_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S1_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S1_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S1_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S2_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S2_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S2_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S2_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S2_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S2_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S3_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S3_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S3_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S3_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S3_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S3_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S4_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S4_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S4_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S4_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S4_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S4_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S5_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S5_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S5_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S5_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S5_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S5_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_SIMULATION : FALSE STRING OPTIONAL} -{SENDING PARAMETER: C_SKIP_IN_TERM_CAL : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_SKIP_IN_TERM_CAL_VALUE : NONE STRING OPTIONAL} -{SENDING PARAMETER: C_SYS_RST_PRESENT : 1 INTEGER UPDATE} -{SENDING PARAMETER: HW_VER : 1.02.a {} {}} -{SENDING PARAMETER: INSTANCE : MCB_DDR3 {} {}} -{Executing C:/devtools/Xilinx/13.1/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_7/bin/nt/mig.exe -cg_exc_inp mig_input.txt -cg_exc_out mig_output.txt} -{SET: IGNORE C_MCB_LOC = MEMC3 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR3_ODS = DIV6 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_ZIO_LOC = R7 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: UPDATE C_S4_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_BASEADDR = 0x80000000 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_MDDR_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)} -{SET: IGNORE C_S0_AXI_STRICT_COHERENCY = 0 (BATCH:OPTIONAL_UPDATE::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_NUM_TIME_SLOTS = 12 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S5_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S2_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TRTP = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_HIGHADDR = 0x807FFFFF (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_ENABLE_AP = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TWR = 15000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TWTR = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_S3_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TRAS = 37500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDREM C_MEM_DDR3_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: UPDATE C_S5_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S1_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRCD = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_0 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_ALGORITHM = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRP = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_1 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_2 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_3 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR3_AUTO_SR = ENABLED (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_4 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_5 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_6 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_7 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEMCLK_PERIOD = 0 (BATCH:OPTIONAL_UPDATE:SKIP_BATCH:MPD:MPDVAL)} -{SET: IGNORE C_MCB_RZQ_LOC = K7 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_8 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_ADDR_ORDER = ROW_BANK_COLUMN (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_USE_EXTERNAL_BUFPLL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_R_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_9 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_S4_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S1_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_SKIP_IN_TERM_CAL_VALUE = NONE (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S2_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR2_3_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_PORT_CONFIG = B32_B32_B32_B32 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)} -{SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -RETURN: 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html deleted file mode 100644 index 7ac689bd4..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html +++ /dev/null @@ -1,565 +0,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - -
Project Status (08/27/2011 - 12:37:45)
Project File:system.xmpImplementation State:Programming File Generated
Module Name:system
  • Errors:
-No Errors
Product Version:EDK 13.1
  • Warnings:
238 Warnings (0 new)
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XPS Reports [-]
Report NameGeneratedErrorsWarningsInfos
Platgen Log FileSat 27. Aug 12:17:02 2011019 Warnings (18 new)34 Infos (32 new)
Libgen Log File    
Simgen Log File    
BitInit Log File    
System Log FileSat 27. Aug 12:34:09 2011   

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XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemSat 27. Aug 12:17:50 20111469614247140
mcb_ddr3_wrapperSat 27. Aug 12:16:50 2011373690 0
debug_module_wrapperSat 27. Aug 12:16:27 2011131142 0
clock_generator_0_wrapperSat 27. Aug 12:16:17 2011 1 0
microblaze_0_bram_block_wrapperSat 27. Aug 12:16:12 2011  40
microblaze_0_d_bram_ctrl_wrapperSat 27. Aug 12:16:06 201126 0
microblaze_0_i_bram_ctrl_wrapperSat 27. Aug 12:16:01 201126 0
axi4lite_0_wrapperSat 27. Aug 12:15:55 201129051827 0
axi_timer_0_wrapperFri 26. Aug 21:17:55 2011260272 0
microblaze_0_intc_wrapperFri 26. Aug 21:17:45 201186115 0
ethernet_dma_wrapperFri 26. Aug 21:17:37 201137283798 0
ethernet_dma_wrapper_fifo_generator_v8_1_6_fifo_generator_v8_1_xst_1Fri 26. Aug 21:16:56 2011107109 0
ethernet_dma_wrapper_fifo_generator_v8_1_7_fifo_generator_v8_1_xst_1Fri 26. Aug 21:15:53 201198100 0
ethernet_dma_wrapper_fifo_generator_v8_1_2_fifo_generator_v8_1_xst_1Fri 26. Aug 21:14:50 2011684910
ethernet_dma_wrapper_fifo_generator_v8_1_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:13:47 2011745910
ethernet_dma_wrapper_fifo_generator_v8_1_5_fifo_generator_v8_1_xst_1Fri 26. Aug 21:12:44 2011694910
ethernet_dma_wrapper_fifo_generator_v8_1_4_fifo_generator_v8_1_xst_1Fri 26. Aug 21:11:41 201199103 0
ethernet_dma_wrapper_fifo_generator_v8_1_3_fifo_generator_v8_1_xst_1Fri 26. Aug 21:10:39 20119798 0
ethernet_wrapperFri 26. Aug 21:09:24 201131663264 0
ethernet_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:08:27 2011104148 0
ethernet_wrapper_blk_mem_gen_v5_2_2_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:07:29 2011  10
ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:07:03 2011  20
ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:36 2011  10
ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:10 201124920
push_buttons_4bits_wrapperFri 26. Aug 21:04:24 20117285 0
leds_4bits_wrapperFri 26. Aug 21:04:14 20113341 0
rs232_uart_1_wrapperFri 26. Aug 21:04:05 201184102 0
proc_sys_reset_0_wrapperFri 26. Aug 21:03:43 20116955 0
microblaze_0_dlmb_wrapperFri 26. Aug 21:03:19 201111 0
microblaze_0_ilmb_wrapperFri 26. Aug 21:03:15 201111 0
microblaze_0_wrapperFri 26. Aug 21:03:10 201113011703 0
axi4_0_wrapperFri 26. Aug 21:02:14 201114881083 0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1Fri 26. Aug 21:01:57 2011909720
axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:00:49 2011899610

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Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers12,06054,57622% 
    Number used as Flip Flops12,052   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics8   
Number of Slice LUTs10,94027,28840% 
    Number used as logic9,63927,28835% 
        Number using O6 output only6,889   
        Number using O5 output only260   
        Number using O5 and O62,490   
        Number used as ROM0   
    Number used as Memory6936,40810% 
        Number used as Dual Port RAM250   
            Number using O6 output only10   
            Number using O5 output only4   
            Number using O5 and O6236   
        Number used as Single Port RAM1   
            Number using O6 output only1   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Shift Register442   
            Number using O6 output only205   
            Number using O5 output only7   
            Number using O5 and O6230   
    Number used exclusively as route-thrus608   
        Number with same-slice register load566   
        Number with same-slice carry load37   
        Number with other load5   
Number of occupied Slices4,5896,82267% 
Number of LUT Flip Flop pairs used13,843   
    Number with an unused Flip Flop3,76513,84327% 
    Number with an unused LUT2,90313,84320% 
    Number of fully used LUT-FF pairs7,17513,84351% 
    Number of unique control sets697   
    Number of slice register sites lost
        to control set restrictions
2,54154,5764% 
Number of bonded IOBs8729629% 
    Number of LOCed IOBs8787100% 
    IOB Flip Flops27   
Number of RAMB16BWERs1211610% 
Number of RAMB8BWERs42321% 
Number of BUFIO2/BUFIO2_2CLKs3329% 
    Number used as BUFIO2s3   
    Number used as BUFIO2_2CLKs0   
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs61637% 
    Number used as BUFGs5   
    Number used as BUFGMUX1   
Number of DCM/DCM_CLKGENs080% 
Number of ILOGIC2/ISERDES2s123763% 
    Number used as ILOGIC2s12   
    Number used as ISERDES2s0   
Number of IODELAY2/IODRP2/IODRP2_MCBs343769% 
    Number used as IODELAY2s10   
    Number used as IODRP2s2   
    Number used as IODRP2_MCBs22   
Number of OLOGIC2/OSERDES2s6037615% 
    Number used as OLOGIC2s14   
    Number used as OSERDES2s46   
Number of BSCANs1425% 
Number of BUFHs02560% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs1425% 
Number of DSP48A1s3585% 
Number of GTPA1_DUALs020% 
Number of ICAPs010% 
Number of MCBs1250% 
Number of PCIE_A1s010% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs2450% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.89   
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Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0, Component Switching Limit: 0)Pinout Data:Pinout Report
Routing Results: -All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: -All Constraints Met  
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Translation ReportCurrentSat 27. Aug 12:19:05 2011087 Warnings (0 new)13 Infos (8 new)
Map ReportCurrentSat 27. Aug 12:28:13 2011050 Warnings (0 new)1134 Infos (0 new)
Place and Route ReportCurrentSat 27. Aug 12:31:43 2011051 Warnings (0 new)3 Infos (0 new)
Post-PAR Static Timing ReportCurrentSat 27. Aug 12:32:50 201103 Warnings (0 new)3 Infos (0 new)
Bitgen ReportCurrentSat 27. Aug 12:34:09 2011047 Warnings (0 new)0

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Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentSat 27. Aug 12:34:09 2011
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Date Generated: 08/27/2011 - 12:37:46
- \ No newline at end of file -- 2.39.5