From f59d2d9ecfee8899df531b87b7acaa468725f238 Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <linux@rempel-privat.de>
Date: Fri, 30 Jan 2015 13:05:31 +0100
Subject: [PATCH] tcl/target|board: add config Atheros ar9331

Add configs for Atheros ar9331 MIPS based WiSoC and
board based on this chip: TP-LINK TL-MR3020

Change-Id: I9e99719bce4bbb28311f6e9cddb32288db6e7b91
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2519
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
---
 tcl/board/tp-link_tl-mr3020.cfg | 44 +++++++++++++++++++++++++++++++++
 tcl/target/atheros_ar9331.cfg   | 16 ++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 tcl/board/tp-link_tl-mr3020.cfg
 create mode 100644 tcl/target/atheros_ar9331.cfg

diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
new file mode 100644
index 00000000..0498d60c
--- /dev/null
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -0,0 +1,44 @@
+source [find target/atheros_ar9331.cfg]
+
+proc ar9331_25mhz_pll_init {} {
+	mww 0xb8050008 0x00018004	;# bypass PLL; AHB_POST_DIV - ratio 4
+	mww 0xb8050004 0x00000352	;# 34000(ns)/40ns(25MHz) = 0x352 (850)
+	mww 0xb8050000 0x40818000	;# Power down control for CPU PLL
+					;# OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050010 0x001003e8	;# CPU PLL Dither FRAC Register
+					;# (disabled?)
+	mww 0xb8050000 0x00818000	;# Power on | OUTDIV | REFDIV | DIV_INT
+	mww 0xb8050008 0x00008000	;# remove bypass;
+					;# AHB_POST_DIV - ratio 2
+}
+
+proc ar9331_ddr1_init {} {
+	mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
+	mww 0xb8000004 0x9dd0e6a8	;# DDR_CONFIG2 - more DRAM confs
+
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x133	;# mode reg: 0x133 - default
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb800000c 0x2	;# Extended mode register value.
+				;# default 0x2 - Reset to weak driver, DLL on
+	mww 0xb8000010 0x2	;# Forces an EMRS update cycle
+	mww 0xb8000010 0x8	;# Forces a PRECHARGE ALL cycle
+	mww 0xb8000008 0x33	;# mode reg: remove some bit?
+	mww 0xb8000010 0x1	;# Forces an MRS update cycl
+	mww 0xb8000014 0x4186	;# enable refres: bit(14) - set refresh rate
+	mww 0xb800001c 0x8	;# This register is used along with DQ Lane 0,
+				;# DQ[7:0], DQS_0
+	mww 0xb8000020 0x9	;# This register is used along with DQ Lane 1,
+				;# DQ[15:8], DQS_1.
+	mww 0xb8000018 0xff	;# DDR read and capture bit mask.
+				;# Each bit represents a cycle of valid data.
+}
+
+$TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr1_init
+}
+
+set ram_boot_address 0xa0000000
+$TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
new file mode 100644
index 00000000..17503c78
--- /dev/null
+++ b/tcl/target/atheros_ar9331.cfg
@@ -0,0 +1,16 @@
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9331
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set TARGETNAME $_CHIPNAME.cpu
+target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
-- 
2.39.5