From fbecbaa158329b882b1c024f845bc52cf4562b47 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 12 Aug 2015 17:46:51 +0800 Subject: [PATCH] net: fec: do not access reserved register for i.MX6UL The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan Signed-off-by: Fugang Duan Cc: Joe Hershberger Cc: Stefano Babic --- drivers/net/fec_mxc.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index c5dcbbbced..bff5fd1119 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd) writel(0x00000000, &fec->eth->gaddr2); - /* clear MIB RAM */ - for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) - writel(0, i); + /* Do not access reserved register for i.MX6UL */ + if (!is_cpu_type(MXC_CPU_MX6UL)) { + /* clear MIB RAM */ + for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) + writel(0, i); - /* FIFO receive start register */ - writel(0x520, &fec->eth->r_fstart); + /* FIFO receive start register */ + writel(0x520, &fec->eth->r_fstart); + } /* size and address of each buffer */ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); -- 2.39.5