From fc009d9ffda09eec6ae49eb02318867900f20c3e Mon Sep 17 00:00:00 2001 From: RichardBarry Date: Wed, 21 May 2008 17:59:30 +0000 Subject: [PATCH] Add STM32 Keil demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@376 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h | 102 ++++ Demo/CORTEX_STM32F103_Keil/LCD_Message.h | 502 +++++++++++++++++++ Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c | 133 +++++ Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt | 72 +++ Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2 | 130 +++++ Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg | 9 + Demo/CORTEX_STM32F103_Keil/RTOSDemo.sct | 15 + Demo/CORTEX_STM32F103_Keil/STM32F10x.s | 294 +++++++++++ Demo/CORTEX_STM32F103_Keil/main.c | 456 +++++++++++++++++ Demo/CORTEX_STM32F103_Keil/serial/serial.c | 250 +++++++++ Demo/CORTEX_STM32F103_Keil/spi_flash.c | 498 ++++++++++++++++++ Demo/CORTEX_STM32F103_Keil/stm32f10x_conf.h | 137 +++++ Demo/CORTEX_STM32F103_Keil/timertest.c | 183 +++++++ 13 files changed, 2781 insertions(+) create mode 100644 Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h create mode 100644 Demo/CORTEX_STM32F103_Keil/LCD_Message.h create mode 100644 Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c create mode 100644 Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt create mode 100644 Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2 create mode 100644 Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg create mode 100644 Demo/CORTEX_STM32F103_Keil/RTOSDemo.sct create mode 100644 Demo/CORTEX_STM32F103_Keil/STM32F10x.s create mode 100644 Demo/CORTEX_STM32F103_Keil/main.c create mode 100644 Demo/CORTEX_STM32F103_Keil/serial/serial.c create mode 100644 Demo/CORTEX_STM32F103_Keil/spi_flash.c create mode 100644 Demo/CORTEX_STM32F103_Keil/stm32f10x_conf.h create mode 100644 Demo/CORTEX_STM32F103_Keil/timertest.c diff --git a/Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h b/Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..f7d0160b9 --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h @@ -0,0 +1,102 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 72000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 17 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255 +(lowest) to 0 (1?) (highest). */ +#define configKERNEL_INTERRUPT_PRIORITY 255 + +/* This is the value being used as per the ST library which permits 16 +priority values, 0 to 15. This must correspond to the +configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest +NVIC value of 255. */ +#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/Demo/CORTEX_STM32F103_Keil/LCD_Message.h b/Demo/CORTEX_STM32F103_Keil/LCD_Message.h new file mode 100644 index 000000000..2323c015f --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/LCD_Message.h @@ -0,0 +1,502 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +/* The structure passed to the LCD when there is text to display. */ +typedef struct +{ + long xColumn; + signed char *pcMessage; +} xLCDMessage; + +/* The bitmap displayed on the LCD when the LCD task starts. */ +const unsigned portCHAR pcBitmap[] = +{ +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x80, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, +0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, +0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, +0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, +0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, +0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf0, +0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0xbe, +0x4d, 0x42, 0x00 +}; + + +#endif + diff --git a/Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c b/Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c new file mode 100644 index 000000000..aaa24c789 --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* FreeRTOS.org includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/* Library includes. */ +#include "stm32f10x_lib.h" + +#define partstMAX_OUTPUT_LED ( 4 ) +#define partstFIRST_LED GPIO_Pin_6 + +static unsigned portSHORT usOutputValue = 0; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure PC.06, PC.07, PC.08 and PC.09 as output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init( GPIOC, &GPIO_InitStructure ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( xValue == pdFALSE ) + { + usBit ^= ( unsigned portSHORT ) 0xffff; + usOutputValue &= usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOC, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( usOutputValue & usBit ) + { + usOutputValue &= ~usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOC, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt new file mode 100644 index 000000000..5a5c2003a --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt @@ -0,0 +1,72 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (Target 1), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(System),0,0,0 +GRPOPT 2,(Demo Files),0,0,0 +GRPOPT 3,(FreeRTOS files),0,0,0 + +OPTFFF 1,1,2,0,0,0,0,0,<.\STM32F10x.s> +OPTFFF 1,2,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\lcd.c> +OPTFFF 1,3,2,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\cortexm3_macro_rvds.s> +OPTFFF 1,4,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_usart.c> +OPTFFF 1,5,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_gpio.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_lib.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_nvic.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_rcc.c> +OPTFFF 1,9,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_spi.c> +OPTFFF 1,10,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_systick.c> +OPTFFF 1,11,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_tim.c> +OPTFFF 2,12,1,285212672,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 2,13,1,0,0,0,0,0,<.\serial\serial.c> +OPTFFF 2,14,1,0,0,0,0,0,<.\timertest.c> +OPTFFF 2,15,1,117440512,0,0,0,0,<.\main.c> +OPTFFF 2,16,1,0,0,0,0,0,<.\spi_flash.c> +OPTFFF 2,17,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 2,18,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 2,19,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c> +OPTFFF 2,20,1,0,0,0,0,0,<..\Common\Minimal\comtest.c> +OPTFFF 2,21,1,0,0,0,0,0,<..\Common\Minimal\death.c> +OPTFFF 2,22,1,0,0,0,0,0,<..\Common\Minimal\flash.c> +OPTFFF 2,23,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 2,24,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 3,25,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 3,26,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 3,27,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 3,28,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 3,29,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> + + +TARGOPT 1, (Target 1) + ADSCLK=8000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 255 + OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB) + OPTDBG 48126,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)) + OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)) + OPTKEY 0,(DLGDARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T0) + OPTKEY 0,(JLTAgdi)(-O1038 -J1 -Y1000 -Z1 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + OPTKEY 0,(UL2CM3)(-UU0226F8E -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP7 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + OPTBB 0,0,237,1,134228048,0,0,0,0,1,()() + OPTDF 0x82 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2 b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2 new file mode 100644 index 000000000..183c54156 --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2 @@ -0,0 +1,130 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (Target 1), 0x0004 // Tools: 'ARM-ADS' + +Group (System) +Group (Demo Files) +Group (FreeRTOS files) + +File 1,2,<.\STM32F10x.s> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\lcd.c> +File 1,2,<..\Common\drivers\ST\STM32F10xFWLib\src\cortexm3_macro_rvds.s> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_usart.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_gpio.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_lib.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_nvic.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_rcc.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_spi.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_systick.c> +File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_tim.c> +File 2,1,<.\ParTest\ParTest.c> +File 2,1,<.\serial\serial.c> +File 2,1,<.\timertest.c> +File 2,1,<.\main.c> +File 2,1,<.\spi_flash.c> +File 2,1,<..\Common\Minimal\semtest.c> +File 2,1,<..\Common\Minimal\BlockQ.c> +File 2,1,<..\Common\Minimal\blocktim.c> +File 2,1,<..\Common\Minimal\comtest.c> +File 2,1,<..\Common\Minimal\death.c> +File 2,1,<..\Common\Minimal\flash.c> +File 2,1,<..\Common\Minimal\integer.c> +File 2,1,<..\Common\Minimal\PollQ.c> +File 3,1,<..\..\Source\tasks.c> +File 3,1,<..\..\Source\list.c> +File 3,1,<..\..\Source\queue.c> +File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +File 3,1,<..\..\Source\portable\MemMang\heap_2.c> + + +Options 1,0,0 // Target 'Target 1' + Device (STM32F103VB) + Vendor (STMicroelectronics) + Cpu (IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")) + FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)) + DevID (4223) + Rgf (stm32f10x_lib.h) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿST\STM32F10x\) + OrgReg (ÿST\STM32F10x\) + TgStat=16 + OutDir (.\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,80,0,0 } + OCMADSIROM { 1,0,0,0,8,0,0,2,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,2,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,80,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (..\CORTEX_STM32F103_Keil;..\Common\include;..\..\Source\include;..\Common\drivers\ST\STM32F10xFWLib\inc) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x08000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC () + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB) + OPTDBG 48126,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + FLASH1 { 9,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2CM3.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg new file mode 100644 index 000000000..4b3970218 --- /dev/null +++ b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg @@ -0,0 +1,9 @@ + + +
+
µVision3 Build Log

+
Project:

+C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_STM32F103_Keil\RTOSDemo.uv2
+Project File Date:  05/21/2008
+
+
Output:

diff --git a/Demo/CORTEX_STM32F103_Keil/RTOSDemo.sct b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.sct
new file mode 100644
index 000000000..f67cd6876
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/RTOSDemo.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00005000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10x.s b/Demo/CORTEX_STM32F103_Keil/STM32F10x.s
new file mode 100644
index 000000000..8c2b0762a
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10x.s
@@ -0,0 +1,294 @@
+;/*****************************************************************************/
+;/* STM32F10x.s: Startup file for ST STM32F10x device series                  */
+;/*****************************************************************************/
+;/* <<< Use Configuration Wizard in Context Menu >>>                          */
+;/*****************************************************************************/
+;/* This file is part of the uVision/ARM development tools.                   */
+;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.               */
+;/* This software may only be used under the terms of a valid, current,       */
+;/* end user licence from KEIL for a compatible version of KEIL software      */
+;/* development tools. Nothing else gives you the right to use this software. */
+;/*****************************************************************************/
+
+
+;//  Stack Configuration
+;//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// 
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;//  Heap Configuration
+;//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+				IMPORT xPortPendSVHandler
+				IMPORT xPortSysTickHandler
+				IMPORT vPortSVCHandler
+				IMPORT vUARTInterruptHandler
+				IMPORT vTimer2IntHandler
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     vPortSVCHandler           ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     xPortPendSVHandler        ; PendSV Handler
+                DCD     xPortSysTickHandler       ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+                DCD     RTC_IRQHandler            ; RTC
+                DCD     FLASH_IRQHandler          ; Flash
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMAChannel1_IRQHandler    ; DMA Channel 1
+                DCD     DMAChannel2_IRQHandler    ; DMA Channel 2
+                DCD     DMAChannel3_IRQHandler    ; DMA Channel 3
+                DCD     DMAChannel4_IRQHandler    ; DMA Channel 4
+                DCD     DMAChannel5_IRQHandler    ; DMA Channel 5
+                DCD     DMAChannel6_IRQHandler    ; DMA Channel 6
+                DCD     DMAChannel7_IRQHandler    ; DMA Channel 7
+                DCD     ADC_IRQHandler            ; ADC
+                DCD     USB_HP_CAN_TX_IRQHandler  ; USB High Priority or CAN TX
+                DCD     USB_LP_CAN_RX0_IRQHandler ; USB Low  Priority or CAN RX0
+                DCD     CAN_RX1_IRQHandler        ; CAN RX1
+                DCD     CAN_SCE_IRQHandler        ; CAN SCE
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+                DCD     vTimer2IntHandler         ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     vUARTInterruptHandler     ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler           [WEAK]
+                EXPORT  PVD_IRQHandler            [WEAK]
+                EXPORT  TAMPER_IRQHandler         [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  FLASH_IRQHandler          [WEAK]
+                EXPORT  RCC_IRQHandler            [WEAK]
+                EXPORT  EXTI0_IRQHandler          [WEAK]
+                EXPORT  EXTI1_IRQHandler          [WEAK]
+                EXPORT  EXTI2_IRQHandler          [WEAK]
+                EXPORT  EXTI3_IRQHandler          [WEAK]
+                EXPORT  EXTI4_IRQHandler          [WEAK]
+                EXPORT  DMAChannel1_IRQHandler    [WEAK]
+                EXPORT  DMAChannel2_IRQHandler    [WEAK]
+                EXPORT  DMAChannel3_IRQHandler    [WEAK]
+                EXPORT  DMAChannel4_IRQHandler    [WEAK]
+                EXPORT  DMAChannel5_IRQHandler    [WEAK]
+                EXPORT  DMAChannel6_IRQHandler    [WEAK]
+                EXPORT  DMAChannel7_IRQHandler    [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  USB_HP_CAN_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN_RX0_IRQHandler [WEAK]
+                EXPORT  CAN_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler        [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM1_UP_IRQHandler        [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM1_CC_IRQHandler        [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  TIM3_IRQHandler           [WEAK]
+                EXPORT  TIM4_IRQHandler           [WEAK]
+                EXPORT  I2C1_EV_IRQHandler        [WEAK]
+                EXPORT  I2C1_ER_IRQHandler        [WEAK]
+                EXPORT  I2C2_EV_IRQHandler        [WEAK]
+                EXPORT  I2C2_ER_IRQHandler        [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  SPI2_IRQHandler           [WEAK]
+                EXPORT  USART1_IRQHandler         [WEAK]
+                EXPORT  USART2_IRQHandler         [WEAK]
+                EXPORT  USART3_IRQHandler         [WEAK]
+                EXPORT  EXTI15_10_IRQHandler      [WEAK]
+                EXPORT  RTCAlarm_IRQHandler       [WEAK]
+                EXPORT  USBWakeUp_IRQHandler      [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMAChannel1_IRQHandler
+DMAChannel2_IRQHandler
+DMAChannel3_IRQHandler
+DMAChannel4_IRQHandler
+DMAChannel5_IRQHandler
+DMAChannel6_IRQHandler
+DMAChannel7_IRQHandler
+ADC_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/Demo/CORTEX_STM32F103_Keil/main.c b/Demo/CORTEX_STM32F103_Keil/main.c
new file mode 100644
index 000000000..dfbf6ba6a
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/main.c
@@ -0,0 +1,456 @@
+/*
+	FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *
+    * and even write all or part of your application on your behalf.          *
+    * See http://www.OpenRTOS.com for details of the services we provide to   *
+    * expedite your project.                                                  *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and 
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety 
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting, 
+	licensing and training services.
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the standard demo application tasks.
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated
+ * using a free running timer to demonstrate the use of the
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant.  The interrupt
+ * service routine measures the number of processor clocks that occur between
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and
+ * displayed on the LCD by the 'Check' task as described below.  The
+ * fast interrupt is configured and handled in the timertest.c source file.
+ *
+ * "LCD" task - the LCD task is a 'gatekeeper' task.  It is the only task that
+ * is permitted to access the display directly.  Other tasks wishing to write a
+ * message to the LCD send the message on a queue to the LCD task instead of
+ * accessing the LCD themselves.  The LCD task just blocks on the queue waiting
+ * for messages - waking and displaying the messages as they arrive.
+ *
+ * "Check" task -  This only executes every five seconds but has the highest
+ * priority so is guaranteed to get processor time.  Its main function is to
+ * check that all the standard demo tasks are still operational.  Should any
+ * unexpected behaviour within a demo task be discovered the 'check' task will
+ * write an error to the LCD (via the LCD task).  If all the demo tasks are
+ * executing with their expected behaviour then the check task writes PASS
+ * along with the max jitter time to the LCD (again via the LCD task), as
+ * described above.
+ *
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Library includes. */
+#include "stm32f10x_it.h"
+
+/* Demo app includes. */
+#include "lcd.h"
+#include "LCD_Message.h"
+#include "BlockQ.h"
+#include "death.h"
+#include "integer.h"
+#include "blocktim.h"
+#include "partest.h"
+#include "semtest.h"
+#include "PollQ.h"
+#include "flash.h"
+#include "comtest2.h"
+
+/* Task priorities. */
+#define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY				( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY				( tskIDLE_PRIORITY + 2 )
+#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 3 )
+#define mainFLASH_TASK_PRIORITY				( tskIDLE_PRIORITY + 1 )
+#define mainCOM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1 )
+#define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )
+
+/* Constants related to the LCD. */
+#define mainMAX_LINE						( 240 )
+#define mainROW_INCREMENT					( 24 )
+#define mainMAX_COLUMN						( 20 )
+#define mainCOLUMN_START					( 319 )
+#define mainCOLUMN_INCREMENT 				( 16 )
+
+/* The maximum number of message that can be waiting for display at any one
+time. */
+#define mainLCD_QUEUE_SIZE					( 3 )
+
+/* The check task uses the sprintf function so requires a little more stack. */
+#define mainCHECK_TASK_STACK_SIZE			( configMINIMAL_STACK_SIZE + 50 )
+
+/* Dimensions the buffer into which the jitter time is written. */
+#define mainMAX_MSG_LEN						25
+
+/* The time between cycles of the 'check' task. */
+#define mainCHECK_DELAY						( ( portTickType ) 5000 / portTICK_RATE_MS )
+
+/* The number of nano seconds between each processor clock. */
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )
+
+/* Baud rate used by the comtest tasks. */
+#define mainCOM_TEST_BAUD_RATE		( 115200 )
+
+/* The LED used by the comtest tasks. See the comtest.c file for more
+information. */
+#define mainCOM_TEST_LED			( 3 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Configure the clocks, GPIO and other peripherals as required by the demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * Configure the LCD as required by the demo.
+ */
+static void prvConfigureLCD( void );
+
+/*
+ * The LCD is written two by more than one task so is controlled by a
+ * 'gatekeeper' task.  This is the only task that is actually permitted to
+ * access the LCD directly.  Other tasks wanting to display a message send
+ * the message to the gatekeeper.
+ */
+static void vLCDTask( void *pvParameters );
+
+/*
+ * Retargets the C library printf function to the USART.
+ */
+int fputc( int ch, FILE *f );
+
+/*
+ * Checks the status of all the demo tasks then prints a message to the
+ * display.  The message will be either PASS - and include in brackets the
+ * maximum measured jitter time (as described at the to of the file), or a
+ * message that describes which of the standard demo tasks an error has been
+ * discovered in.
+ *
+ * Messages are not written directly to the terminal, but passed to vLCDTask
+ * via a queue.
+ */
+static void vCheckTask( void *pvParameters );
+
+/*
+ * Configures the timers and interrupts for the fast interrupt test as
+ * described at the top of this file.
+ */
+extern void vSetupTimerTest( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used to send messages to the LCD task. */
+xQueueHandle xLCDQueue;
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+#ifdef DEBUG
+  debug();
+#endif
+
+	prvSetupHardware();
+
+	/* Create the queue used by the LCD task.  Messages for display on the LCD
+	are received via this queue. */
+	xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) );
+	
+	/* Start the standard demo tasks. */
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+    vCreateBlockTimeTasks();
+    vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+    vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+    vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );
+	vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+
+	/* Start the tasks defined within this file/specific to this demo. */
+    xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+	xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	/* The suicide tasks must be created last as they need to know how many
+	tasks were running prior to their creation in order to ascertain whether
+	or not the correct/expected number of tasks are running at any given time. */
+    vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+	
+	/* Configure the timers used by the fast interrupt timer test. */
+	vSetupTimerTest();
+	
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+	
+	/* Will only get here if there was not enough heap space to create the
+	idle task. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vLCDTask( void *pvParameters )
+{
+xLCDMessage xMessage;
+
+	/* Initialise the LCD and display a startup message. */
+	prvConfigureLCD();
+	LCD_DrawMonoPict( ( unsigned portLONG * ) pcBitmap );
+
+	for( ;; )
+	{
+		/* Wait for a message to arrive that requires displaying. */
+		while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS );
+
+		/* Display the message.  Print each message to a different position. */
+		printf( ( portCHAR const * ) xMessage.pcMessage );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCheckTask( void *pvParameters )
+{
+portTickType xLastExecutionTime;
+xLCDMessage xMessage;
+static signed portCHAR cPassMessage[ mainMAX_MSG_LEN ];
+extern unsigned portSHORT usMaxJitter;
+
+	xLastExecutionTime = xTaskGetTickCount();
+	xMessage.pcMessage = cPassMessage;
+	
+    for( ;; )
+	{
+		/* Perform this check every mainCHECK_DELAY milliseconds. */
+		vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );
+
+		/* Has an error been found in any task? */
+
+        if( xAreBlockingQueuesStillRunning() != pdTRUE )
+		{
+			xMessage.pcMessage = "ERROR IN BLOCK Q\n";
+		}
+		else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+		{
+			xMessage.pcMessage = "ERROR IN BLOCK TIME\n";
+		}
+        else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+        {
+            xMessage.pcMessage = "ERROR IN SEMAPHORE\n";
+        }
+        else if( xArePollingQueuesStillRunning() != pdTRUE )
+        {
+            xMessage.pcMessage = "ERROR IN POLL Q\n";
+        }
+        else if( xIsCreateTaskStillRunning() != pdTRUE )
+        {
+            xMessage.pcMessage = "ERROR IN CREATE\n";
+        }
+        else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+        {
+            xMessage.pcMessage = "ERROR IN MATH\n";
+        }
+		else if( xAreComTestTasksStillRunning() != pdTRUE )
+		{
+			xMessage.pcMessage = "ERROR IN COM TEST\n";
+		}				
+		else
+		{
+			sprintf( ( portCHAR * ) cPassMessage, "PASS [%uns]\n", ( ( unsigned portLONG ) usMaxJitter ) * mainNS_PER_CLOCK );
+		}
+
+		/* Send the message to the LCD gatekeeper for display. */
+		xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Start with the clocks in their expected state. */
+	RCC_DeInit();
+
+	/* Enable HSE (high speed external clock). */
+	RCC_HSEConfig( RCC_HSE_ON );
+
+	/* Wait till HSE is ready. */
+	while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET )
+	{
+	}
+
+	/* 2 wait states required on the flash. */
+	*( ( unsigned portLONG * ) 0x40022000 ) = 0x02;
+
+	/* HCLK = SYSCLK */
+	RCC_HCLKConfig( RCC_SYSCLK_Div1 );
+
+	/* PCLK2 = HCLK */
+	RCC_PCLK2Config( RCC_HCLK_Div1 );
+
+	/* PCLK1 = HCLK/2 */
+	RCC_PCLK1Config( RCC_HCLK_Div2 );
+
+	/* PLLCLK = 8MHz * 9 = 72 MHz. */
+	RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_9 );
+
+	/* Enable PLL. */
+	RCC_PLLCmd( ENABLE );
+
+	/* Wait till PLL is ready. */
+	while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+	{
+	}
+
+	/* Select PLL as system clock source. */
+	RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK );
+
+	/* Wait till PLL is used as system clock source. */
+	while( RCC_GetSYSCLKSource() != 0x08 )
+	{
+	}
+
+	/* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */
+	RCC_APB2PeriphClockCmd(	RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC
+							| RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE );
+
+	/* SPI2 Periph clock enable */
+	RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );
+
+
+	/* Set the Vector Table base address at 0x08000000 */
+	NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 );
+
+	NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );
+	
+	/* Configure HCLK clock as SysTick clock source. */
+	SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK );
+	
+	vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+static void prvConfigureLCD( void )
+{
+GPIO_InitTypeDef GPIO_InitStructure;
+
+	/* Configure LCD Back Light (PA8) as output push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_Init( GPIOA, &GPIO_InitStructure );
+
+	/* Set the Backlight Pin */
+	GPIO_WriteBit(GPIOA, GPIO_Pin_8, Bit_SET);
+
+	/* Initialize the LCD */
+	LCD_Init();
+
+	/* Set the Back Color */
+	LCD_SetBackColor( White );
+
+	/* Set the Text Color */
+	LCD_SetTextColor( 0x051F );
+
+	LCD_Clear();
+}
+/*-----------------------------------------------------------*/
+
+int fputc( int ch, FILE *f )
+{
+static unsigned portSHORT usColumn = 0, usRefColumn = mainCOLUMN_START;
+static unsigned portCHAR ucLine = 0;
+
+	if( ( usColumn == 0 ) && ( ucLine == 0 ) )
+	{
+		LCD_Clear();
+	}
+
+	if( ch != '\n' )
+	{
+		/* Display one character on LCD */
+		LCD_DisplayChar( ucLine, usRefColumn, (u8) ch );
+		
+		/* Decrement the column position by 16 */
+		usRefColumn -= mainCOLUMN_INCREMENT;
+		
+		/* Increment the character counter */
+		usColumn++;
+		if( usColumn == mainMAX_COLUMN )
+		{
+			ucLine += mainROW_INCREMENT;
+			usRefColumn = mainCOLUMN_START;
+			usColumn = 0;
+		}
+	}
+	else
+	{
+		/* Move back to the first column of the next line. */
+		ucLine += mainROW_INCREMENT;
+		usRefColumn = mainCOLUMN_START;
+		usColumn = 0;	
+	}
+
+	/* Wrap back to the top of the display. */
+	if( ucLine >= mainMAX_LINE )
+	{
+		ucLine = 0;
+	}
+	
+	return ch;
+}
+/*-----------------------------------------------------------*/
+
+#ifdef  DEBUG
+/* Keep the linker happy. */
+void assert_failed( unsigned portCHAR* pcFile, unsigned portLONG ulLine )
+{
+	for( ;; )
+	{
+	}
+}
+#endif
diff --git a/Demo/CORTEX_STM32F103_Keil/serial/serial.c b/Demo/CORTEX_STM32F103_Keil/serial/serial.c
new file mode 100644
index 000000000..af6100ef3
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/serial/serial.c
@@ -0,0 +1,250 @@
+/*
+	FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *
+    * and even write all or part of your application on your behalf.          *
+    * See http://www.OpenRTOS.com for details of the services we provide to   *
+    * expedite your project.                                                  *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and 
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety 
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting, 
+	licensing and training services.
+*/
+
+/*
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Library includes. */
+#include "stm32f10x_lib.h"
+
+/* Demo application includes. */
+#include "serial.h"
+/*-----------------------------------------------------------*/
+
+/* Misc defines. */
+#define serINVALID_QUEUE				( ( xQueueHandle ) 0 )
+#define serNO_BLOCK						( ( portTickType ) 0 )
+#define serTX_BLOCK_TIME				( 40 / portTICK_RATE_MS )
+
+/*-----------------------------------------------------------*/
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+/*-----------------------------------------------------------*/
+
+/* UART interrupt handler. */
+void vUARTInterruptHandler( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See the serial2.h header file.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+xComPortHandle xReturn;
+USART_InitTypeDef USART_InitStructure;
+NVIC_InitTypeDef NVIC_InitStructure;
+GPIO_InitTypeDef GPIO_InitStructure;
+
+	/* Create the queues used to hold Rx/Tx characters. */
+	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	
+	/* If the queue/semaphore was created correctly then setup the serial port
+	hardware. */
+	if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
+	{
+		/* Enable USART1 clock */
+		RCC_APB2PeriphClockCmd( RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE );	
+
+		/* Configure USART1 Rx (PA10) as input floating */
+		GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+		GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+		GPIO_Init( GPIOA, &GPIO_InitStructure );
+		
+		/* Configure USART1 Tx (PA9) as alternate function push-pull */
+		GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+		GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+		GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+		GPIO_Init( GPIOA, &GPIO_InitStructure );
+
+		USART_InitStructure.USART_BaudRate = ulWantedBaud;
+		USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+		USART_InitStructure.USART_StopBits = USART_StopBits_1;
+		USART_InitStructure.USART_Parity = USART_Parity_No ;
+		USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+		USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+		USART_InitStructure.USART_Clock = USART_Clock_Disable;
+		USART_InitStructure.USART_CPOL = USART_CPOL_Low;
+		USART_InitStructure.USART_CPHA = USART_CPHA_2Edge;
+		USART_InitStructure.USART_LastBit = USART_LastBit_Disable;
+		
+		USART_Init( USART1, &USART_InitStructure );
+		
+		USART_ITConfig( USART1, USART_IT_RXNE, ENABLE );
+		
+		NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel;
+		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
+		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+		NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+		NVIC_Init( &NVIC_InitStructure );
+		
+		USART_Cmd( USART1, ENABLE );		
+	}
+	else
+	{
+		xReturn = ( xComPortHandle ) 0;
+	}
+
+	/* This demo file only supports a single port but we have to return
+	something to comply with the standard demo header file. */
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* The port handle is not required as this driver only supports one port. */
+	( void ) pxPort;
+
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+	/* A couple of parameters that this port does not use. */
+	( void ) usStringLength;
+	( void ) pxPort;
+
+	/* NOTE: This implementation does not handle the queue being full as no
+	block time is used! */
+
+	/* The port handle is not required as this driver only supports UART1. */
+	( void ) pxPort;
+
+	/* Send each character in the string, one at a time. */
+	pxNext = ( signed portCHAR * ) pcString;
+	while( *pxNext )
+	{
+		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+		pxNext++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
+	{
+		xReturn = pdPASS;
+		USART_ITConfig( USART1, USART_IT_TXE, ENABLE );
+	}
+	else
+	{
+		xReturn = pdFAIL;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+	/* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+void vUARTInterruptHandler( void )
+{
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+portCHAR cChar;
+
+	if( USART_GetITStatus( USART1, USART_IT_TXE ) == SET )
+	{
+		/* The interrupt was caused by the THR becoming empty.  Are there any
+		more characters to transmit? */
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
+		{
+			/* A character was retrieved from the queue so can be sent to the
+			THR now. */
+			USART_SendData( USART1, cChar );
+		}
+		else
+		{
+			USART_ITConfig( USART1, USART_IT_TXE, DISABLE );		
+		}		
+	}
+	
+	if( USART_GetITStatus( USART1, USART_IT_RXNE ) == SET )
+	{
+		cChar = USART_ReceiveData( USART1 );
+		xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
+	}	
+	
+	portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+
+
+
+
+
+	
diff --git a/Demo/CORTEX_STM32F103_Keil/spi_flash.c b/Demo/CORTEX_STM32F103_Keil/spi_flash.c
new file mode 100644
index 000000000..b96cbff6e
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/spi_flash.c
@@ -0,0 +1,498 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : spi_flash.c
+* Author             : MCD Application Team
+* Date First Issued  : 02/05/2007
+* Description        : This file provides a set of functions needed to manage the
+*                      communication between SPI peripheral and SPI M25P64 FLASH.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "spi_flash.h"
+
+/* Private typedef -----------------------------------------------------------*/
+#define SPI_FLASH_PageSize 256
+
+#define WRITE      0x02  /* Write to Memory instruction */
+#define WRSR       0x01  /* Write Status Register instruction */ 
+#define WREN       0x06  /* Write enable instruction */
+
+#define READ       0x03  /* Read from Memory instruction */
+#define RDSR       0x05  /* Read Status Register instruction  */
+#define RDID       0x9F  /* Read identification */
+#define SE         0xD8  /* Sector Erase instruction */
+#define BE         0xC7  /* Bulk Erase instruction */
+
+#define WIP_Flag   0x01  /* Write In Progress (WIP) flag */
+
+#define Dummy_Byte 0xA5
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_Init
+* Description    : Initializes the peripherals used by the SPI FLASH driver.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_Init(void)
+{
+  SPI_InitTypeDef  SPI_InitStructure;
+  GPIO_InitTypeDef GPIO_InitStructure;
+   
+  /* Enable SPI1 and GPIOA clocks */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1 | RCC_APB2Periph_GPIOA, ENABLE);
+  
+  /* Configure SPI1 pins: NSS, SCK, MISO and MOSI */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* Configure PA.4 as Output push-pull, used as Flash Chip select */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);
+
+  /* SPI1 configuration */ 
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(SPI1, &SPI_InitStructure);
+  
+  /* Enable SPI1  */
+  SPI_Cmd(SPI1, ENABLE);   
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_SectorErase
+* Description    : Erases the specified FLASH sector.
+* Input          : SectorAddr: address of the sector to erase.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_SectorErase(u32 SectorAddr)
+{
+  /* Send write enable instruction */
+  SPI_FLASH_WriteEnable();
+			
+  /* Sector Erase */ 
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);		
+  /* Send Sector Erase instruction  */
+  SPI_FLASH_SendByte(SE);
+  /* Send SectorAddr high nibble address byte */
+  SPI_FLASH_SendByte((SectorAddr & 0xFF0000) >> 16);
+  /* Send SectorAddr medium nibble address byte */
+  SPI_FLASH_SendByte((SectorAddr & 0xFF00) >> 8);
+  /* Send SectorAddr low nibble address byte */
+  SPI_FLASH_SendByte(SectorAddr & 0xFF);
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);	
+
+  /* Wait the end of Flash writing */
+  SPI_FLASH_WaitForWriteEnd();	
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_BulkErase
+* Description    : Erases the entire FLASH.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_BulkErase(void)
+{ 	
+  /* Send write enable instruction */
+  SPI_FLASH_WriteEnable();	
+	
+  /* Bulk Erase */ 
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);		
+  /* Send Bulk Erase instruction  */
+  SPI_FLASH_SendByte(BE);
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);	
+		
+  /* Wait the end of Flash writing */
+  SPI_FLASH_WaitForWriteEnd();		
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_PageWrite
+* Description    : Writes more than one byte to the FLASH with a single WRITE
+*                  cycle(Page WRITE sequence). The number of byte can't exceed
+*                  the FLASH page size.
+* Input          : - pBuffer : pointer to the buffer  containing the data to be 
+*                    written to the FLASH.
+*                  - WriteAddr : FLASH's internal address to write to.
+*                  - NumByteToWrite : number of bytes to write to the FLASH,
+*                    must be equal or less than "SPI_FLASH_PageSize" value. 
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite)
+{
+  /* Enable the write access to the FLASH */
+  SPI_FLASH_WriteEnable();		
+  
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);	   
+  /* Send "Write to Memory " instruction */    
+  SPI_FLASH_SendByte(WRITE);	
+  /* Send WriteAddr high nibble address byte to write to */
+  SPI_FLASH_SendByte((WriteAddr & 0xFF0000) >> 16);
+  /* Send WriteAddr medium nibble address byte to write to */
+  SPI_FLASH_SendByte((WriteAddr & 0xFF00) >> 8);  
+  /* Send WriteAddr low nibble address byte to write to */
+  SPI_FLASH_SendByte(WriteAddr & 0xFF);             
+  
+  /* while there is data to be written on the FLASH */
+  while(NumByteToWrite--) 
+  {
+    /* Send the current byte */			
+    SPI_FLASH_SendByte(*pBuffer); 	               
+    /* Point on the next byte to be written */
+    pBuffer++; 
+  }		
+  
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);
+  
+  /* Wait the end of Flash writing */
+  SPI_FLASH_WaitForWriteEnd();	
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_BufferWrite
+* Description    : Writes block of data to the FLASH. In this function, the
+*                  number of WRITE cycles are reduced, using Page WRITE sequence.
+* Input          : - pBuffer : pointer to the buffer  containing the data to be 
+*                    written to the FLASH.
+*                  - WriteAddr : FLASH's internal address to write to.
+*                  - NumByteToWrite : number of bytes to write to the FLASH.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite)
+{
+  u8 NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
+
+  Addr = WriteAddr % SPI_FLASH_PageSize;
+  count = SPI_FLASH_PageSize - Addr;
+  NumOfPage =  NumByteToWrite / SPI_FLASH_PageSize;
+  NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize;
+  
+  if(Addr == 0) /* WriteAddr is SPI_FLASH_PageSize aligned  */
+  {
+    if(NumOfPage == 0) /* NumByteToWrite < SPI_FLASH_PageSize */
+    {
+      SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite);
+    }
+    else /* NumByteToWrite > SPI_FLASH_PageSize */ 
+    {
+      while(NumOfPage--)
+      {
+        SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize);
+        WriteAddr +=  SPI_FLASH_PageSize;
+        pBuffer += SPI_FLASH_PageSize;  
+      }    
+     
+      SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle);      
+   }
+  }
+  else /* WriteAddr is not SPI_FLASH_PageSize aligned  */
+  {
+    if(NumOfPage== 0) /* NumByteToWrite < SPI_FLASH_PageSize */
+    {
+      if(NumOfSingle > count) /* (NumByteToWrite + WriteAddr) > SPI_FLASH_PageSize */
+      {
+      	temp = NumOfSingle - count;
+      	
+      	SPI_FLASH_PageWrite(pBuffer, WriteAddr, count);
+        WriteAddr +=  count;
+        pBuffer += count; 
+        
+        SPI_FLASH_PageWrite(pBuffer, WriteAddr, temp);       	
+      }
+      else
+      {
+      	SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite);
+      }
+    }
+    else /* NumByteToWrite > SPI_FLASH_PageSize */
+    {
+      NumByteToWrite -= count;
+      NumOfPage =  NumByteToWrite / SPI_FLASH_PageSize;
+      NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize;	
+      
+      SPI_FLASH_PageWrite(pBuffer, WriteAddr, count);
+      WriteAddr +=  count;
+      pBuffer += count;  
+     
+      while(NumOfPage--)
+      {
+        SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize);
+        WriteAddr +=  SPI_FLASH_PageSize;
+        pBuffer += SPI_FLASH_PageSize;  
+      }
+      
+      if(NumOfSingle != 0)
+      {
+        SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle);
+      }
+    }
+  }      	
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_BufferRead
+* Description    : Reads a block of data from the FLASH.
+* Input          : - pBuffer : pointer to the buffer that receives the data read 
+*                    from the FLASH.
+*                  - ReadAddr : FLASH's internal address to read from.
+*                  - NumByteToRead : number of bytes to read from the FLASH.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead)
+{
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);	   
+  
+  /* Send "Read from Memory " instruction */
+  SPI_FLASH_SendByte(READ);	 
+  
+  /* Send ReadAddr high nibble address byte to read from */
+  SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
+  /* Send ReadAddr medium nibble address byte to read from */
+  SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8);  
+  /* Send ReadAddr low nibble address byte to read from */
+  SPI_FLASH_SendByte(ReadAddr & 0xFF);     
+   	
+  while(NumByteToRead--) /* while there is data to be read */
+  {
+    /* Read a byte from the FLASH */			
+    *pBuffer = SPI_FLASH_SendByte(Dummy_Byte);   
+    /* Point to the next location where the byte read will be saved */
+    pBuffer++;
+  }	
+  
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);		
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_ReadID
+* Description    : Reads FLASH identification.
+* Input          : None
+* Output         : None
+* Return         : FLASH identification
+*******************************************************************************/
+u32 SPI_FLASH_ReadID(void)
+{   	 
+  u32 Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
+
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);	   
+  
+  /* Send "RDID " instruction */
+  SPI_FLASH_SendByte(0x9F);
+
+  /* Read a byte from the FLASH */			
+  Temp0 = SPI_FLASH_SendByte(Dummy_Byte);
+
+  /* Read a byte from the FLASH */			
+  Temp1 = SPI_FLASH_SendByte(Dummy_Byte);
+
+  /* Read a byte from the FLASH */			
+  Temp2 = SPI_FLASH_SendByte(Dummy_Byte);
+
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);
+         
+  Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
+
+  return Temp;
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_StartReadSequence
+* Description    : Initiates a read data byte (READ) sequence from the Flash.
+*                  This is done by driving the /CS line low to select the device,
+*                  then the READ instruction is transmitted followed by 3 bytes
+*                  address. This function exit and keep the /CS line low, so the
+*                  Flash still being selected. With this technique the whole
+*                  content of the Flash is read with a single READ instruction.
+* Input          : - ReadAddr : FLASH's internal address to read from.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_StartReadSequence(u32 ReadAddr)
+{
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);	   
+  
+  /* Send "Read from Memory " instruction */
+  SPI_FLASH_SendByte(READ);	 
+
+/* Send the 24-bit address of the address to read from -----------------------*/  
+  /* Send ReadAddr high nibble address byte */
+  SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
+  /* Send ReadAddr medium nibble address byte */
+  SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8);  
+  /* Send ReadAddr low nibble address byte */
+  SPI_FLASH_SendByte(ReadAddr & 0xFF);  
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_ReadByte
+* Description    : Reads a byte from the SPI Flash.
+*                  This function must be used only if the Start_Read_Sequence
+*                  function has been previously called.
+* Input          : None
+* Output         : None
+* Return         : Byte Read from the SPI Flash.
+*******************************************************************************/
+u8 SPI_FLASH_ReadByte(void)
+{
+  return (SPI_FLASH_SendByte(Dummy_Byte));
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_ChipSelect
+* Description    : Selects or deselects the FLASH.
+* Input          : State : level to be applied on the FLASH's ChipSelect pin.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_ChipSelect(u8 State)
+{
+  /* Set High or low the chip select line on PA.4 pin */
+  GPIO_WriteBit(GPIOA, GPIO_Pin_4, (BitAction)State);
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_SendByte
+* Description    : Sends a byte through the SPI interface and return the byte 
+*                  received from the SPI bus.
+* Input          : byte : byte to send.
+* Output         : None
+* Return         : The value of the received byte.
+*******************************************************************************/
+u8 SPI_FLASH_SendByte(u8 byte)
+{
+  /* Loop while DR register in not emplty */
+  while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET); 
+
+  /* Send byte through the SPI1 peripheral */	
+  SPI_SendData(SPI1, byte);	
+
+  /* Wait to receive a byte */
+  while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET);
+
+  /* Return the byte read from the SPI bus */  
+  return SPI_ReceiveData(SPI1); 
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_SendHalfWord
+* Description    : Sends a Half Word through the SPI interface and return the  
+*                  Half Word received from the SPI bus.
+* Input          : Half Word : Half Word to send.
+* Output         : None
+* Return         : The value of the received Half Word.
+*******************************************************************************/
+u16 SPI_FLASH_SendHalfWord(u16 HalfWord)
+{
+  /* Loop while DR register in not emplty */
+  while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET); 
+
+  /* Send Half Word through the SPI1 peripheral */	
+  SPI_SendData(SPI1, HalfWord);	
+
+  /* Wait to receive a Half Word */
+  while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET);
+
+  /* Return the Half Word read from the SPI bus */  
+  return SPI_ReceiveData(SPI1); 
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_WriteEnable
+* Description    : Enables the write access to the FLASH.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_WriteEnable(void)  
+{
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);	
+  
+  /* Send "Write Enable" instruction */
+  SPI_FLASH_SendByte(WREN);
+  
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);	
+}
+
+/*******************************************************************************
+* Function Name  : SPI_FLASH_WaitForWriteEnd
+* Description    : Polls the status of the Write In Progress (WIP) flag in the  
+*                  FLASH's status  register  and  loop  until write  opertaion
+*                  has completed.  
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI_FLASH_WaitForWriteEnd(void) 
+{
+  u8 FLASH_Status = 0;
+  
+  /* Select the FLASH: Chip Select low */
+  SPI_FLASH_ChipSelect(Low);
+  	
+  /* Send "Read Status Register" instruction */
+  SPI_FLASH_SendByte(RDSR);
+  
+  /* Loop as long as the memory is busy with a write cycle */ 		
+  do
+  { 	
+	 
+    /* Send a dummy byte to generate the clock needed by the FLASH 
+    and put the value of the status register in FLASH_Status variable */
+    FLASH_Status = SPI_FLASH_SendByte(Dummy_Byte);  
+																	
+  } while((FLASH_Status & WIP_Flag) == SET); /* Write in progress */  
+
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(High);	 	
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/stm32f10x_conf.h b/Demo/CORTEX_STM32F103_Keil/stm32f10x_conf.h
new file mode 100644
index 000000000..5537c251d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/stm32f10x_conf.h
@@ -0,0 +1,137 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_conf.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : Library configuration file.
+********************************************************************************
+* History:
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Comment the line below to compile the library in release mode */
+//#define DEBUG
+
+/* Comment the line below to disable the specific peripheral inclusion */
+/************************************* ADC ************************************/
+//#define _ADC
+//#define _ADC1
+//#define _ADC2
+
+/************************************* CAN ************************************/
+//#define _CAN
+
+/************************************* DMA ************************************/
+//#define _DMA
+//#define _DMA_Channel1
+//#define _DMA_Channel2
+//#define _DMA_Channel3
+//#define _DMA_Channel4
+//#define _DMA_Channel5
+//#define _DMA_Channel6
+//#define _DMA_Channel7
+
+/************************************* EXTI ***********************************/
+#define _EXTI
+
+/************************************* GPIO ***********************************/
+#define _GPIO
+#define _GPIOA
+#define _GPIOB
+#define _GPIOC
+#define _GPIOD
+#define _GPIOE
+#define _AFIO
+
+/************************************* I2C ************************************/
+//#define _I2C
+//#define _I2C1
+//#define _I2C2
+
+/************************************* IWDG ***********************************/
+//#define _IWDG
+
+/************************************* NVIC ***********************************/
+#define _NVIC
+#define _SCB
+
+/************************************* BKP ************************************/
+//#define _BKP
+
+/************************************* PWR ************************************/
+//#define _PWR
+
+/************************************* RCC ************************************/
+#define _RCC
+
+/************************************* RTC ************************************/
+//#define _RTC
+
+/************************************* SPI ************************************/
+#define _SPI
+#define _SPI1
+#define _SPI2
+
+/************************************* SysTick ********************************/
+#define _SysTick
+
+/************************************* TIM ************************************/
+//#define _TIM
+#define _TIM2
+#define _TIM3
+//#define _TIM4
+
+/************************************* USART **********************************/
+#define _USART
+#define _USART1
+//#define _USART2
+//#define _USART3
+
+/************************************* WWDG ***********************************/
+//#define _WWDG
+
+/* In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application */
+#define HSE_Value    ((u32)8000000)   /* Value of the External oscillator in Hz*/
+
+/* Exported macro ------------------------------------------------------------*/
+#undef assert
+#ifdef  DEBUG
+/*******************************************************************************
+* Macro Name     : assert
+* Description    : The assert macro is used for function's parameters check.
+*                  It is used only if the library is compiled in DEBUG mode.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed.
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/
+  #define assert(expr) ((expr) ? (void)0 : assert_failed(__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(u8* file, u32 line);
+#else
+  #define assert(expr) ((void)0)
+#endif /* DEBUG */
+
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/timertest.c b/Demo/CORTEX_STM32F103_Keil/timertest.c
new file mode 100644
index 000000000..fcc8fefed
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/timertest.c
@@ -0,0 +1,183 @@
+/*
+	FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *
+    * and even write all or part of your application on your behalf.          *
+    * See http://www.OpenRTOS.com for details of the services we provide to   *
+    * expedite your project.                                                  *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and 
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety 
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting, 
+	licensing and training services.
+*/
+
+/* High speed timer test as described in main.c. */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Library includes. */
+#include "stm32f10x_lib.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_map.h"
+
+/* The set frequency of the interrupt.  Deviations from this are measured as
+the jitter. */
+#define timerINTERRUPT_FREQUENCY		( ( unsigned portSHORT ) 20000 )
+
+/* The expected time between each of the timer interrupts - if the jitter was
+zero. */
+#define timerEXPECTED_DIFFERENCE_VALUE	( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )
+
+/* The highest available interrupt priority. */
+#define timerHIGHEST_PRIORITY			( 0 )
+
+/* Misc defines. */
+#define timerMAX_32BIT_VALUE			( 0xffffffffUL )
+#define timerTIMER_1_COUNT_VALUE		( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )
+
+/* The number of interrupts to pass before we start looking at the jitter. */
+#define timerSETTLE_TIME			5
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Configures the two timers used to perform the test.
+ */
+void vSetupTimerTest( void );
+
+/* Interrupt handler in which the jitter is measured. */
+void vTimer2IntHandler( void );
+
+/* Stores the value of the maximum recorded jitter between interrupts. */
+volatile unsigned portSHORT usMaxJitter = 0;
+
+/*-----------------------------------------------------------*/
+
+void vSetupTimerTest( void )
+{
+unsigned long ulFrequency;
+TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+NVIC_InitTypeDef NVIC_InitStructure;
+
+
+	/* Enable timer clocks */
+	RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
+	RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE );
+
+	/* Initialise data. */
+	TIM_DeInit( TIM2 );
+	TIM_DeInit( TIM3 );
+	TIM_TimeBaseStructInit( &TIM_TimeBaseStructure );
+
+	/* Time base configuration for timer 2 - which generates the interrupts. */
+	ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY;	
+	TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) ( ulFrequency & 0xffffUL );
+	TIM_TimeBaseStructure.TIM_Prescaler = 0x0;
+	TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
+	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+	TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure );
+	TIM_ARRPreloadConfig( TIM2, ENABLE );
+
+	
+	/* Configuration for timer 3 which is used as a high resolution time
+	measurement. */
+	TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) 0xffff;
+	TIM_TimeBaseInit( TIM3, &TIM_TimeBaseStructure );
+	TIM_ARRPreloadConfig( TIM3, ENABLE );
+	
+	/* Enable TIM2 IT.  TIM3 does not generate an interrupt. */
+	NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = timerHIGHEST_PRIORITY;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init( &NVIC_InitStructure );	
+	TIM_ITConfig( TIM2, TIM_IT_Update, ENABLE );
+
+	/* Finally, enable both timers. */
+	TIM_Cmd( TIM2, ENABLE );
+	TIM_Cmd( TIM3, ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+void vTimer2IntHandler( void )
+{
+static unsigned portSHORT usLastCount = 0, usSettleCount = 0, usMaxDifference = 0;
+unsigned portSHORT usThisCount, usDifference;
+
+	/* Capture the free running timer 3 value as we enter the interrupt. */
+	usThisCount = TIM3->CNT;
+	
+	if( usSettleCount >= timerSETTLE_TIME )
+	{
+		/* What is the difference between the timer value in this interrupt
+		and the value from the last interrupt. */
+		usDifference = usThisCount - usLastCount;
+
+		/* Store the difference in the timer values if it is larger than the
+		currently stored largest value.  The difference over and above the
+		expected difference will give the 'jitter' in the processing of these
+		interrupts. */
+		if( usDifference > usMaxDifference )
+		{
+			usMaxDifference = usDifference;
+			usMaxJitter = usMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;
+		}
+	}
+	else
+	{
+		/* Don't bother storing any values for the first couple of
+		interrupts. */
+		usSettleCount++;
+	}
+
+	/* Remember what the timer value was this time through, so we can calculate
+	the difference the next time through. */
+	usLastCount = usThisCount;
+
+    TIM_ClearITPendingBit( TIM2, TIM_IT_Update );
+}
+
+
+
+
+
+
+
+
-- 
2.39.5