From fd6986168a5e9f33b8dba628b9d9e42196c02923 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 5 Oct 2017 15:44:58 +0200 Subject: [PATCH] pipistrello: decrease jtag speed to 10 MHz 30 MHz is not working reliably here Change-Id: I38f5f8c7153fc64e313ee911b1629fb5f1114c39 Signed-off-by: Robert Jordens Reviewed-on: http://openocd.zylin.com/4242 Tested-by: jenkins Reviewed-by: Tomas Vanek --- tcl/interface/ftdi/pipistrello.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg index b51405a2..5ee5be5b 100644 --- a/tcl/interface/ftdi/pipistrello.cfg +++ b/tcl/interface/ftdi/pipistrello.cfg @@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b reset_config none # this generally works fast: the fpga can handle 30MHz, the spi flash can handle # 54MHz with simple read, no dummy cycles, and wait-for-write-completion -adapter_khz 30000 +adapter_khz 10000 -- 2.39.5