From fed713104904bfc4884e748ef4160be4ab7e4575 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 12 Jan 2016 10:46:07 +0100 Subject: [PATCH] armv4_5: support weirdo ARMv6 secure monitor mode On the ARM PB1176JZF-S the system comes up in secure monitor mode after reset. However the modebits in CPSR form the value 28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED. Define this mode to be synonymous to mode 22 (MON) and things start to work like a charm. Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413 Cc: Will Deacon Signed-off-by: Linus Walleij Reviewed-on: http://openocd.zylin.com/3196 Tested-by: jenkins Reviewed-by: Andreas Fritiofson --- src/target/arm.h | 1 + src/target/armv4_5.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/target/arm.h b/src/target/arm.h index 27636cc3..d8361bd6 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -61,6 +61,7 @@ enum arm_mode { ARM_MODE_MON = 22, ARM_MODE_ABT = 23, ARM_MODE_UND = 27, + ARM_MODE_1176_MON = 28, ARM_MODE_SYS = 31, ARM_MODE_THREAD = 0, diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index e75fe99c..5b24e69a 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -140,6 +140,12 @@ static const struct { .n_indices = ARRAY_SIZE(arm_mon_indices), .indices = arm_mon_indices, }, + { + .name = "Secure Monitor ARM1176JZF-S", + .psr = ARM_MODE_1176_MON, + .n_indices = ARRAY_SIZE(arm_mon_indices), + .indices = arm_mon_indices, + }, /* These special modes are currently only supported * by ARMv6M and ARMv7M profiles */ @@ -199,6 +205,7 @@ int arm_mode_to_number(enum arm_mode mode) case ARM_MODE_SYS: return 6; case ARM_MODE_MON: + case ARM_MODE_1176_MON: return 7; default: LOG_ERROR("invalid mode value encountered %d", mode); -- 2.39.5