From 6823a97beb706a5a3a4b7f813d33a7f3faadf2f0 Mon Sep 17 00:00:00 2001 From: Christopher Head Date: Wed, 19 Sep 2018 16:20:26 -0700 Subject: [PATCH] target/atsamv: make APCSW cacheable Change-Id: Ic00d3192642c682f370a6f7f8b70ae29744eb746 Signed-off-by: Christopher Head Reviewed-on: http://openocd.zylin.com/4678 Tested-by: jenkins Reviewed-by: Tomas Vanek --- tcl/target/atsamv.cfg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg index d1f8454d..1d026aa9 100644 --- a/tcl/target/atsamv.cfg +++ b/tcl/target/atsamv.cfg @@ -50,3 +50,10 @@ if {![using_hla]} { set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME +# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal +# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 +# makes the data access cacheable. This allows reading and writing data in the +# CPU cache from the debugger, which is far more useful than going straight to +# RAM when operating on typical variables, and is generally no worse when +# operating on special memory locations. +$_CHIPNAME.dap apcsw 0x08000000 0x08000000 -- 2.39.5