From 8ac2c5cb01b2c5eb89d49528dcc4aefbbcb71d03 Mon Sep 17 00:00:00 2001 From: rtel Date: Sun, 30 Dec 2018 23:20:26 +0000 Subject: [PATCH] Re-org of RISC-V file structure and naming step 1. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2619 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- ...freertos_risc_v_port_specific_extensions.h | 0 ...freertos_risc_v_port_specific_extensions.h | 0 .../portable/GCC/RISC-V-RV32/readme.txt | 27 +++++++++++++++++++ 3 files changed, 27 insertions(+) rename FreeRTOS/Source/portable/GCC/RISC-V-RV32/{ => chip_specific_extensions}/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h (100%) rename FreeRTOS/Source/portable/GCC/RISC-V-RV32/{CLINT_no_extensions => }/freertos_risc_v_port_specific_extensions.h (100%) create mode 100644 FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h similarity index 100% rename from FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h rename to FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h similarity index 100% rename from FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h rename to FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt new file mode 100644 index 000000000..db628a412 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt @@ -0,0 +1,27 @@ + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_port_specific_extensions.h. There + * is one freertos_risc_v_port_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. -- 2.39.5