1 /**************************************************************************//**
3 * @brief IBDAP DAP config for LPC11U35
8 * Copyright (C) 2015 Armstart. All rights reserved.
14 ******************************************************************************/
16 #ifndef __DAP_CONFIG_H__
17 #define __DAP_CONFIG_H__
20 //**************************************************************************************************
22 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
23 \ingroup DAP_ConfigIO_gr
25 Provides definitions about:
26 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
27 - Debug Unit communication packet size.
28 - Debug Access Port communication mode (JTAG or SWD).
29 - Optional information about a connected Target Device (for Evaluation Boards).
38 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
39 /// This value is used to calculate the SWD/JTAG clock speed.
40 #define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz
42 /// Number of processor cycles for I/O Port write operations.
43 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
44 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
45 /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
46 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
48 #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
50 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
51 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
52 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
54 /// Indicate that JTAG communication mode is available at the Debug Port.
55 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
56 #define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
58 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
59 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
60 #define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
62 /// Default communication mode on the Debug Access Port.
63 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
64 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
66 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
67 /// Used to initialize the default SWD/JTAG clock frequency.
68 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
69 #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
71 /// Maximum Package Size for Command and Response data.
72 /// This configuration settings is used to optimized the communication performance with the
73 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
74 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
76 /// Maximum Package Buffers for Command and Response data.
77 /// This configuration settings is used to optimized the communication performance with the
78 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
79 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
80 #define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
83 /// Debug Unit is connected to fixed Target Device.
84 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
85 /// known device. In this case a Device Vendor and Device Name string is stored which
86 /// may be used by the debugger or IDE to configure device parameters.
87 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
89 #if TARGET_DEVICE_FIXED
90 #define TARGET_DEVICE_VENDOR "ARMSTART" ///< String indicating the Silicon Vendor
91 #define TARGET_DEVICE_NAME "IBDAP-LPC11U35 CMSIS-DAP" ///< String indicating the Target Device
97 // Peripheral register bit masks (used for pin inits)
100 #define PULL_DOWN_ENABLED (1 << 3)
101 #define PULL_UP_ENABLED (2 << 3)
102 #define OPENDRAIN (1 << 10)
104 // Debug Port I/O Pins
105 // For LPC11Uxx DAPs all SWD and JTAG pins are on GPIO port 0
106 // Default is mbed HDK reference design with LPC11U35/501
107 // SWCLK/TCK Pin PIO0_7
108 #define PIN_SWCLK_IN_BIT 7
109 #define PIN_SWCLK (1 << PIN_SWCLK_IN_BIT)
110 #define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7
112 // SWDIO/TMS In/Out Pin PIO0_8
113 #define PIN_SWDIO_IN_BIT 8
114 #define PIN_SWDIO (1 << PIN_SWDIO_IN_BIT)
115 #define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8
118 #define PIN_nRESET_IN_BIT 2
119 #define PIN_nRESET (1 << PIN_nRESET_IN_BIT)
120 #define PIN_nRESET_IOCON LPC_IOCON->PIO0_2
125 #define PIN_TDI_IN_BIT 17
126 #define PIN_TDI (1 << PIN_TDI_IN_BIT)
127 #define PIN_TDI_IOCON LPC_IOCON->PIO0_17
129 // SWO/TDO Pin PIO0_9
130 #define PIN_TDO_IN_BIT 9
131 #define PIN_TDO (1 << PIN_TDO_IN_BIT)
132 #define PIN_TDO_IOCON LPC_IOCON->PIO0_9
133 #endif // (DAP_JTAG != 0)
135 //**************************************************************************************************
137 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
138 \ingroup DAP_ConfigIO_gr
141 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
142 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
143 interface of a device. The following I/O Pins are provided:
145 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
146 ---------------------------- | -------------------- | ---------------------------------------------
147 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
148 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
149 TDI: Test Data Input | | Output Push/Pull
150 TDO: Test Data Output | | Input
151 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
152 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
155 DAP Hardware I/O Pin Access Functions
156 -------------------------------------
157 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
160 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
161 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
162 peripherals that can independently write/read a single I/O pin without affecting any other pins
163 of the same I/O port. The following SWDIO I/O Pin functions are provided:
164 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
165 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
166 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
167 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
171 // Configure DAP I/O pins ------------------------------
173 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
174 Configures the DAP Hardware I/O pins for JTAG mode:
175 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
178 static __inline void PORT_JTAG_SETUP (void) {
180 LPC_GPIO->SET[0] = PIN_TDI;
181 LPC_GPIO->DIR[0] |= PIN_TDI;
182 LPC_GPIO->DIR[0] &= ~PIN_TDO;
186 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
187 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
188 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
189 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
191 static __inline void PORT_SWD_SETUP (void) {
192 LPC_GPIO->SET[0] = PIN_SWCLK;
193 LPC_GPIO->SET[0] = PIN_SWDIO;
194 #if defined(CONF_OPENDRAIN)
196 LPC_GPIO->DIR[0] &= ~PIN_nRESET;
197 LPC_GPIO->CLR[0] = PIN_nRESET;
198 LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO);
200 LPC_GPIO->SET[0] = PIN_nRESET;
201 LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO | PIN_nRESET);
205 /** Disable JTAG/SWD I/O Pins.
206 Disables the DAP Hardware I/O pins which configures:
207 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
209 static __inline void PORT_OFF (void) {
210 LPC_GPIO->CLR[0] = PIN_SWCLK;
211 LPC_GPIO->CLR[0] = PIN_SWDIO;
212 #if defined(CONF_OPENDRAIN)
214 LPC_GPIO->DIR[0] &= ~PIN_nRESET; // reset not an output
215 LPC_GPIO->CLR[0] = PIN_nRESET;
216 LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO);
218 LPC_GPIO->SET[0] = PIN_nRESET;
219 LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO | PIN_nRESET);
224 // SWCLK/TCK I/O pin -------------------------------------
226 /** SWCLK/TCK I/O pin: Get Input.
227 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
229 static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
230 return LPC_GPIO->B[PIN_SWCLK_IN_BIT] & 0x1;
233 /** SWCLK/TCK I/O pin: Set Output to High.
234 Set the SWCLK/TCK DAP hardware I/O pin to high level.
236 static __forceinline void PIN_SWCLK_TCK_SET (void) {
237 LPC_GPIO->SET[0] = (PIN_SWCLK);
240 /** SWCLK/TCK I/O pin: Set Output to Low.
241 Set the SWCLK/TCK DAP hardware I/O pin to low level.
243 static __forceinline void PIN_SWCLK_TCK_CLR (void) {
244 LPC_GPIO->CLR[0] = (PIN_SWCLK);
248 // SWDIO/TMS Pin I/O --------------------------------------
250 /** SWDIO/TMS I/O pin: Get Input.
251 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
253 static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
254 return LPC_GPIO->B[PIN_SWDIO_IN_BIT] & 0x1;
257 /** SWDIO/TMS I/O pin: Set Output to High.
258 Set the SWDIO/TMS DAP hardware I/O pin to high level.
260 static __forceinline void PIN_SWDIO_TMS_SET (void) {
261 LPC_GPIO->SET[0] = (PIN_SWDIO);
264 /** SWDIO/TMS I/O pin: Set Output to Low.
265 Set the SWDIO/TMS DAP hardware I/O pin to low level.
267 static __forceinline void PIN_SWDIO_TMS_CLR (void) {
268 LPC_GPIO->CLR[0] = (PIN_SWDIO);
271 /** SWDIO I/O pin: Get Input (used in SWD mode only).
272 \return Current status of the SWDIO DAP hardware I/O pin.
274 static __forceinline uint32_t PIN_SWDIO_IN (void) {
275 return LPC_GPIO->B[PIN_SWDIO_IN_BIT] & 0x1;
278 /** SWDIO I/O pin: Set Output (used in SWD mode only).
279 \param bit Output value for the SWDIO DAP hardware I/O pin.
281 static __forceinline void PIN_SWDIO_OUT (uint32_t bit){
283 LPC_GPIO->SET[0] = (PIN_SWDIO);
285 LPC_GPIO->CLR[0] = (PIN_SWDIO);
288 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
289 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
290 called prior \ref PIN_SWDIO_OUT function calls.
292 static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
293 LPC_GPIO->DIR[0] |= (PIN_SWDIO);
296 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
297 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
298 called prior \ref PIN_SWDIO_IN function calls.
300 static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
301 LPC_GPIO->DIR[0] &= ~(PIN_SWDIO);
305 // TDI Pin I/O ---------------------------------------------
307 /** TDI I/O pin: Get Input.
308 \return Current status of the TDI DAP hardware I/O pin.
310 static __forceinline uint32_t PIN_TDI_IN (void) {
312 return LPC_GPIO->B[PIN_TDI_IN_BIT] & 0x1;
314 return (0); // Not available
318 /** TDI I/O pin: Set Output.
319 \param bit Output value for the TDI DAP hardware I/O pin.
321 static __forceinline void PIN_TDI_OUT (uint32_t bit) {
324 LPC_GPIO->SET[0] = (PIN_TDI);
326 LPC_GPIO->CLR[0] = (PIN_TDI);
333 // TDO Pin I/O ---------------------------------------------
335 /** TDO I/O pin: Get Input.
336 \return Current status of the TDO DAP hardware I/O pin.
338 static __forceinline uint32_t PIN_TDO_IN (void) {
340 return LPC_GPIO->B[PIN_TDO_IN_BIT] & 0x1;
342 return (0); // Not available
347 // nTRST Pin I/O -------------------------------------------
349 /** nTRST I/O pin: Get Input.
350 \return Current status of the nTRST DAP hardware I/O pin.
352 static __forceinline uint32_t PIN_nTRST_IN (void) {
353 return (0); // Not available
356 /** nTRST I/O pin: Set Output.
357 \param bit JTAG TRST Test Reset pin status:
358 - 0: issue a JTAG TRST Test Reset.
359 - 1: release JTAG TRST Test Reset.
361 static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
365 // nRESET Pin I/O------------------------------------------
367 /** nRESET I/O pin: Get Input.
368 \return Current status of the nRESET DAP hardware I/O pin.
370 static __forceinline uint32_t PIN_nRESET_IN (void) {
371 return LPC_GPIO->B[PIN_nRESET_IN_BIT] & 0x1;
374 /** nRESET I/O pin: Set Output.
375 \param bit target device hardware reset pin status:
376 - 0: issue a device hardware reset.
377 - 1: release device hardware reset.
379 static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
380 #if defined(CONF_OPENDRAIN)
382 if (bit) LPC_GPIO->DIR[0] &= ~PIN_nRESET; // input (pulled high external)
383 else LPC_GPIO->DIR[0] |= PIN_nRESET; // output (low)
386 LPC_GPIO->SET[0] = (PIN_nRESET);
388 LPC_GPIO->CLR[0] = (PIN_nRESET);
395 //**************************************************************************************************
397 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
398 \ingroup DAP_ConfigIO_gr
401 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
403 It is recommended to provide the following LEDs for status indication:
404 - Connect LED: is active when the DAP hardware is connected to a debugger.
405 - Running LED: is active when the debugger has put the target device into running state.
408 /** Debug Unit: Set status of Connected LED.
409 \param bit status of the Connect LED.
410 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
411 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
413 static __inline void LED_CONNECTED_OUT (uint32_t bit) {
416 /** Debug Unit: Set status Target Running LED.
417 \param bit status of the Target Running LED.
418 - 1: Target Running LED ON: program execution in target started.
419 - 0: Target Running LED OFF: program execution in target stopped.
421 static __inline void LED_RUNNING_OUT (uint32_t bit) {
428 //**************************************************************************************************
430 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
431 \ingroup DAP_ConfigIO_gr
434 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
437 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
438 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
439 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
440 - I/O clock system enabled.
441 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
442 - for nTRST, nRESET a weak pull-up (if available) is enabled.
443 - LED output pins are enabled and LEDs are turned off.
445 static __inline void DAP_SETUP (void) {
446 // Configure I/O pins
447 PIN_SWCLK_TCK_IOCON = FUNC_0 | PULL_UP_ENABLED; // SWCLK/TCK
448 PIN_SWDIO_TMS_IOCON = FUNC_0 | PULL_UP_ENABLED; // SWDIO/TMS
449 #if !defined(CONF_OPENDRAIN)
450 PIN_nRESET_IOCON = FUNC_0 | PULL_UP_ENABLED; // nRESET
452 PIN_nRESET_IOCON = FUNC_0 | OPENDRAIN; // nRESET
455 PIN_TDI_IOCON = FUNC_0 | PULL_UP_ENABLED; // TDI
456 PIN_TDO_IOCON = FUNC_0 | PULL_UP_ENABLED; // TDO
460 /** Reset Target Device with custom specific I/O pin or command sequence.
461 This function allows the optional implementation of a device specific reset sequence.
462 It is called when the command \ref DAP_ResetTarget and is for example required
463 when a device needs a time-critical unlock sequence that enables the debug port.
464 \return 0 = no device specific reset sequence is implemented.\n
465 1 = a device specific reset sequence is implemented.
467 static __inline uint32_t RESET_TARGET (void) {
468 return (0); // change to '1' when a device reset sequence is implemented
474 #endif /* __DAP_CONFIG_H__ */