+/******************************************************************************\r
+ * @file system_LPC11Uxx.c\r
+ * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File\r
+ * for the NXP LPC13xx Device Series\r
+ * @version V1.10\r
+ * @date 24. November 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#include <stdint.h>\r
+#include "LPC11Uxx.h"\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+/*--------------------- Clock Configuration ----------------------------------\r
+//\r
+// <e> Clock Configuration\r
+// <h> System Oscillator Control Register (SYSOSCCTRL)\r
+// <o1.0> BYPASS: System Oscillator Bypass Enable\r
+// <i> If enabled then PLL input (sys_osc_clk) is fed\r
+// <i> directly from XTALIN and XTALOUT pins.\r
+// <o1.9> FREQRANGE: System Oscillator Frequency Range\r
+// <i> Determines frequency range for Low-power oscillator.\r
+// <0=> 1 - 20 MHz\r
+// <1=> 15 - 25 MHz\r
+// </h>\r
+//\r
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)\r
+// <o2.0..4> DIVSEL: Select Divider for Fclkana\r
+// <i> wdt_osc_clk = Fclkana/ (2 � (1 + DIVSEL))\r
+// <0-31>\r
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)\r
+// <0=> Undefined\r
+// <1=> 0.5 MHz\r
+// <2=> 0.8 MHz\r
+// <3=> 1.1 MHz\r
+// <4=> 1.4 MHz\r
+// <5=> 1.6 MHz\r
+// <6=> 1.8 MHz\r
+// <7=> 2.0 MHz\r
+// <8=> 2.2 MHz\r
+// <9=> 2.4 MHz\r
+// <10=> 2.6 MHz\r
+// <11=> 2.7 MHz\r
+// <12=> 2.9 MHz\r
+// <13=> 3.1 MHz\r
+// <14=> 3.2 MHz\r
+// <15=> 3.4 MHz\r
+// </h>\r
+//\r
+// <h> System PLL Control Register (SYSPLLCTRL)\r
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)\r
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz\r
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz\r
+// <o3.0..4> MSEL: Feedback Divider Selection\r
+// <i> M = MSEL + 1\r
+// <0-31>\r
+// <o3.5..6> PSEL: Post Divider Selection\r
+// <0=> P = 1\r
+// <1=> P = 2\r
+// <2=> P = 4\r
+// <3=> P = 8\r
+// </h>\r
+//\r
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)\r
+// <o4.0..1> SEL: System PLL Clock Source\r
+// <0=> IRC Oscillator\r
+// <1=> System Oscillator\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> Main Clock Source Select Register (MAINCLKSEL)\r
+// <o5.0..1> SEL: Clock Source for Main Clock\r
+// <0=> IRC Oscillator\r
+// <1=> Input Clock to System PLL\r
+// <2=> WDT Oscillator\r
+// <3=> System PLL Clock Out\r
+// </h>\r
+//\r
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)\r
+// <o6.0..7> DIV: System AHB Clock Divider\r
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.\r
+// <i> 0 = is disabled\r
+// <0-255>\r
+// </h>\r
+//\r
+// <h> USB PLL Control Register (USBPLLCTRL)\r
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)\r
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz\r
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz\r
+// <o7.0..4> MSEL: Feedback Divider Selection\r
+// <i> M = MSEL + 1\r
+// <0-31>\r
+// <o7.5..6> PSEL: Post Divider Selection\r
+// <0=> P = 1\r
+// <1=> P = 2\r
+// <2=> P = 4\r
+// <3=> P = 8\r
+// </h>\r
+//\r
+// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)\r
+// <o8.0..1> SEL: USB PLL Clock Source\r
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation\r
+// <0=> IRC Oscillator\r
+// <1=> System Oscillator\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> USB Clock Source Select Register (USBCLKSEL)\r
+// <o9.0..1> SEL: System PLL Clock Source\r
+// <0=> USB PLL out\r
+// <1=> Main clock\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> USB Clock Divider Register (USBCLKDIV)\r
+// <o10.0..7> DIV: USB Clock Divider\r
+// <i> Divides USB clock to 48 MHz.\r
+// <i> 0 = is disabled\r
+// <0-255>\r
+// </h>\r
+// </e>\r
+*/\r
+#define CLOCK_SETUP 1\r
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000\r
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000\r
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000\r
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000\r
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000\r
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001\r
+#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000\r
+#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000\r
+#define USBCLKSEL_Val 0x00000000 // Reset: 0x000\r
+#define USBCLKDIV_Val 0x00000000 // Reset: 0x001\r
+\r
+#define PDRUNCFGUSEMASK 0x0000E800\r
+#define PDRUNCFGMASKTMP 0x000005FF\r
+\r
+/*\r
+//-------- <<< end of configuration section >>> ------------------------------\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Check the register settings\r
+ *----------------------------------------------------------------------------*/\r
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
+#define CHECK_RSVD(val, mask) (val & mask)\r
+\r
+/* Clock Configuration -------------------------------------------------------*/\r
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))\r
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))\r
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))\r
+ #error "SYSPLLCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))\r
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))\r
+ #error "MAINCLKSEL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))\r
+ #error "SYSAHBCLKDIV: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))\r
+ #error "USBPLLCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))\r
+ #error "USBPLLCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))\r
+ #error "USBCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))\r
+ #error "USBCLKDIV: Value out of range!"\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ DEFINES\r
+ *----------------------------------------------------------------------------*/\r
+ \r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define __XTAL (12000000UL) /* Oscillator frequency */\r
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */\r
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */\r
+\r
+\r
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)\r
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)\r
+\r
+#if (CLOCK_SETUP) /* Clock Setup */\r
+ #if (__FREQSEL == 0)\r
+ #define __WDT_OSC_CLK ( 0) /* undefined */\r
+ #elif (__FREQSEL == 1)\r
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)\r
+ #elif (__FREQSEL == 2)\r
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)\r
+ #elif (__FREQSEL == 3)\r
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)\r
+ #elif (__FREQSEL == 4)\r
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)\r
+ #elif (__FREQSEL == 5)\r
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)\r
+ #elif (__FREQSEL == 6)\r
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)\r
+ #elif (__FREQSEL == 7)\r
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)\r
+ #elif (__FREQSEL == 8)\r
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)\r
+ #elif (__FREQSEL == 9)\r
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)\r
+ #elif (__FREQSEL == 10)\r
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)\r
+ #elif (__FREQSEL == 11)\r
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)\r
+ #elif (__FREQSEL == 12)\r
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)\r
+ #elif (__FREQSEL == 13)\r
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)\r
+ #elif (__FREQSEL == 14)\r
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)\r
+ #else\r
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)\r
+ #endif\r
+\r
+ /* sys_pllclkin calculation */\r
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)\r
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)\r
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)\r
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)\r
+ #else\r
+ #define __SYS_PLLCLKIN (0)\r
+ #endif\r
+\r
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))\r
+\r
+ /* main clock calculation */\r
+ #if ((MAINCLKSEL_Val & 0x03) == 0)\r
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)\r
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)\r
+ #if (__FREQSEL == 0)\r
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"\r
+ #else\r
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)\r
+ #endif\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)\r
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)\r
+ #else\r
+ #define __MAIN_CLOCK (0)\r
+ #endif\r
+\r
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) \r
+\r
+#else\r
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)\r
+#endif // CLOCK_SETUP \r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock functions\r
+ *----------------------------------------------------------------------------*/\r
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\r
+{\r
+ uint32_t wdt_osc = 0;\r
+\r
+ /* Determine clock frequency according to clock register values */\r
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {\r
+ case 0: wdt_osc = 0; break;\r
+ case 1: wdt_osc = 500000; break;\r
+ case 2: wdt_osc = 800000; break;\r
+ case 3: wdt_osc = 1100000; break;\r
+ case 4: wdt_osc = 1400000; break;\r
+ case 5: wdt_osc = 1600000; break;\r
+ case 6: wdt_osc = 1800000; break;\r
+ case 7: wdt_osc = 2000000; break;\r
+ case 8: wdt_osc = 2200000; break;\r
+ case 9: wdt_osc = 2400000; break;\r
+ case 10: wdt_osc = 2600000; break;\r
+ case 11: wdt_osc = 2700000; break;\r
+ case 12: wdt_osc = 2900000; break;\r
+ case 13: wdt_osc = 3100000; break;\r
+ case 14: wdt_osc = 3200000; break;\r
+ case 15: wdt_osc = 3400000; break;\r
+ }\r
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;\r
+ \r
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ break;\r
+ case 1: /* Input Clock to System PLL */\r
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ break;\r
+ case 1: /* System oscillator */\r
+ SystemCoreClock = __SYS_OSC_CLK;\r
+ break;\r
+ case 2: /* Reserved */\r
+ case 3: /* Reserved */\r
+ SystemCoreClock = 0;\r
+ break;\r
+ }\r
+ break;\r
+ case 2: /* WDT Oscillator */\r
+ SystemCoreClock = wdt_osc;\r
+ break;\r
+ case 3: /* System PLL Clock Out */\r
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ } else {\r
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);\r
+ }\r
+ break;\r
+ case 1: /* System oscillator */\r
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {\r
+ SystemCoreClock = __SYS_OSC_CLK;\r
+ } else {\r
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);\r
+ }\r
+ break;\r
+ case 2: /* Reserved */\r
+ case 3: /* Reserved */\r
+ SystemCoreClock = 0;\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+\r
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; \r
+\r
+}\r
+\r
+__INLINE void SYSCTL_PowerDown(uint32_t powerdownmask)\r
+{\r
+ uint32_t pdrun;\r
+\r
+ pdrun = LPC_SYSCON->PDRUNCFG & PDRUNCFGMASKTMP;\r
+ pdrun |= (powerdownmask & PDRUNCFGMASKTMP);\r
+ LPC_SYSCON->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);\r
+}\r
+\r
+__INLINE void SYSCTL_PowerUp(uint32_t powerupmask)\r
+{\r
+ uint32_t pdrun;\r
+\r
+ pdrun = LPC_SYSCON->PDRUNCFG & PDRUNCFGMASKTMP;\r
+ pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);\r
+\r
+ LPC_SYSCON->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);\r
+}\r
+\r
+__STATIC_INLINE void FLASH_SetFLASHAccess(uint32_t clks)\r
+{\r
+ uint32_t tmp = LPC_FLASHCTRL->FLASHCFG & (~(0x3));\r
+\r
+ /* Don't alter upper bits */\r
+ LPC_FLASHCTRL->FLASHCFG = tmp | clks;\r
+}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+void SystemInit (void) {\r
+ volatile uint32_t i;\r
+\r
+#if (CLOCK_SETUP) /* Clock Setup */\r
+\r
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */\r
+ SYSCTL_PowerUp ((1 << 5));\r
+ //LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;\r
+ for (i = 0; i < 0x100; i++) __NOP();\r
+#endif\r
+\r
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */\r
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */\r
+\r
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */\r
+ SYSCTL_PowerDown (1 << 7);\r
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */\r
+ SYSCTL_PowerUp ((1 << 7));\r
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */\r
+#endif\r
+\r
+#if (((MAINCLKSEL_Val & 0x03) == 2) )\r
+ SYSCTL_PowerDown (1 << 6);\r
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */\r
+ SYSCTL_PowerUp ((1 << 6));\r
+ for (i = 0; i < 200; i++) __NOP();\r
+#endif\r
+\r
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;\r
+\r
+ FLASH_SetFLASHAccess (FLASHCFG_50MHZ_CPU);\r
+\r
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */\r
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->MAINCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */\r
+\r
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */\r
+ //SYSCTL_PowerDown (1 << 8);\r
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */\r
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */\r
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;\r
+ SYSCTL_PowerUp (1 << 8);\r
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */\r
+ //LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */\r
+\r
+#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */\r
+ SYSCTL_PowerDown (1 << 10);\r
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */\r
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */\r
+ SYSCTL_PowerUp (1 << 10);\r
+#endif\r
+\r
+\r
+\r
+#else /* USB clock is not used */ \r
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */\r
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */\r
+#endif\r
+\r
+#endif\r
+\r
+ /* System clock to the IOCON needs to be enabled or\r
+ most of the I/O related peripherals won't work. */\r
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);\r
+\r
+ LPC_IOCON->PIO0_3 = 1; // USB_VBUS\r
+ LPC_IOCON->PIO0_6 = 1; // USB_CONNECT\r
+\r
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 26;\r
+\r
+}\r
projects / armstart-ibdap / blobdiff