From: Stefan Date: Thu, 7 Feb 2019 11:19:49 +0000 (+0100) Subject: Fixed 65C02 timing. X-Git-Url: https://git.sur5r.net/?p=cc65;a=commitdiff_plain;h=50fd96bbabe91ad115ad324cd0aa2a19382905c1;hp=58484449b4842517d09618bc1c5dad59373250ef Fixed 65C02 timing. --- diff --git a/src/sim65/6502.c b/src/sim65/6502.c index bfbfbd78c..683937ed7 100644 --- a/src/sim65/6502.c +++ b/src/sim65/6502.c @@ -37,8 +37,6 @@ BBRx, BBSx, RMBx, SMBx, WAI, and STP are unsupported * BCD flag handling equals 6502 (unchecked if bug is simulated or wrong for 6502) - * one cycle win for fetch-modify-write instructions ignored - (e.g., ROL abs,x takes only 6 cycles if no page break occurs) */ #include "memory.h" @@ -629,6 +627,8 @@ static void OPC_6502_1E (void) unsigned Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr) << 1; MemWriteByte (Addr, (unsigned char) Val); TEST_ZF (Val & 0xFF); @@ -898,6 +898,8 @@ static void OPC_6502_3E (void) unsigned Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr); ROL (Val); MemWriteByte (Addr, Val); @@ -1132,6 +1134,8 @@ static void OPC_6502_5E (void) unsigned char Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr); SET_CF (Val & 0x01); Val >>= 1; @@ -1462,6 +1466,8 @@ static void OPC_6502_7E (void) unsigned Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr); ROR (Val); MemWriteByte (Addr, Val); @@ -2341,6 +2347,8 @@ static void OPC_6502_DE (void) unsigned char Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr) - 1; MemWriteByte (Addr, Val); TEST_ZF (Val); @@ -2648,6 +2656,8 @@ static void OPC_6502_FE (void) unsigned char Val; Cycles = 7; Addr = MemReadWord (Regs.PC+1) + Regs.XR; + if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) + --Cycles; Val = MemReadByte (Addr) + 1; MemWriteByte (Addr, Val); TEST_ZF (Val);