--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/**\r
+ * @file atomic.h\r
+ * @brief FreeRTOS atomic operation support.\r
+ *\r
+ * Two implementations of atomic are given in this header file:\r
+ * 1. Disabling interrupt globally.\r
+ * 2. ISA native atomic support.\r
+ * The former is available to all ports (compiler-architecture combination),\r
+ * while the latter is only available to ports compiling with GCC (version at\r
+ * least 4.7.0), which also have ISA atomic support.\r
+ *\r
+ * User can select which implementation to use by:\r
+ * setting/clearing configUSE_ATOMIC_INSTRUCTION in FreeRTOSConfig.h.\r
+ * Define AND set configUSE_ATOMIC_INSTRUCTION to 1 for ISA native atomic support.\r
+ * Undefine OR clear configUSE_ATOMIC_INSTRUCTION for disabling global interrupt\r
+ * implementation.\r
+ *\r
+ * @see GCC Built-in Functions for Memory Model Aware Atomic Operations\r
+ * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html\r
+ */\r
+\r
+#ifndef ATOMIC_H\r
+#define ATOMIC_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include atomic.h"\r
+#endif\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ /* Needed for __atomic_compare_exchange() weak=false. */\r
+ #include <stdbool.h>\r
+\r
+ /* This branch is for GCC compiler and GCC compiler only. */\r
+ #ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__((always_inline))\r
+ #endif\r
+\r
+#else\r
+\r
+ /* Port specific definitions -- entering/exiting critical section.\r
+ * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h\r
+ *\r
+ * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with\r
+ * ATOMIC_ENTER_CRITICAL().\r
+ */\r
+ #if defined( portSET_INTERRUPT_MASK_FROM_ISR )\r
+\r
+ /* Nested interrupt scheme is supported in this port. */\r
+ #define ATOMIC_ENTER_CRITICAL() \\r
+ UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()\r
+\r
+ #define ATOMIC_EXIT_CRITICAL() \\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )\r
+\r
+ #else\r
+\r
+ /* Nested interrupt scheme is NOT supported in this port. */\r
+ #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL()\r
+ #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL()\r
+\r
+ #endif /* portSET_INTERRUPT_MASK_FROM_ISR() */\r
+\r
+ /* Port specific definition -- "always inline". \r
+ * Inline is compiler specific, and may not always get inlined depending on your optimization level. \r
+ * Also, inline is considerred as performance optimization for atomic. \r
+ * Thus, if portFORCE_INLINE is not provided by portmacro.h, instead of resulting error,\r
+ * simply define it. \r
+ */\r
+ #ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE \r
+ #endif\r
+\r
+#endif /* configUSE_GCC_BUILTIN_ATOMICS */\r
+\r
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */\r
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */\r
+\r
+/*----------------------------- Swap && CAS ------------------------------*/\r
+\r
+/**\r
+ * Atomic compare-and-swap\r
+ *\r
+ * @brief Performs an atomic compare-and-swap operation on the specified values.\r
+ *\r
+ * @param[in, out] pDestination Pointer to memory location from where value is\r
+ * to be loaded and checked.\r
+ * @param[in] ulExchange If condition meets, write this value to memory.\r
+ * @param[in] ulComparand Swap condition.\r
+ *\r
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\r
+ *\r
+ * @note This function only swaps *pDestination with ulExchange, if previous\r
+ * *pDestination value equals ulComparand.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32(\r
+ uint32_t volatile * pDestination,\r
+ uint32_t ulExchange,\r
+ uint32_t ulComparand )\r
+{\r
+\r
+ uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\r
+\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ if ( __atomic_compare_exchange( pDestination,\r
+ &ulComparand,\r
+ &ulExchange,\r
+ false,\r
+ __ATOMIC_SEQ_CST,\r
+ __ATOMIC_SEQ_CST ) )\r
+ {\r
+ ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\r
+ }\r
+\r
+#else\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ if ( *pDestination == ulComparand )\r
+ {\r
+ *pDestination = ulExchange;\r
+ ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\r
+ }\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+#endif\r
+\r
+ return ulReturnValue;\r
+\r
+}\r
+\r
+/**\r
+ * Atomic swap (pointers)\r
+ *\r
+ * @brief Atomically sets the address pointed to by *ppDestination to the value\r
+ * of *pExchange.\r
+ *\r
+ * @param[in, out] ppDestination Pointer to memory location from where a pointer\r
+ * value is to be loaded and written back to.\r
+ * @param[in] pExchange Pointer value to be written to *ppDestination.\r
+ *\r
+ * @return The initial value of *ppDestination.\r
+ */\r
+static portFORCE_INLINE void * Atomic_SwapPointers_p32(\r
+ void * volatile * ppDestination,\r
+ void * pExchange )\r
+{\r
+ void * pReturnValue;\r
+\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ __atomic_exchange( ppDestination, &pExchange, &pReturnValue, __ATOMIC_SEQ_CST );\r
+\r
+#else\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ pReturnValue = *ppDestination;\r
+\r
+ *ppDestination = pExchange;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+#endif\r
+\r
+ return pReturnValue;\r
+}\r
+\r
+/**\r
+ * Atomic compare-and-swap (pointers)\r
+ *\r
+ * @brief Performs an atomic compare-and-swap operation on the specified pointer\r
+ * values.\r
+ *\r
+ * @param[in, out] ppDestination Pointer to memory location from where a pointer\r
+ * value is to be loaded and checked.\r
+ * @param[in] pExchange If condition meets, write this value to memory.\r
+ * @param[in] pComparand Swap condition.\r
+ *\r
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\r
+ *\r
+ * @note This function only swaps *ppDestination with pExchange, if previous\r
+ * *ppDestination value equals pComparand.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32(\r
+ void * volatile * ppDestination,\r
+ void * pExchange, void * pComparand )\r
+{\r
+ uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\r
+\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+ if ( __atomic_compare_exchange( ppDestination,\r
+ &pComparand,\r
+ &pExchange,\r
+ false,\r
+ __ATOMIC_SEQ_CST,\r
+ __ATOMIC_SEQ_CST ) )\r
+ {\r
+ ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\r
+ }\r
+\r
+#else\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ if ( *ppDestination == pComparand )\r
+ {\r
+ *ppDestination = pExchange;\r
+ ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\r
+ }\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+#endif\r
+\r
+ return ulReturnValue;\r
+}\r
+\r
+\r
+/*----------------------------- Arithmetic ------------------------------*/\r
+\r
+/**\r
+ * Atomic add\r
+ *\r
+ * @brief Atomically adds count to the value of the specified pointer points to.\r
+ *\r
+ * @param[in,out] pAddend Pointer to memory location from where value is to be\r
+ * loaded and written back to.\r
+ * @param[in] ulCount Value to be added to *pAddend.\r
+ *\r
+ * @return previous *pAddend value.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_Add_u32(\r
+ uint32_t volatile * pAddend,\r
+ uint32_t ulCount )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_add(pAddend, ulCount, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pAddend;\r
+\r
+ *pAddend += ulCount;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic subtract\r
+ *\r
+ * @brief Atomically subtracts count from the value of the specified pointer\r
+ * pointers to.\r
+ *\r
+ * @param[in,out] pAddend Pointer to memory location from where value is to be\r
+ * loaded and written back to.\r
+ * @param[in] ulCount Value to be subtract from *pAddend.\r
+ *\r
+ * @return previous *pAddend value.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_Subtract_u32(\r
+ uint32_t volatile * pAddend,\r
+ uint32_t ulCount )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_sub(pAddend, ulCount, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pAddend;\r
+\r
+ *pAddend -= ulCount;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic increment\r
+ *\r
+ * @brief Atomically increments the value of the specified pointer points to.\r
+ *\r
+ * @param[in,out] pAddend Pointer to memory location from where value is to be\r
+ * loaded and written back to.\r
+ *\r
+ * @return *pAddend value before increment.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pAddend )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_add(pAddend, 1, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pAddend;\r
+\r
+ *pAddend += 1;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic decrement\r
+ *\r
+ * @brief Atomically decrements the value of the specified pointer points to\r
+ *\r
+ * @param[in,out] pAddend Pointer to memory location from where value is to be\r
+ * loaded and written back to.\r
+ *\r
+ * @return *pAddend value before decrement.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pAddend )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_sub(pAddend, 1, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pAddend;\r
+\r
+ *pAddend -= 1;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/*----------------------------- Bitwise Logical ------------------------------*/\r
+\r
+/**\r
+ * Atomic OR\r
+ *\r
+ * @brief Performs an atomic OR operation on the specified values.\r
+ *\r
+ * @param [in, out] pDestination Pointer to memory location from where value is\r
+ * to be loaded and written back to.\r
+ * @param [in] ulValue Value to be ORed with *pDestination.\r
+ *\r
+ * @return The original value of *pDestination.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_OR_u32(\r
+ uint32_t volatile * pDestination,\r
+ uint32_t ulValue )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_or(pDestination, ulValue, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pDestination;\r
+\r
+ *pDestination |= ulValue;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic AND\r
+ *\r
+ * @brief Performs an atomic AND operation on the specified values.\r
+ *\r
+ * @param [in, out] pDestination Pointer to memory location from where value is\r
+ * to be loaded and written back to.\r
+ * @param [in] ulValue Value to be ANDed with *pDestination.\r
+ *\r
+ * @return The original value of *pDestination.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_AND_u32(\r
+ uint32_t volatile * pDestination,\r
+ uint32_t ulValue )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_and(pDestination, ulValue, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pDestination;\r
+\r
+ *pDestination &= ulValue;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic NAND\r
+ *\r
+ * @brief Performs an atomic NAND operation on the specified values.\r
+ *\r
+ * @param [in, out] pDestination Pointer to memory location from where value is\r
+ * to be loaded and written back to.\r
+ * @param [in] ulValue Value to be NANDed with *pDestination.\r
+ *\r
+ * @return The original value of *pDestination.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_NAND_u32(\r
+ uint32_t volatile * pDestination,\r
+ uint32_t ulValue )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_nand(pDestination, ulValue, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pDestination;\r
+\r
+ *pDestination = ~(ulCurrent & ulValue);\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * Atomic XOR\r
+ *\r
+ * @brief Performs an atomic XOR operation on the specified values.\r
+ *\r
+ * @param [in, out] pDestination Pointer to memory location from where value is\r
+ * to be loaded and written back to.\r
+ * @param [in] ulValue Value to be XORed with *pDestination.\r
+ *\r
+ * @return The original value of *pDestination.\r
+ */\r
+static portFORCE_INLINE uint32_t Atomic_XOR_u32(\r
+ uint32_t volatile * pDestination,\r
+ uint32_t ulValue )\r
+{\r
+#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 )\r
+\r
+ return __atomic_fetch_xor(pDestination, ulValue, __ATOMIC_SEQ_CST);\r
+\r
+#else\r
+\r
+ uint32_t ulCurrent;\r
+\r
+ ATOMIC_ENTER_CRITICAL();\r
+\r
+ ulCurrent = *pDestination;\r
+\r
+ *pDestination ^= ulValue;\r
+\r
+ ATOMIC_EXIT_CRITICAL();\r
+\r
+ return ulCurrent;\r
+\r
+#endif\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ATOMIC_H */\r
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