+++ /dev/null
-/*\r
- * Handling of Ethernet PHY's\r
- * PHY's communicate with an EMAC either through\r
- * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).\r
- * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports\r
- * shall be treated independently.\r
- * \r
- */\r
-\r
-/* Standard includes. */\r
-#include <stdint.h>\r
-#include <stdio.h>\r
-#include <stdlib.h>\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "queue.h"\r
-#include "semphr.h"\r
-\r
-/* FreeRTOS+TCP includes. */\r
-#include "FreeRTOS_IP.h"\r
-#include "FreeRTOS_Sockets.h"\r
-\r
-#include "phyHandling.h"\r
-\r
-#define phyMIN_PHY_ADDRESS 0\r
-#define phyMAX_PHY_ADDRESS 31\r
-\r
-#if defined( PHY_LS_HIGH_CHECK_TIME_MS ) || defined( PHY_LS_LOW_CHECK_TIME_MS )\r
- #warning please use the new defines with 'ipconfig' prefix\r
-#endif\r
-\r
-#ifndef ipconfigPHY_LS_HIGH_CHECK_TIME_MS\r
- /* Check if the LinkStatus in the PHY is still high after 15 seconds of not\r
- receiving packets. */\r
- #define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000uL\r
-#endif\r
-\r
-#ifndef ipconfigPHY_LS_LOW_CHECK_TIME_MS\r
- /* Check if the LinkStatus in the PHY is still low every second. */\r
- #define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000uL\r
-#endif\r
-\r
-/* As the following 3 macro's are OK in most situations, and so they're not\r
-included in 'FreeRTOSIPConfigDefaults.h'.\r
-Users can change their values in the project's 'FreeRTOSIPConfig.h'. */\r
-#ifndef phyPHY_MAX_RESET_TIME_MS\r
- #define phyPHY_MAX_RESET_TIME_MS 1000uL\r
-#endif\r
-\r
-#ifndef phyPHY_MAX_NEGOTIATE_TIME_MS\r
- #define phyPHY_MAX_NEGOTIATE_TIME_MS 3000uL\r
-#endif\r
-\r
-#ifndef phySHORT_DELAY_MS\r
- #define phySHORT_DELAY_MS 50uL\r
-#endif\r
-\r
-/* Naming and numbering of basic PHY registers. */\r
-#define phyREG_00_BMCR 0x00u /* Basic Mode Control Register. */\r
-#define phyREG_01_BMSR 0x01u /* Basic Mode Status Register. */\r
-#define phyREG_02_PHYSID1 0x02u /* PHYS ID 1 */\r
-#define phyREG_03_PHYSID2 0x03u /* PHYS ID 2 */\r
-#define phyREG_04_ADVERTISE 0x04u /* Advertisement control reg */\r
-\r
-/* Naming and numbering of extended PHY registers. */\r
-#define PHYREG_10_PHYSTS 0x10u /* 16 PHY status register Offset */\r
-#define phyREG_19_PHYCR 0x19u /* 25 RW PHY Control Register */\r
-#define phyREG_1F_PHYSPCS 0x1Fu /* 31 RW PHY Special Control Status */\r
-\r
-/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */\r
-#define phyBMCR_FULL_DUPLEX 0x0100u /* Full duplex. */\r
-#define phyBMCR_AN_RESTART 0x0200u /* Auto negotiation restart. */\r
-#define phyBMCR_ISOLATE 0x0400u /* 1 = Isolates 0 = Normal operation. */\r
-#define phyBMCR_AN_ENABLE 0x1000u /* Enable auto negotiation. */\r
-#define phyBMCR_SPEED_100 0x2000u /* Select 100Mbps. */\r
-#define phyBMCR_RESET 0x8000u /* Reset the PHY. */\r
-\r
-/* Bit fields for 'phyREG_19_PHYCR', the 'PHY Control Register'. */\r
-#define PHYCR_MDIX_EN 0x8000u /* Enable Auto MDIX. */\r
-#define PHYCR_MDIX_FORCE 0x4000u /* Force MDIX crossed. */\r
-\r
-#define phyBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */\r
-\r
-#define phyBMSR_LINK_STATUS 0x0004u\r
-\r
-#define phyPHYSTS_LINK_STATUS 0x0001u /* PHY Link mask */\r
-#define phyPHYSTS_SPEED_STATUS 0x0002u /* PHY Speed mask */\r
-#define phyPHYSTS_DUPLEX_STATUS 0x0004u /* PHY Duplex mask */\r
-\r
-/* Bit fields for 'phyREG_1F_PHYSPCS\r
- 001 = 10BASE-T half-duplex\r
- 101 = 10BASE-T full-duplex\r
- 010 = 100BASE-TX half-duplex\r
- 110 = 100BASE-TX full-duplex\r
-*/\r
-#define phyPHYSPCS_SPEED_MASK 0x000Cu\r
-#define phyPHYSPCS_SPEED_10 0x0004u\r
-#define phyPHYSPCS_FULL_DUPLEX 0x0010u\r
-\r
-/*\r
- * Description of all capabilities that can be advertised to\r
- * the peer (usually a switch or router).\r
- */\r
-\r
-#define phyADVERTISE_CSMA 0x0001u /* Supports IEEE 802.3u: Fast Ethernet at 100 Mbit/s */\r
-#define phyADVERTISE_10HALF 0x0020u /* Try for 10mbps half-duplex. */\r
-#define phyADVERTISE_10FULL 0x0040u /* Try for 10mbps full-duplex. */\r
-#define phyADVERTISE_100HALF 0x0080u /* Try for 100mbps half-duplex. */\r
-#define phyADVERTISE_100FULL 0x0100u /* Try for 100mbps full-duplex. */\r
-\r
-#define phyADVERTISE_ALL ( phyADVERTISE_10HALF | phyADVERTISE_10FULL | \\r
- phyADVERTISE_100HALF | phyADVERTISE_100FULL | \\r
- phyADVERTISE_CSMA )\r
-\r
-/* Send a reset command to a set of PHY-ports. */\r
-static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );\r
-\r
-static BaseType_t xHas_1F_PHYSPCS( uint32_t ulPhyID )\r
-{\r
-BaseType_t xResult;\r
-\r
- switch( ulPhyID )\r
- {\r
- case PHY_ID_LAN8720:\r
- case PHY_ID_LAN8742A:\r
- case PHY_ID_KSZ8041:\r
-/*\r
- case PHY_ID_KSZ8051: // same ID as 8041\r
- case PHY_ID_KSZ8081: // same ID as 8041\r
-*/\r
- case PHY_ID_KSZ8081MNXIA:\r
-\r
- case PHY_ID_KSZ8863:\r
- default:\r
- /* Most PHY's have a 1F_PHYSPCS */\r
- xResult = pdTRUE;\r
- break;\r
- case PHY_ID_DP83848I:\r
- xResult = pdFALSE;\r
- break;\r
- }\r
- return xResult;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static BaseType_t xHas_19_PHYCR( uint32_t ulPhyID )\r
-{\r
-BaseType_t xResult;\r
-\r
- switch( ulPhyID )\r
- {\r
- case PHY_ID_LAN8742A:\r
- case PHY_ID_DP83848I:\r
- xResult = pdTRUE;\r
- break;\r
- default:\r
- /* Most PHY's do not have a 19_PHYCR */\r
- xResult = pdFALSE;\r
- break;\r
- }\r
- return xResult;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Initialise the struct and assign a PHY-read and -write function. */\r
-void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite )\r
-{\r
- memset( ( void * )pxPhyObject, '\0', sizeof( *pxPhyObject ) );\r
-\r
- pxPhyObject->fnPhyRead = fnPhyRead;\r
- pxPhyObject->fnPhyWrite = fnPhyWrite;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */\r
-BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject )\r
-{\r
-BaseType_t xPhyAddress;\r
-\r
- pxPhyObject->xPortCount = 0;\r
-\r
- for( xPhyAddress = phyMIN_PHY_ADDRESS; xPhyAddress <= phyMAX_PHY_ADDRESS; xPhyAddress++ )\r
- {\r
- uint32_t ulLowerID;\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID );\r
- /* A valid PHY id can not be all zeros or all ones. */\r
- if( ( ulLowerID != ( uint16_t )~0u ) && ( ulLowerID != ( uint16_t )0u ) )\r
- {\r
- uint32_t ulUpperID;\r
- uint32_t ulPhyID;\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_02_PHYSID1, &ulUpperID );\r
- ulPhyID = ( ( ( uint32_t ) ulUpperID ) << 16 ) | ( ulLowerID & 0xFFF0 );\r
-\r
- pxPhyObject->ucPhyIndexes[ pxPhyObject->xPortCount ] = xPhyAddress;\r
- pxPhyObject->ulPhyIDs[ pxPhyObject->xPortCount ] = ulPhyID;\r
-\r
- pxPhyObject->xPortCount++;\r
-\r
- /* See if there is more storage space. */\r
- if( pxPhyObject->xPortCount == ipconfigPHY_MAX_PORTS )\r
- {\r
- break;\r
- }\r
- }\r
- }\r
- if( pxPhyObject->xPortCount > 0 )\r
- {\r
- FreeRTOS_printf( ( "PHY ID %lX\n", pxPhyObject->ulPhyIDs[ 0 ] ) );\r
- }\r
-\r
- return pxPhyObject->xPortCount;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Send a reset command to a set of PHY-ports. */\r
-static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
-{\r
-uint32_t ulDoneMask, ulConfig;\r
-TickType_t xRemainingTime;\r
-TimeOut_t xTimer;\r
-BaseType_t xPhyIndex;\r
-\r
- /* A bit-mask of PHY ports that are ready. */\r
- ulDoneMask = 0ul;\r
-\r
- /* Set the RESET bits high. */\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- /* Read Control register. */\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig | phyBMCR_RESET );\r
- }\r
-\r
- xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( phyPHY_MAX_RESET_TIME_MS );\r
- vTaskSetTimeOutState( &xTimer );\r
-\r
- /* The reset should last less than a second. */\r
- for( ;; )\r
- {\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
- if( ( ulConfig & phyBMCR_RESET ) == 0 )\r
- {\r
- FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET %d ready\n", (int)xPhyIndex ) );\r
- ulDoneMask |= ( 1ul << xPhyIndex );\r
- }\r
- }\r
- if( ulDoneMask == ulPhyMask )\r
- {\r
- break;\r
- }\r
- if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )\r
- {\r
- FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
- break;\r
- }\r
- /* Block for a while */\r
- vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );\r
- }\r
-\r
- /* Clear the reset bits. */\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
- {\r
- if( ( ulDoneMask & ( 1ul << xPhyIndex ) ) == 0uL )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- /* The reset operation timed out, clear the bit manually. */\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig & ~phyBMCR_RESET );\r
- }\r
- }\r
-\r
- vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );\r
-\r
- return ulDoneMask;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties )\r
-{\r
-uint32_t ulConfig, ulAdvertise;\r
-BaseType_t xPhyIndex;\r
-\r
- if( pxPhyObject->xPortCount < 1 )\r
- {\r
- FreeRTOS_printf( ( "xPhyConfigure: No PHY's detected.\n" ) );\r
- return -1;\r
- }\r
-\r
- /* The expected ID for the 'LAN8742A' is 0x0007c130. */\r
- /* The expected ID for the 'LAN8720' is 0x0007c0f0. */\r
- /* The expected ID for the 'DP83848I' is 0x20005C90. */\r
-\r
- /* Set advertise register. */\r
- if( ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) && ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) )\r
- {\r
- ulAdvertise = phyADVERTISE_ALL;\r
- /* Reset auto-negotiation capability. */\r
- }\r
- else\r
- {\r
- /* Always select protocol 802.3u. */\r
- ulAdvertise = phyADVERTISE_CSMA;\r
-\r
- if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO )\r
- {\r
- if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_100FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= phyADVERTISE_10HALF | phyADVERTISE_100HALF;\r
- }\r
- }\r
- else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO )\r
- {\r
- if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 )\r
- {\r
- ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_10HALF;\r
- }\r
- else\r
- {\r
- ulAdvertise |= phyADVERTISE_100FULL | phyADVERTISE_100HALF;\r
- }\r
- }\r
- else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 )\r
- {\r
- if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= phyADVERTISE_100FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= phyADVERTISE_100HALF;\r
- }\r
- }\r
- else\r
- {\r
- if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= phyADVERTISE_10FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= phyADVERTISE_10HALF;\r
- }\r
- }\r
- }\r
-\r
- /* Send a reset command to a set of PHY-ports. */\r
- xPhyReset( pxPhyObject, xPhyGetMask( pxPhyObject ) );\r
-\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
- uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];\r
-\r
- /* Write advertise register. */\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, ulAdvertise );\r
-\r
- /*\r
- AN_EN AN1 AN0 Forced Mode\r
- 0 0 0 10BASE-T, Half-Duplex\r
- 0 0 1 10BASE-T, Full-Duplex\r
- 0 1 0 100BASE-TX, Half-Duplex\r
- 0 1 1 100BASE-TX, Full-Duplex\r
- AN_EN AN1 AN0 Advertised Mode\r
- 1 0 0 10BASE-T, Half/Full-Duplex\r
- 1 0 1 100BASE-TX, Half/Full-Duplex\r
- 1 1 0 10BASE-T Half-Duplex\r
- 100BASE-TX, Half-Duplex\r
- 1 1 1 10BASE-T, Half/Full-Duplex\r
- 100BASE-TX, Half/Full-Duplex\r
- */\r
-\r
- /* Read Control register. */\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
-\r
- ulConfig &= ~( phyBMCR_SPEED_100 | phyBMCR_FULL_DUPLEX );\r
-\r
- ulConfig |= phyBMCR_AN_ENABLE;\r
-\r
- if( ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 ) || ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) )\r
- {\r
- ulConfig |= phyBMCR_SPEED_100;\r
- }\r
- else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 )\r
- {\r
- ulConfig &= ~phyBMCR_SPEED_100;\r
- }\r
-\r
- if( ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) || ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) )\r
- {\r
- ulConfig |= phyBMCR_FULL_DUPLEX;\r
- }\r
- else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_HALF )\r
- {\r
- ulConfig &= ~phyBMCR_FULL_DUPLEX;\r
- }\r
-\r
- if( xHas_19_PHYCR( ulPhyID ) )\r
- {\r
- uint32_t ulPhyControl;\r
- /* Read PHY Control register. */\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_19_PHYCR, &ulPhyControl );\r
-\r
- /* Clear bits which might get set: */\r
- ulPhyControl &= ~( PHYCR_MDIX_EN|PHYCR_MDIX_FORCE );\r
-\r
- if( pxPhyProperties->ucMDI_X == PHY_MDIX_AUTO )\r
- {\r
- ulPhyControl |= PHYCR_MDIX_EN;\r
- }\r
- else if( pxPhyProperties->ucMDI_X == PHY_MDIX_CROSSED )\r
- {\r
- /* Force direct link = Use crossed RJ45 cable. */\r
- ulPhyControl &= ~PHYCR_MDIX_FORCE;\r
- }\r
- else\r
- {\r
- /* Force crossed link = Use direct RJ45 cable. */\r
- ulPhyControl |= PHYCR_MDIX_FORCE;\r
- }\r
- /* update PHY Control Register. */\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_19_PHYCR, ulPhyControl );\r
- }\r
-\r
- FreeRTOS_printf( ( "+TCP: advertise: %04lX config %04lX\n", ulAdvertise, ulConfig ) );\r
- }\r
-\r
- /* Keep these values for later use. */\r
- pxPhyObject->ulBCRValue = ulConfig & ~phyBMCR_ISOLATE;\r
- pxPhyObject->ulACRValue = ulAdvertise;\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* xPhyFixedValue(): this function is called in case auto-negotiation is disabled.\r
-The caller has set the values in 'xPhyPreferences' (ucDuplex and ucSpeed).\r
-The PHY register phyREG_00_BMCR will be set for every connected PHY that matches\r
-with ulPhyMask. */\r
-BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
-{\r
-BaseType_t xPhyIndex;\r
-uint32_t ulValue, ulBitMask = ( uint32_t )1u;\r
-\r
- ulValue = ( uint32_t )0u;\r
-\r
- if( pxPhyObject->xPhyPreferences.ucDuplex == PHY_DUPLEX_FULL )\r
- {\r
- ulValue |= phyBMCR_FULL_DUPLEX;\r
- }\r
- if( pxPhyObject->xPhyPreferences.ucSpeed == PHY_SPEED_100 )\r
- {\r
- ulValue |= phyBMCR_SPEED_100;\r
- }\r
-\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
- {\r
- if( ( ulPhyMask & ulBitMask ) != 0lu )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- /* Enable Auto-Negotiation. */\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulValue );\r
- }\r
- }\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* xPhyStartAutoNegotiation() is the alternative xPhyFixedValue():\r
-It sets the BMCR_AN_RESTART bit and waits for the auto-negotiation completion\r
-( phyBMSR_AN_COMPLETE ). */\r
-BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
-{\r
-uint32_t xPhyIndex, ulDoneMask, ulBitMask;\r
-uint32_t ulPHYLinkStatus, ulRegValue;\r
-TickType_t xRemainingTime;\r
-TimeOut_t xTimer;\r
-\r
- if( ulPhyMask == ( uint32_t )0u )\r
- {\r
- return 0;\r
- }\r
- for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++ )\r
- {\r
- if( ( ulPhyMask & ( 1lu << xPhyIndex ) ) != 0lu )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- /* Enable Auto-Negotiation. */\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, pxPhyObject->ulACRValue);\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue | phyBMCR_AN_RESTART );\r
- }\r
- }\r
- xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( phyPHY_MAX_NEGOTIATE_TIME_MS );\r
- vTaskSetTimeOutState( &xTimer );\r
- ulDoneMask = 0;\r
- /* Wait until the auto-negotiation will be completed */\r
- for( ;; )\r
- {\r
- ulBitMask = ( uint32_t )1u;\r
- for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
- {\r
- if( ( ulPhyMask & ulBitMask ) != 0lu )\r
- {\r
- if( ( ulDoneMask & ulBitMask ) == 0lu )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue );\r
- if( ( ulRegValue & phyBMSR_AN_COMPLETE ) != 0 )\r
- {\r
- ulDoneMask |= ulBitMask;\r
- }\r
- }\r
- }\r
- }\r
- if( ulPhyMask == ulDoneMask )\r
- {\r
- break;\r
- }\r
- if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )\r
- {\r
- FreeRTOS_printf( ( "xPhyStartAutoNegotiation: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
- break;\r
- }\r
- vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );\r
- }\r
-\r
- if( ulDoneMask != ( uint32_t)0u )\r
- {\r
- ulBitMask = ( uint32_t )1u;\r
- pxPhyObject->ulLinkStatusMask &= ~( ulDoneMask );\r
- for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
- uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];\r
-\r
- if( ( ulDoneMask & ulBitMask ) == ( uint32_t )0u )\r
- {\r
- continue;\r
- }\r
-\r
- /* Clear the 'phyBMCR_AN_RESTART' bit. */\r
- pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue );\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue);\r
- if( ( ulRegValue & phyBMSR_LINK_STATUS ) != 0 )\r
- {\r
- ulPHYLinkStatus |= phyBMSR_LINK_STATUS;\r
- pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
- }\r
- else\r
- {\r
- ulPHYLinkStatus &= ~( phyBMSR_LINK_STATUS );\r
- }\r
-\r
- if( ulPhyID == PHY_ID_KSZ8081MNXIA )\r
- {\r
- uint32_t ulControlStatus;\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, 0x1E, &ulControlStatus);\r
- switch( ulControlStatus & 0x07 )\r
- {\r
- case 0x01:\r
- case 0x05:\r
-// [001] = 10BASE-T half-duplex\r
-// [101] = 10BASE-T full-duplex\r
- /* 10 Mbps. */\r
- ulRegValue |= phyPHYSTS_SPEED_STATUS;\r
- break;\r
- case 0x02:\r
- case 0x06:\r
-// [010] = 100BASE-TX half-duplex\r
-// [110] = 100BASE-TX full-duplex\r
- break;\r
- }\r
- switch( ulControlStatus & 0x07 )\r
- {\r
- case 0x05:\r
- case 0x06:\r
-// [101] = 10BASE-T full-duplex\r
-// [110] = 100BASE-TX full-duplex\r
- /* Full duplex. */\r
- ulRegValue |= phyPHYSTS_DUPLEX_STATUS;\r
- break;\r
- case 0x01:\r
- case 0x02:\r
-// [001] = 10BASE-T half-duplex\r
-// [010] = 100BASE-TX half-duplex\r
- break;\r
- }\r
- }\r
- else if( xHas_1F_PHYSPCS( ulPhyID ) )\r
- {\r
- /* 31 RW PHY Special Control Status */\r
- uint32_t ulControlStatus;\r
-\r
- pxPhyObject->fnPhyRead( xPhyAddress, phyREG_1F_PHYSPCS, &ulControlStatus);\r
- ulRegValue = 0;\r
- if( ( ulControlStatus & phyPHYSPCS_FULL_DUPLEX ) != 0 )\r
- {\r
- ulRegValue |= phyPHYSTS_DUPLEX_STATUS;\r
- }\r
- if( ( ulControlStatus & phyPHYSPCS_SPEED_MASK ) == phyPHYSPCS_SPEED_10 )\r
- {\r
- ulRegValue |= phyPHYSTS_SPEED_STATUS;\r
- }\r
- }\r
- else\r
- {\r
- /* Read the result of the auto-negotiation. */\r
- pxPhyObject->fnPhyRead( xPhyAddress, PHYREG_10_PHYSTS, &ulRegValue);\r
- }\r
-\r
- FreeRTOS_printf( ( "Autonego ready: %08lx: %s duplex %u mbit %s status\n",\r
- ulRegValue,\r
- ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",\r
- ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,\r
- ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ) );\r
- if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t )0u )\r
- {\r
- pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL;\r
- }\r
- else\r
- {\r
- pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_HALF;\r
- }\r
-\r
- if( ( ulRegValue & phyPHYSTS_SPEED_STATUS ) != 0 )\r
- {\r
- pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_10;\r
- }\r
- else\r
- {\r
- pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_100;\r
- }\r
- }\r
- } /* if( ulDoneMask != ( uint32_t)0u ) */\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception )\r
-{\r
-uint32_t ulStatus, ulBitMask = 1u;\r
-BaseType_t xPhyIndex;\r
-BaseType_t xNeedCheck = pdFALSE;\r
-\r
- if( xHadReception > 0 )\r
- {\r
- /* A packet was received. No need to check for the PHY status now,\r
- but set a timer to check it later on. */\r
- vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );\r
- pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
- {\r
- if( ( pxPhyObject->ulLinkStatusMask & ulBitMask ) == 0ul )\r
- {\r
- pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
- FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );\r
- xNeedCheck = pdTRUE;\r
- }\r
- }\r
- }\r
- else if( xTaskCheckForTimeOut( &( pxPhyObject->xLinkStatusTimer ), &( pxPhyObject->xLinkStatusRemaining ) ) != pdFALSE )\r
- {\r
- /* Frequent checking the PHY Link Status can affect for the performance of Ethernet controller.\r
- As long as packets are received, no polling is needed.\r
- Otherwise, polling will be done when the 'xLinkStatusTimer' expires. */\r
- for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
- {\r
- BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
-\r
- if( pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulStatus ) == 0 )\r
- {\r
- if( !!( pxPhyObject->ulLinkStatusMask & ulBitMask ) != !!( ulStatus & phyBMSR_LINK_STATUS ) )\r
- {\r
- if( ( ulStatus & phyBMSR_LINK_STATUS ) != 0 )\r
- {\r
- pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
- }\r
- else\r
- {\r
- pxPhyObject->ulLinkStatusMask &= ~( ulBitMask );\r
- }\r
- FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );\r
- xNeedCheck = pdTRUE;\r
- }\r
- }\r
- }\r
- vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );\r
- if( ( pxPhyObject->ulLinkStatusMask & phyBMSR_LINK_STATUS ) != 0 )\r
- {\r
- /* The link status is high, so don't poll the PHY too often. */\r
- pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );\r
- }\r
- else\r
- {\r
- /* The link status is low, polling may be done more frequently. */\r
- pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_LOW_CHECK_TIME_MS );\r
- }\r
- }\r
- return xNeedCheck;\r
-}\r
-/*-----------------------------------------------------------*/\r
projects / freertos / blobdiff