--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32fxx_hal_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.2.2\r
+ * @date 14-April-2017\r
+ * @brief Header file of ETH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32Fxx_HAL_ETH_H\r
+#define __STM32Fxx_HAL_ETH_H\r
+\r
+/* make sure that the original ETH headers files won't be included after this. */\r
+#define __STM32F2xx_HAL_ETH_H\r
+#define __STM32F4xx_HAL_ETH_H\r
+#define __STM32F7xx_HAL_ETH_H\r
+\r
+#if defined(STM32F7xx)\r
+ #include "stm32f7xx_hal_def.h"\r
+#elif defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
+ #include "stm32f4xx_hal_def.h"\r
+#elif defined(STM32F2xx)\r
+ #include "stm32f2xx_hal_def.h"\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** @addtogroup STM32Fxx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
+ ((SPEED) == ETH_SPEED_100M))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
+ ((CMD) == ETH_WATCHDOG_DISABLE))\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
+ ((CMD) == ETH_JABBER_DISABLE))\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEAll_DISABLE))\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
+ ((CMD) == ETH_FIXEDBURST_DISABLE))\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMATXDESC_IC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LS) || \\r
+ ((FLAG) == ETH_DMATXDESC_FS) || \\r
+ ((FLAG) == ETH_DMATXDESC_DC) || \\r
+ ((FLAG) == ETH_DMATXDESC_DP) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
+ ((FLAG) == ETH_DMATXDESC_TER) || \\r
+ ((FLAG) == ETH_DMATXDESC_TCH) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
+ ((FLAG) == ETH_DMATXDESC_IHE) || \\r
+ ((FLAG) == ETH_DMATXDESC_ES) || \\r
+ ((FLAG) == ETH_DMATXDESC_JT) || \\r
+ ((FLAG) == ETH_DMATXDESC_FF) || \\r
+ ((FLAG) == ETH_DMATXDESC_PCE) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCA) || \\r
+ ((FLAG) == ETH_DMATXDESC_NC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCO) || \\r
+ ((FLAG) == ETH_DMATXDESC_EC) || \\r
+ ((FLAG) == ETH_DMATXDESC_VF) || \\r
+ ((FLAG) == ETH_DMATXDESC_CC) || \\r
+ ((FLAG) == ETH_DMATXDESC_ED) || \\r
+ ((FLAG) == ETH_DMATXDESC_UF) || \\r
+ ((FLAG) == ETH_DMATXDESC_DB))\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMARXDESC_AFM) || \\r
+ ((FLAG) == ETH_DMARXDESC_ES) || \\r
+ ((FLAG) == ETH_DMARXDESC_DE) || \\r
+ ((FLAG) == ETH_DMARXDESC_SAF) || \\r
+ ((FLAG) == ETH_DMARXDESC_LE) || \\r
+ ((FLAG) == ETH_DMARXDESC_OE) || \\r
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
+ ((FLAG) == ETH_DMARXDESC_FS) || \\r
+ ((FLAG) == ETH_DMARXDESC_LS) || \\r
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARXDESC_LC) || \\r
+ ((FLAG) == ETH_DMARXDESC_FT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RWT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RE) || \\r
+ ((FLAG) == ETH_DMARXDESC_DBE) || \\r
+ ((FLAG) == ETH_DMARXDESC_CE) || \\r
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Defines\r
+ * @{\r
+ */\r
+/* Delay to wait when writing to some Ethernet registers */\r
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)\r
+\r
+/* Ethernet Errors */\r
+#define ETH_SUCCESS ((uint32_t)0U)\r
+#define ETH_ERROR ((uint32_t)1U)\r
+\r
+/* Ethernet DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)\r
+\r
+/* Ethernet DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame length Shift */\r
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */\r
+\r
+/* Ethernet MACMIIAR register Mask */\r
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)\r
+\r
+/* Ethernet MACCR register Mask */\r
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)\r
+\r
+/* Ethernet MACFCR register Mask */\r
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)\r
+\r
+/* Ethernet DMAOMR register Mask */\r
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)\r
+\r
+/* Ethernet Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8U\r
+\r
+/* Ethernet Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U\r
+ /**\r
+ * @}\r
+ */\r
+\r
+#ifdef _lint\r
+ #ifdef __IO\r
+ #undef __IO\r
+ #endif\r
+ #define __IO\r
+\r
+ #ifdef ETH_TypeDef\r
+ #undef ETH_TypeDef\r
+ #endif\r
+ #define ETH_TypeDef void\r
+\r
+ #ifdef HAL_LockTypeDef\r
+ #undef HAL_LockTypeDef\r
+ #endif\r
+ #define HAL_LockTypeDef unsigned\r
+\r
+ #ifdef ETH_RX_BUF_SIZE\r
+ #undef ETH_RX_BUF_SIZE\r
+ #endif\r
+ #define ETH_RX_BUF_SIZE 1536\r
+\r
+ #ifdef ETH_TX_BUF_SIZE\r
+ #undef ETH_TX_BUF_SIZE\r
+ #endif\r
+ #define ETH_TX_BUF_SIZE 1536\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Types ETH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */\r
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */\r
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+}HAL_ETH_StateTypeDef;\r
+\r
+/**\r
+ * @brief ETH Init Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */\r
+\r
+ uint16_t PhyAddress; /*!< Ethernet PHY address.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
+\r
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
+ This parameter can be a value of @ref ETH_Rx_Mode */\r
+\r
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.\r
+ This parameter can be a value of @ref ETH_Checksum_Mode */\r
+\r
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.\r
+ This parameter can be a value of @ref ETH_Media_Interface */\r
+\r
+} ETH_InitTypeDef;\r
+\r
+\r
+ /**\r
+ * @brief ETH MAC Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Watchdog */\r
+\r
+ uint32_t Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */\r
+\r
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode.\r
+ This parameter can be a value of @ref ETH_Receive_Own */\r
+\r
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */\r
+\r
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */\r
+\r
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a collision occurs (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */\r
+\r
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Deferral_Check */\r
+\r
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
+ This parameter can be a value of @ref ETH_Receive_All */\r
+\r
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.\r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */\r
+\r
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)\r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */\r
+\r
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */\r
+\r
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */\r
+\r
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */\r
+\r
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */\r
+\r
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame.\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+\r
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address).\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */\r
+\r
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */\r
+\r
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering.\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */\r
+\r
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+} ETH_MACInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */\r
+\r
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */\r
+\r
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */\r
+\r
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */\r
+\r
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+\r
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */\r
+\r
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
+\r
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
+\r
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */\r
+} ETH_DMAInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Descriptors data structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t Status; /*!< Status */\r
+\r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+\r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+\r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+\r
+ /*!< Enhanced Ethernet DMA PTP Descriptors */\r
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
+\r
+ uint32_t Reserved1; /*!< Reserved */\r
+\r
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
+\r
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
+\r
+} ETH_DMADescTypeDef;\r
+\r
+\r
+/**\r
+ * @brief Received Frame Informations structure definition\r
+ */\r
+typedef struct\r
+{\r
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
+\r
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
+\r
+ uint32_t SegCount; /*!< Segment count */\r
+\r
+ uint32_t length; /*!< Frame length */\r
+\r
+ uint32_t buffer; /*!< Frame buffer */\r
+\r
+} ETH_DMARxFrameInfos;\r
+\r
+\r
+/**\r
+ * @brief ETH Handle Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ ETH_TypeDef *Instance; /*!< Register base address */\r
+\r
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
+\r
+ uint32_t LinkStatus; /*!< Ethernet link status */\r
+\r
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
+\r
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
+\r
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
+\r
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
+\r
+ HAL_LockTypeDef Lock; /*!< ETH Lock */\r
+\r
+} ETH_HandleTypeDef;\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
+ * @{\r
+ */\r
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1536U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */\r
+#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */\r
+#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */\r
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */\r
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */\r
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */\r
+\r
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
+ to the driver receive buffers memory.\r
+\r
+ Depending on the size of the received Ethernet packet and the size of\r
+ each Ethernet driver receive buffer, the received packet can take one or more\r
+ Ethernet driver receive buffer.\r
+\r
+ In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE\r
+ and the total count of the driver receive buffers ETH_RXBUFNB.\r
+\r
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_RX_BUF_SIZE\r
+ #error please define ETH_RX_BUF_SIZE\r
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/\r
+#ifndef ETH_RXBUFNB\r
+ #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#endif\r
+\r
+\r
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the\r
+ driver transmit buffers memory to the TxFIFO.\r
+\r
+ Depending on the size of the Ethernet packet to be transmitted and the size of\r
+ each Ethernet driver transmit buffer, the packet to be transmitted can take\r
+ one or more Ethernet driver transmit buffer.\r
+\r
+ In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE\r
+ and the total count of the driver transmit buffers ETH_TXBUFNB.\r
+\r
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_TX_BUF_SIZE\r
+ #error please define ETH_TX_BUF_SIZE\r
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/\r
+#ifndef ETH_TXBUFNB\r
+ #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
+#endif\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Tx Descriptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */\r
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */\r
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */\r
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */\r
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */\r
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */\r
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */\r
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */\r
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */\r
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */\r
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */\r
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */\r
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */\r
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */\r
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */\r
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */\r
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */\r
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */\r
+\r
+/**\r
+ * @brief Bit definition of TDES1 register\r
+ */\r
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of TDES2 register\r
+ */\r
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of TDES3 register\r
+ */\r
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+ /*---------------------------------------------------------------------------------------------\r
+ TDES6 | Transmit Time Stamp Low [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES7 | Transmit Time Stamp High [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES6 register */\r
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */\r
+\r
+/* Bit definition of TDES7 register */\r
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Rx Descriptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */\r
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */\r
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */\r
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */\r
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */\r
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */\r
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */\r
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */\r
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */\r
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/**\r
+ * @brief Bit definition of RDES1 register\r
+ */\r
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */\r
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */\r
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of RDES2 register\r
+ */\r
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of RDES3 register\r
+ */\r
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES5 | Reserved[31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES6 | Receive Time Stamp Low [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES7 | Receive Time Stamp High [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES4 register */\r
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */\r
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */\r
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */\r
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */\r
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */\r
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */\r
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */\r
+\r
+/* Bit definition of RDES6 register */\r
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */\r
+\r
+/* Bit definition of RDES7 register */\r
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */\r
+/**\r
+ * @}\r
+ */\r
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation\r
+ * @{\r
+ */\r
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Speed ETH Speed\r
+ * @{\r
+ */\r
+#define ETH_SPEED_10M ((uint32_t)0x00000000U)\r
+#define ETH_SPEED_100M ((uint32_t)0x00004000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r
+ * @{\r
+ */\r
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)\r
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Rx_Mode ETH Rx Mode\r
+ * @{\r
+ */\r
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)\r
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)\r
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Media_Interface ETH Media Interface\r
+ * @{\r
+ */\r
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)\r
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Watchdog ETH Watchdog\r
+ * @{\r
+ */\r
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber ETH Jabber\r
+ * @{\r
+ */\r
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap\r
+ * @{\r
+ */\r
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r
+ * @{\r
+ */\r
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own ETH Receive Own\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode\r
+ * @{\r
+ */\r
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)\r
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)\r
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r
+ * @{\r
+ */\r
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r
+ * @{\r
+ */\r
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r
+ * @{\r
+ */\r
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)\r
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)\r
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)\r
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check ETH Deferral Check\r
+ * @{\r
+ */\r
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)\r
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All ETH Receive All\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)\r
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)\r
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)\r
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r
+ * @{\r
+ */\r
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r
+ * @{\r
+ */\r
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)\r
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r
+ * @{\r
+ */\r
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)\r
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)\r
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)\r
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause\r
+ * @{\r
+ */\r
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r
+ * @{\r
+ */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r
+ * @{\r
+ */\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)\r
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r
+ * @{\r
+ */\r
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)\r
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses ETH MAC addresses\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)\r
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)\r
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags\r
+ * @{\r
+ */\r
+#ifndef ETH_MAC_TXFIFO_FULL\r
+ #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+ #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+ #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+ #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+ #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+ #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+ #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+ #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+ #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+ #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+ #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+ #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */\r
+ #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */\r
+ #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+ #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+ #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+ #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+#else\r
+ /* stm32_hal_legacy.h has probably been included. That file defines 'ETH_MAC_TXFIFO_FULL' and all macro's here below. */\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r
+ * @{\r
+ */\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r
+ * @{\r
+ */\r
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r
+ * @{\r
+ */\r
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)\r
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r
+ * @{\r
+ */\r
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats\r
+ * @{\r
+ */\r
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r
+ * @{\r
+ */\r
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)\r
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r
+ * @{\r
+ */\r
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r
+ * @{\r
+ */\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)\r
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */\r
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers\r
+ * @{\r
+ */\r
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags ETH PMT Flags\r
+ * @{\r
+ */\r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags ETH MAC Flags\r
+ * @{\r
+ */\r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags ETH DMA Flags\r
+ * @{\r
+ */\r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */\r
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts\r
+ * @{\r
+ */\r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */\r
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */\r
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */\r
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow ETH DMA overflow\r
+ * @{\r
+ */\r
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r
+ * @{\r
+ */\r
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Macros ETH Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset ETH handle state\r
+ * @param __HANDLE__: specifies the ETH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of TDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of RDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r
+\r
+/**\r
+ * @brief Disables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r
+\r
+/**\r
+ * @brief Returns the specified Ethernet DMA Tx Desc collision count.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r
+\r
+/**\r
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the Ethernet flow control busy bit is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet MAC flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag\r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag\r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag\r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag\r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag\r
+ * @retval The state of Ethernet MAC flag.\r
+ */\r
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * enabled @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * disabled. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the Ethernet DMA IT pending bit.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+* @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA overflow flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r
+ * @retval The state of Ethernet DMA overflow Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r
+\r
+/**\r
+ * @brief Set the DMA Receive status watchdog timer register value\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __VALUE__: DMA Receive status watchdog timer register value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r
+\r
+/**\r
+ * @brief Enables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Enables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Disables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r
+\r
+/**\r
+ * @brief Disables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Disables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet PMT flag is set or not.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset\r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received\r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of Ethernet PMT Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\r
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Enables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Disables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enable event on ETH External event line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disable event on ETH External event line\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Get flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Clear flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\r
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\r
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup ETH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* IO operation functions ****************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r
+/* Communication with PHY functions*/\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r
+/* Callback in non blocking modes (Interrupt) */\r
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions ************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32Fxx_HAL_ETH_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff