+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief KS8851SNL driver for SAM.\r
+ *\r
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#include "spi_master.h"\r
+#include "ksz8851snl.h"\r
+#include "ksz8851snl_reg.h"\r
+#include "delay.h"\r
+#include "pio.h"\r
+#include "pio_handler.h"\r
+#include "pdc.h"\r
+#include "conf_eth.h"\r
+\r
+/* Clock polarity. */\r
+#define SPI_CLK_POLARITY 0\r
+\r
+/* Clock phase. */\r
+#define SPI_CLK_PHASE 1\r
+\r
+/* SPI PDC register base. */\r
+Pdc *g_p_spi_pdc = 0;\r
+\r
+int lUDPLoggingPrintf( const char *pcFormatString, ... );\r
+\r
+/* Temporary buffer for PDC reception. */\r
+uint8_t tmpbuf[1536] __attribute__ ((aligned (16)));\r
+\r
+union {\r
+ uint64_t ul[2];\r
+ uint8_t uc[16];\r
+} cmdBuf, respBuf;\r
+\r
+void dbg_add_line( const char *pcFormat, ... );\r
+\r
+static void spi_clear_ovres( void );\r
+\r
+/**\r
+ * \brief Read register content, set bitmask and write back to register.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param bits_to_set bitmask to apply.\r
+ */\r
+void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set)\r
+{\r
+ uint16_t temp;\r
+\r
+ temp = ksz8851_reg_read(reg);\r
+ temp |= bits_to_set;\r
+ ksz8851_reg_write(reg, temp);\r
+}\r
+\r
+/**\r
+ * \brief Read register content, clear bitmask and write back to register.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param bits_to_set bitmask to apply.\r
+ */\r
+void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr)\r
+{\r
+ uint16_t temp;\r
+\r
+ temp = ksz8851_reg_read(reg);\r
+ temp &= ~(uint32_t) bits_to_clr;\r
+ ksz8851_reg_write(reg, temp);\r
+}\r
+\r
+/**\r
+ * \brief Configure the INTN interrupt.\r
+ */\r
+void configure_intn(void (*p_handler) (uint32_t, uint32_t))\r
+{\r
+// gpio_configure_pin(KSZ8851SNL_INTN_GPIO, PIO_INPUT);\r
+// pio_set_input(PIOA, PIO_PA11_IDX, PIO_PULLUP);\r
+\r
+ /* Configure PIO clock. */\r
+ pmc_enable_periph_clk(INTN_ID);\r
+\r
+ /* Adjust PIO debounce filter parameters, uses 10 Hz filter. */\r
+ pio_set_debounce_filter(INTN_PIO, INTN_PIN_MSK, 10);\r
+\r
+ /* Initialize PIO interrupt handlers, see PIO definition in board.h. */\r
+ pio_handler_set(INTN_PIO, INTN_ID, INTN_PIN_MSK,\r
+ INTN_ATTR, p_handler);\r
+\r
+ /* Enable NVIC interrupts. */\r
+ NVIC_SetPriority(INTN_IRQn, INT_PRIORITY_PIO);\r
+ NVIC_EnableIRQ((IRQn_Type)INTN_ID);\r
+\r
+ /* Enable PIO interrupts. */\r
+ pio_enable_interrupt(INTN_PIO, INTN_PIN_MSK);\r
+}\r
+\r
+/**\r
+ * \brief Read a register value.\r
+ *\r
+ * \param reg the register address to modify.\r
+ *\r
+ * \return the register value.\r
+ */\r
+uint16_t ksz8851_reg_read(uint16_t reg)\r
+{\r
+pdc_packet_t g_pdc_spi_tx_packet;\r
+pdc_packet_t g_pdc_spi_rx_packet;\r
+uint16_t cmd = 0;\r
+uint16_t res = 0;\r
+int iTryCount = 3;\r
+\r
+ while( iTryCount-- > 0 )\r
+ {\r
+ uint32_t ulStatus;\r
+\r
+ spi_clear_ovres();\r
+ /* Move register address to cmd bits 9-2, make 32-bit address. */\r
+ cmd = (reg << 2) & REG_ADDR_MASK;\r
+\r
+ /* Last 2 bits still under "don't care bits" handled with byte enable. */\r
+ /* Select byte enable for command. */\r
+ if (reg & 2) {\r
+ /* Odd word address writes bytes 2 and 3 */\r
+ cmd |= (0xc << 10);\r
+ } else {\r
+ /* Even word address write bytes 0 and 1 */\r
+ cmd |= (0x3 << 10);\r
+ }\r
+\r
+ /* Add command read code. */\r
+ cmd |= CMD_READ;\r
+ cmdBuf.uc[0] = cmd >> 8;\r
+ cmdBuf.uc[1] = cmd & 0xff;\r
+ cmdBuf.uc[2] = CONFIG_SPI_MASTER_DUMMY;\r
+ cmdBuf.uc[3] = CONFIG_SPI_MASTER_DUMMY;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 4;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = 4;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ gpio_set_pin_low(KSZ8851SNL_CSN_GPIO);\r
+\r
+ spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul );\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ for( ;; )\r
+ {\r
+ ulStatus = spi_read_status( KSZ8851SNL_SPI );\r
+ if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ gpio_set_pin_high( KSZ8851SNL_CSN_GPIO );\r
+ if( ( ulStatus & SPI_SR_OVRES ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ lUDPLoggingPrintf( "ksz8851_reg_read: SPI_SR_OVRES\n" );\r
+ }\r
+\r
+ res = (tmpbuf[3] << 8) | tmpbuf[2];\r
+ return res;\r
+}\r
+\r
+/**\r
+ * \brief Write a register value.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param wrdata the new register value.\r
+ */\r
+void ksz8851_reg_write(uint16_t reg, uint16_t wrdata)\r
+{\r
+pdc_packet_t g_pdc_spi_tx_packet;\r
+pdc_packet_t g_pdc_spi_rx_packet;\r
+uint16_t cmd = 0;\r
+int iTryCount = 3;\r
+\r
+ while( iTryCount-- > 0 )\r
+ {\r
+ uint32_t ulStatus;\r
+\r
+\r
+ spi_clear_ovres();\r
+ /* Move register address to cmd bits 9-2, make 32-bit address. */\r
+ cmd = (reg << 2) & REG_ADDR_MASK;\r
+\r
+ /* Last 2 bits still under "don't care bits" handled with byte enable. */\r
+ /* Select byte enable for command. */\r
+ if (reg & 2) {\r
+ /* Odd word address writes bytes 2 and 3 */\r
+ cmd |= (0xc << 10);\r
+ } else {\r
+ /* Even word address write bytes 0 and 1 */\r
+ cmd |= (0x3 << 10);\r
+ }\r
+\r
+ /* Add command write code. */\r
+ cmd |= CMD_WRITE;\r
+ cmdBuf.uc[0] = cmd >> 8;\r
+ cmdBuf.uc[1] = cmd & 0xff;\r
+ cmdBuf.uc[2] = wrdata & 0xff;\r
+ cmdBuf.uc[3] = wrdata >> 8;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 4;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = 4;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ gpio_set_pin_low(KSZ8851SNL_CSN_GPIO);\r
+\r
+ spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul );\r
+\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ for( ;; )\r
+ {\r
+ ulStatus = spi_read_status( KSZ8851SNL_SPI );\r
+ if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ gpio_set_pin_high( KSZ8851SNL_CSN_GPIO );\r
+ if( ( ulStatus & SPI_SR_OVRES ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ lUDPLoggingPrintf( "ksz8851_reg_write: SPI_SR_OVRES\n" );\r
+ }\r
+}\r
+\r
+static void spi_clear_ovres( void )\r
+{\r
+volatile uint32_t rc;\r
+ rc = KSZ8851SNL_SPI->SPI_RDR;\r
+\r
+ spi_read_status( KSZ8851SNL_SPI );\r
+}\r
+\r
+/**\r
+ * \brief Read internal fifo buffer.\r
+ *\r
+ * \param buf the buffer to store the data from the fifo buffer.\r
+ * \param len the amount of data to read.\r
+ */\r
+void ksz8851_fifo_read(uint8_t *buf, uint32_t len)\r
+{\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+ pdc_packet_t g_pdc_spi_tx_npacket;\r
+ pdc_packet_t g_pdc_spi_rx_npacket;\r
+\r
+ memset( cmdBuf.uc, '\0', sizeof cmdBuf );\r
+ cmdBuf.uc[0] = FIFO_READ;\r
+ spi_clear_ovres();\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 9;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc;\r
+ g_pdc_spi_rx_packet.ul_size = 9;\r
+\r
+ g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_tx_npacket.ul_size = len;\r
+ g_pdc_spi_rx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_rx_npacket.ul_size = len;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket);\r
+\r
+spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_RXBUFF | SPI_IER_OVRES);\r
+\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+}\r
+\r
+/**\r
+ * \brief Write internal fifo buffer.\r
+ *\r
+ * \param buf the buffer to send to the fifo buffer.\r
+ * \param ulActualLength the total amount of data to write.\r
+ * \param ulFIFOLength the size of the first pbuf to write from the pbuf chain.\r
+ */\r
+void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength)\r
+{\r
+ static uint8_t frameID = 0;\r
+\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+ pdc_packet_t g_pdc_spi_tx_npacket;\r
+ pdc_packet_t g_pdc_spi_rx_npacket;\r
+\r
+ /* Prepare control word and byte count. */\r
+ cmdBuf.uc[0] = FIFO_WRITE;\r
+ cmdBuf.uc[1] = frameID++ & 0x3f;\r
+ cmdBuf.uc[2] = 0;\r
+ cmdBuf.uc[3] = ulActualLength & 0xff;\r
+ cmdBuf.uc[4] = ulActualLength >> 8;\r
+\r
+ spi_clear_ovres();\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 5;\r
+\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc;\r
+ g_pdc_spi_rx_packet.ul_size = 5;\r
+\r
+ g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_tx_npacket.ul_size = ulFIFOLength;\r
+\r
+ g_pdc_spi_rx_npacket.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_npacket.ul_size = ulFIFOLength;\r
+\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket);\r
+ #if( TX_USES_RECV == 1 )\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket);\r
+ spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_ENDRX | SPI_IER_OVRES);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ #else\r
+ spi_enable_interrupt(KSZ8851SNL_SPI, SPI_SR_TXBUFE | SPI_IER_OVRES);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_TXTEN);\r
+ #endif\r
+}\r
+\r
+/**\r
+ * \brief Write dummy data to the internal fifo buffer.\r
+ *\r
+ * \param len the amount of dummy data to write.\r
+ */\r
+void ksz8851_fifo_dummy(uint32_t len)\r
+{\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_tx_packet.ul_size = len;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = len;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+\r
+ while (!(spi_read_status(KSZ8851SNL_SPI) & SPI_SR_ENDRX))\r
+ ;\r
+}\r
+\r
+void ksz8851snl_set_registers(void)\r
+{\r
+ /* Init step2-4: write QMU MAC address (low, middle then high). */\r
+ ksz8851_reg_write(REG_MAC_ADDR_0, (ETHERNET_CONF_ETHADDR4 << 8) | ETHERNET_CONF_ETHADDR5);\r
+ ksz8851_reg_write(REG_MAC_ADDR_2, (ETHERNET_CONF_ETHADDR2 << 8) | ETHERNET_CONF_ETHADDR3);\r
+ ksz8851_reg_write(REG_MAC_ADDR_4, (ETHERNET_CONF_ETHADDR0 << 8) | ETHERNET_CONF_ETHADDR1);\r
+\r
+ /* Init step5: enable QMU Transmit Frame Data Pointer Auto Increment. */\r
+ ksz8851_reg_write(REG_TX_ADDR_PTR, ADDR_PTR_AUTO_INC);\r
+\r
+ /* Init step6: configure QMU transmit control register. */\r
+ ksz8851_reg_write(REG_TX_CTRL,\r
+ TX_CTRL_ICMP_CHECKSUM |\r
+ TX_CTRL_UDP_CHECKSUM |\r
+ TX_CTRL_TCP_CHECKSUM |\r
+ TX_CTRL_IP_CHECKSUM |\r
+ TX_CTRL_FLOW_ENABLE |\r
+ TX_CTRL_PAD_ENABLE |\r
+ TX_CTRL_CRC_ENABLE\r
+ );\r
+\r
+ /* Init step7: enable QMU Receive Frame Data Pointer Auto Increment. */\r
+ ksz8851_reg_write(REG_RX_ADDR_PTR, ADDR_PTR_AUTO_INC);\r
+\r
+ /* Init step8: configure QMU Receive Frame Threshold for one frame. */\r
+ ksz8851_reg_write(REG_RX_FRAME_CNT_THRES, 1);\r
+\r
+ /* Init step9: configure QMU receive control register1. */\r
+ ksz8851_reg_write(REG_RX_CTRL1,\r
+ RX_CTRL_UDP_CHECKSUM |\r
+ RX_CTRL_TCP_CHECKSUM |\r
+ RX_CTRL_IP_CHECKSUM |\r
+ RX_CTRL_MAC_FILTER |\r
+ RX_CTRL_FLOW_ENABLE |\r
+ RX_CTRL_BROADCAST |\r
+ RX_CTRL_ALL_MULTICAST|\r
+ RX_CTRL_UNICAST);\r
+// ksz8851_reg_write(REG_RX_CTRL1,\r
+// RX_CTRL_UDP_CHECKSUM |\r
+// RX_CTRL_TCP_CHECKSUM |\r
+// RX_CTRL_IP_CHECKSUM |\r
+// RX_CTRL_FLOW_ENABLE |\r
+// RX_CTRL_PROMISCUOUS);\r
+\r
+ ksz8851_reg_write(REG_RX_CTRL2,\r
+ RX_CTRL_IPV6_UDP_NOCHECKSUM |\r
+ RX_CTRL_UDP_LITE_CHECKSUM |\r
+ RX_CTRL_ICMP_CHECKSUM |\r
+ RX_CTRL_BURST_LEN_FRAME);\r
+\r
+\r
+//#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */\r
+#warning Remember to try the above option to get a 2-byte offset\r
+\r
+ /* Init step11: configure QMU receive queue: trigger INT and auto-dequeue frame. */\r
+ ksz8851_reg_write( REG_RXQ_CMD, RXQ_CMD_CNTL | RXQ_TWOBYTE_OFFSET );\r
+\r
+ /* Init step12: adjust SPI data output delay. */\r
+ ksz8851_reg_write(REG_BUS_CLOCK_CTRL, BUS_CLOCK_166 | BUS_CLOCK_DIVIDEDBY_1);\r
+\r
+ /* Init step13: restart auto-negotiation. */\r
+ ksz8851_reg_setbits(REG_PORT_CTRL, PORT_AUTO_NEG_RESTART);\r
+\r
+ /* Init step13.1: force link in half duplex if auto-negotiation failed. */\r
+ if ((ksz8851_reg_read(REG_PORT_CTRL) & PORT_AUTO_NEG_RESTART) != PORT_AUTO_NEG_RESTART)\r
+ {\r
+ ksz8851_reg_clrbits(REG_PORT_CTRL, PORT_FORCE_FULL_DUPLEX);\r
+ }\r
+\r
+ /* Init step14: clear interrupt status. */\r
+ ksz8851_reg_write(REG_INT_STATUS, 0xFFFF);\r
+\r
+ /* Init step15: set interrupt mask. */\r
+ ksz8851_reg_write(REG_INT_MASK, INT_RX);\r
+\r
+ /* Init step16: enable QMU Transmit. */\r
+ ksz8851_reg_setbits(REG_TX_CTRL, TX_CTRL_ENABLE);\r
+\r
+ /* Init step17: enable QMU Receive. */\r
+ ksz8851_reg_setbits(REG_RX_CTRL1, RX_CTRL_ENABLE);\r
+}\r
+/**\r
+ * \brief KSZ8851SNL initialization function.\r
+ *\r
+ * \return 0 on success, 1 on communication error.\r
+ */\r
+uint32_t ksz8851snl_init(void)\r
+{\r
+uint32_t count = 10;\r
+uint16_t dev_id = 0;\r
+uint8_t id_ok = 0;\r
+\r
+ /* Configure the SPI peripheral. */\r
+ spi_enable_clock(KSZ8851SNL_SPI);\r
+ spi_disable(KSZ8851SNL_SPI);\r
+ spi_reset(KSZ8851SNL_SPI);\r
+ spi_set_master_mode(KSZ8851SNL_SPI);\r
+ spi_disable_mode_fault_detect(KSZ8851SNL_SPI);\r
+ spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN));\r
+spi_set_fixed_peripheral_select(KSZ8851SNL_SPI);\r
+//spi_disable_peripheral_select_decode(KSZ8851SNL_SPI);\r
+\r
+ spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY);\r
+ spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE);\r
+ spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN,\r
+ SPI_CSR_BITS_8_BIT);\r
+ spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED));\r
+// spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS,\r
+// CONFIG_SPI_MASTER_DELAY_BCT);\r
+\r
+\r
+ spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0);\r
+\r
+ spi_enable(KSZ8851SNL_SPI);\r
+\r
+ /* Get pointer to UART PDC register base. */\r
+ g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+\r
+ /* Control RSTN and CSN pin from the driver. */\r
+ gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS);\r
+ gpio_set_pin_high(KSZ8851SNL_CSN_GPIO);\r
+ gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS);\r
+\r
+ /* Reset the Micrel in a proper state. */\r
+ while( count-- )\r
+ {\r
+ /* Perform hardware reset with respect to the reset timing from the datasheet. */\r
+ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+ gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+\r
+ /* Init step1: read chip ID. */\r
+ dev_id = ksz8851_reg_read(REG_CHIP_ID);\r
+ if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )\r
+ {\r
+ id_ok = 1;\r
+ break;\r
+ }\r
+ }\r
+ if( id_ok != 0 )\r
+ {\r
+ ksz8851snl_set_registers();\r
+ }\r
+\r
+ return id_ok ? 1 : -1;\r
+}\r
+\r
+uint32_t ksz8851snl_reinit(void)\r
+{\r
+uint32_t count = 10;\r
+uint16_t dev_id = 0;\r
+uint8_t id_ok = 0;\r
+ /* Reset the Micrel in a proper state. */\r
+ while( count-- )\r
+ {\r
+ /* Perform hardware reset with respect to the reset timing from the datasheet. */\r
+ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+ gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+\r
+ /* Init step1: read chip ID. */\r
+ dev_id = ksz8851_reg_read(REG_CHIP_ID);\r
+ if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )\r
+ {\r
+ id_ok = 1;\r
+ break;\r
+ }\r
+ }\r
+ if( id_ok != 0 )\r
+ {\r
+ ksz8851snl_set_registers();\r
+ }\r
+\r
+ return id_ok ? 1 : -1;\r
+}\r
+\r
+uint32_t ksz8851snl_reset_rx( void )\r
+{\r
+uint16_t usValue;\r
+\r
+ usValue = ksz8851_reg_read(REG_RX_CTRL1);\r
+\r
+ usValue &= ~( ( uint16_t ) RX_CTRL_ENABLE | RX_CTRL_FLUSH_QUEUE );\r
+\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 2 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_ENABLE ); vTaskDelay( 1 );\r
+\r
+ return ( uint32_t )usValue;\r
+}\r
+\r
+uint32_t ksz8851snl_reset_tx( void )\r
+{\r
+uint16_t usValue;\r
+\r
+ usValue = ksz8851_reg_read( REG_TX_CTRL );\r
+\r
+ usValue &= ~( ( uint16_t ) TX_CTRL_ENABLE | TX_CTRL_FLUSH_QUEUE );\r
+\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 2 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_ENABLE ); vTaskDelay( 1 );\r
+\r
+ return ( uint32_t )usValue;\r
+}\r
projects / freertos / blobdiff