]> git.sur5r.net Git - freertos/blobdiff - FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcHardwarePort.c
Update trace recorder to include heap tracing and new v8 features.
[freertos] / FreeRTOS-Plus / Source / FreeRTOS-Plus-Trace / trcHardwarePort.c
index 6570e3553fcc28182b797cc0b52ebed6f7e1ccc0..ac4a6f263b6159c99edbb8e3897cd8b04fb7a283 100644 (file)
@@ -1,5 +1,5 @@
 /******************************************************************************* \r
- * Tracealyzer v2.5.0 Recorder Library\r
+ * Tracealyzer v2.6.0 Recorder Library\r
  * Percepio AB, www.percepio.com\r
  *\r
  * trcHardwarePort.c\r
@@ -37,6 +37,7 @@
  ******************************************************************************/\r
 \r
 #include "trcHardwarePort.h"\r
+#include "trcKernelPort.h"\r
 \r
 #if (USE_TRACEALYZER_RECORDER == 1)\r
 \r
@@ -55,6 +56,45 @@ uint32_t last_timestamp = 0;
  ******************************************************************************/\r
 uint32_t uiTraceTickCount = 0;\r
 \r
+uint32_t DWT_CYCLES_ADDED = 0;\r
+\r
+#if (SELECTED_PORT == PORT_ARM_CortexM)\r
+\r
+void prvTraceEnableIRQ(void)\r
+{\r
+       asm volatile ("cpsie i");\r
+}\r
+\r
+void prvTraceDisableIRQ(void)\r
+{\r
+       asm volatile ("cpsid i");\r
+}\r
+\r
+void prvTraceSetIRQMask(uint32_t priMask)\r
+{\r
+       asm volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+uint32_t prvTraceGetIRQMask(void)\r
+{\r
+       uint32_t result;\r
+       asm volatile ("MRS %0, primask" : "=r" (result) );\r
+       return result;\r
+}\r
+\r
+void prvTraceInitCortexM()\r
+{\r
+       DWT_CTRL_REG |= 1;     /* Enable the cycle counter */\r
+       DWT_CYCLE_COUNTER = 0;\r
+       \r
+       if (RecorderDataPtr->frequency == 0)\r
+       {               \r
+               RecorderDataPtr->frequency = TRACE_CPU_CLOCK_HZ / HWTC_DIVISOR;\r
+       }\r
+}\r
+\r
+#endif\r
+\r
 /******************************************************************************\r
  * vTracePortGetTimeStamp\r
  *\r