--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ .global vRegTest1Implementation\r
+ .global vRegTest2Implementation\r
+ .extern ullRegTest1LoopCounter\r
+ .extern ullRegTest2LoopCounter\r
+\r
+ .text\r
+\r
+ /* This function is explained in the comments at the top of main-full.c. */\r
+.type vRegTest1Implementation, %function\r
+vRegTest1Implementation:\r
+\r
+ /* Fill each general purpose register with a known value. */\r
+ mov x0, #0xff\r
+ mov x1, #0x01\r
+ mov x2, #0x02\r
+ mov x3, #0x03\r
+ mov x4, #0x04\r
+ mov x5, #0x05\r
+ mov x6, #0x06\r
+ mov x7, #0x07\r
+ mov x8, #0x08\r
+ mov x9, #0x09\r
+ mov x10, #0x10\r
+ mov x11, #0x11\r
+ mov x12, #0x12\r
+ mov x13, #0x13\r
+ mov x14, #0x14\r
+ mov x15, #0x15\r
+ mov x16, #0x16\r
+ mov x17, #0x17\r
+ mov x18, #0x18\r
+ mov x19, #0x19\r
+ mov x20, #0x20\r
+ mov x21, #0x21\r
+ mov x22, #0x22\r
+ mov x23, #0x23\r
+ mov x24, #0x24\r
+ mov x25, #0x25\r
+ mov x26, #0x26\r
+ mov x27, #0x27\r
+ mov x28, #0x28\r
+ mov x29, #0x29\r
+ mov x30, #0x30\r
+\r
+ /* Fill each FPU register with a known value. */\r
+ fmov v0.d[1], x0\r
+ fmov d1, x1\r
+ fmov d2, x2\r
+ fmov d3, x3\r
+ fmov d4, x4\r
+ fmov d5, x5\r
+ fmov d6, x6\r
+ fmov d7, x7\r
+ fmov d8, x8\r
+ fmov d9, x9\r
+ fmov d10, x10\r
+ fmov d11, x11\r
+ fmov d12, x12\r
+ fmov d13, x13\r
+ fmov d14, x14\r
+ fmov d15, x15\r
+ fmov d16, x16\r
+ fmov d17, x17\r
+ fmov d18, x18\r
+ fmov d19, x19\r
+ fmov d20, x20\r
+ fmov d21, x21\r
+ fmov d22, x22\r
+ fmov d23, x23\r
+ fmov d24, x24\r
+ fmov d25, x25\r
+ fmov d26, x26\r
+ fmov d27, x27\r
+ fmov d28, x28\r
+ fmov d29, x29\r
+ fmov v30.d[1], x30\r
+ fmov d31, xzr\r
+\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+reg1_loop:\r
+ /* Yield to increase test coverage */\r
+ SMC 0\r
+\r
+ /* Test each general purpose register to check that it still contains the\r
+ expected known value, jumping to reg1_error_loop if any register contains\r
+ an unexpected value. */\r
+ cmp x0, #0xFF\r
+ bne reg1_error_loop\r
+ cmp x1, #0x01\r
+ bne reg1_error_loop\r
+ cmp x2, #0x02\r
+ bne reg1_error_loop\r
+ cmp x3, #0x03\r
+ bne reg1_error_loop\r
+ cmp x4, #0x04\r
+ bne reg1_error_loop\r
+ cmp x5, #0x05\r
+ bne reg1_error_loop\r
+ cmp x6, #0x06\r
+ bne reg1_error_loop\r
+ cmp x7, #0x07\r
+ bne reg1_error_loop\r
+ cmp x8, #0x08\r
+ bne reg1_error_loop\r
+ cmp x9, #0x09\r
+ bne reg1_error_loop\r
+ cmp x10, #0x10\r
+ bne reg1_error_loop\r
+ cmp x11, #0x11\r
+ bne reg1_error_loop\r
+ cmp x12, #0x12\r
+ bne reg1_error_loop\r
+ cmp x13, #0x13\r
+ bne reg1_error_loop\r
+ cmp x14, #0x14\r
+ bne reg1_error_loop\r
+ cmp x15, #0x15\r
+ bne reg1_error_loop\r
+ cmp x16, #0x16\r
+ bne reg1_error_loop\r
+ cmp x17, #0x17\r
+ bne reg1_error_loop\r
+ cmp x18, #0x18\r
+ bne reg1_error_loop\r
+ cmp x19, #0x19\r
+ bne reg1_error_loop\r
+ cmp x20, #0x20\r
+ bne reg1_error_loop\r
+ cmp x21, #0x21\r
+ bne reg1_error_loop\r
+ cmp x22, #0x22\r
+ bne reg1_error_loop\r
+ cmp x23, #0x23\r
+ bne reg1_error_loop\r
+ cmp x24, #0x24\r
+ bne reg1_error_loop\r
+ cmp x25, #0x25\r
+ bne reg1_error_loop\r
+ cmp x26, #0x26\r
+ bne reg1_error_loop\r
+ cmp x27, #0x27\r
+ bne reg1_error_loop\r
+ cmp x28, #0x28\r
+ bne reg1_error_loop\r
+ cmp x29, #0x29\r
+ bne reg1_error_loop\r
+ cmp x30, #0x30\r
+ bne reg1_error_loop\r
+\r
+ /* Check every floating point register to ensure it contains the expected\r
+ value. First save the registers clobbered by the test. */\r
+ stp x0, x1, [sp,#-0x10]!\r
+\r
+ fmov x0, v0.d[1]\r
+ cmp x0, 0xff\r
+ bne reg1_error_loop\r
+ fmov x0, d1\r
+ cmp x0, 0x01\r
+ bne reg1_error_loop\r
+ fmov x0, d2\r
+ cmp x0, 0x02\r
+ bne reg1_error_loop\r
+ fmov x0, d3\r
+ cmp x0, 0x03\r
+ bne reg1_error_loop\r
+ fmov x0, d4\r
+ cmp x0, 0x04\r
+ bne reg1_error_loop\r
+ fmov x0, d5\r
+ cmp x0, 0x05\r
+ bne reg1_error_loop\r
+ fmov x0, d6\r
+ cmp x0, 0x06\r
+ bne reg1_error_loop\r
+ fmov x0, d7\r
+ cmp x0, 0x07\r
+ bne reg1_error_loop\r
+ fmov x0, d8\r
+ cmp x0, 0x08\r
+ bne reg1_error_loop\r
+ fmov x0, d9\r
+ cmp x0, 0x09\r
+ bne reg1_error_loop\r
+ fmov x0, d10\r
+ cmp x0, 0x10\r
+ bne reg1_error_loop\r
+ fmov x0, d11\r
+ cmp x0, 0x11\r
+ bne reg1_error_loop\r
+ fmov x0, d12\r
+ cmp x0, 0x12\r
+ bne reg1_error_loop\r
+ fmov x0, d13\r
+ cmp x0, 0x13\r
+ bne reg1_error_loop\r
+ fmov x0, d14\r
+ cmp x0, 0x14\r
+ bne reg1_error_loop\r
+ fmov x0, d15\r
+ cmp x0, 0x15\r
+ bne reg1_error_loop\r
+ fmov x0, d16\r
+ cmp x0, 0x16\r
+ bne reg1_error_loop\r
+ fmov x0, d17\r
+ cmp x0, 0x17\r
+ bne reg1_error_loop\r
+ fmov x0, d18\r
+ cmp x0, 0x18\r
+ bne reg1_error_loop\r
+ fmov x0, d19\r
+ cmp x0, 0x19\r
+ bne reg1_error_loop\r
+ fmov x0, d20\r
+ cmp x0, 0x20\r
+ bne reg1_error_loop\r
+ fmov x0, d21\r
+ cmp x0, 0x21\r
+ bne reg1_error_loop\r
+ fmov x0, d22\r
+ cmp x0, 0x22\r
+ bne reg1_error_loop\r
+ fmov x0, d23\r
+ cmp x0, 0x23\r
+ bne reg1_error_loop\r
+ fmov x0, d24\r
+ cmp x0, 0x24\r
+ bne reg1_error_loop\r
+ fmov x0, d25\r
+ cmp x0, 0x25\r
+ bne reg1_error_loop\r
+ fmov x0, d26\r
+ cmp x0, 0x26\r
+ bne reg1_error_loop\r
+ fmov x0, d27\r
+ cmp x0, 0x27\r
+ bne reg1_error_loop\r
+ fmov x0, d28\r
+ cmp x0, 0x28\r
+ bne reg1_error_loop\r
+ fmov x0, d29\r
+ cmp x0, 0x29\r
+ bne reg1_error_loop\r
+ fmov x0, v30.d[1]\r
+ cmp x0, 0x30\r
+ bne reg1_error_loop\r
+ fmov x0, d31\r
+ cmp x0, 0x00\r
+ bne reg1_error_loop\r
+\r
+ /* Restore the registers clobbered by the test. */\r
+ ldp x0, x1, [sp], #0x10\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ stp x0, x1, [sp,#-0x10]!\r
+ ldr x0, =ullRegTest1LoopCounter\r
+ ldr x1, [x0]\r
+ adds x1, x1, #1\r
+ str x1, [x0]\r
+ ldp x0, x1, [sp], #0x10\r
+\r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+.type vRegTest2Implementation, %function\r
+vRegTest2Implementation:\r
+\r
+ /* Fill each general purpose register with a known value. */\r
+ mov x0, #0xff0\r
+ mov x1, #0x010\r
+ mov x2, #0x020\r
+ mov x3, #0x030\r
+ mov x4, #0x040\r
+ mov x5, #0x050\r
+ mov x6, #0x060\r
+ mov x7, #0x070\r
+ mov x8, #0x080\r
+ mov x9, #0x090\r
+ mov x10, #0x100\r
+ mov x11, #0x110\r
+ mov x12, #0x120\r
+ mov x13, #0x130\r
+ mov x14, #0x140\r
+ mov x15, #0x150\r
+ mov x16, #0x160\r
+ mov x17, #0x170\r
+ mov x18, #0x180\r
+ mov x19, #0x190\r
+ mov x20, #0x200\r
+ mov x21, #0x210\r
+ mov x22, #0x220\r
+ mov x23, #0x230\r
+ mov x24, #0x240\r
+ mov x25, #0x250\r
+ mov x26, #0x260\r
+ mov x27, #0x270\r
+ mov x28, #0x280\r
+ mov x29, #0x290\r
+ mov x30, #0x300\r
+\r
+ /* Fill each FPU register with a known value. */\r
+ fmov d0, x0\r
+ fmov d1, x1\r
+ fmov d2, x2\r
+ fmov d3, x3\r
+ fmov d4, x4\r
+ fmov d5, x5\r
+ fmov d6, x6\r
+ fmov d7, x7\r
+ fmov d8, x8\r
+ fmov d9, x9\r
+ fmov v10.d[1], x10\r
+ fmov d11, x11\r
+ fmov d12, x12\r
+ fmov d13, x13\r
+ fmov d14, x14\r
+ fmov d15, x15\r
+ fmov d16, x16\r
+ fmov d17, x17\r
+ fmov d18, x18\r
+ fmov d19, x19\r
+ fmov d20, x20\r
+ fmov d21, x21\r
+ fmov d22, x22\r
+ fmov d23, x23\r
+ fmov d24, x24\r
+ fmov d25, x25\r
+ fmov d26, x26\r
+ fmov v27.d[1], x27\r
+ fmov d28, x28\r
+ fmov d29, x29\r
+ fmov d30, x30\r
+ fmov d31, x0\r
+\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+reg2_loop:\r
+\r
+ /* Test each general purpose register to check that it still contains the\r
+ expected known value, jumping to reg2_error_loop if any register contains\r
+ an unexpected value. */\r
+ cmp x0, #0xFF0\r
+ bne reg2_error_loop\r
+ cmp x1, #0x010\r
+ bne reg2_error_loop\r
+ cmp x2, #0x020\r
+ bne reg2_error_loop\r
+ cmp x3, #0x030\r
+ bne reg2_error_loop\r
+ cmp x4, #0x040\r
+ bne reg2_error_loop\r
+ cmp x5, #0x050\r
+ bne reg2_error_loop\r
+ cmp x6, #0x060\r
+ bne reg2_error_loop\r
+ cmp x7, #0x070\r
+ bne reg2_error_loop\r
+ cmp x8, #0x080\r
+ bne reg2_error_loop\r
+ cmp x9, #0x090\r
+ bne reg2_error_loop\r
+ cmp x10, #0x100\r
+ bne reg2_error_loop\r
+ cmp x11, #0x110\r
+ bne reg2_error_loop\r
+ cmp x12, #0x120\r
+ bne reg2_error_loop\r
+ cmp x13, #0x130\r
+ bne reg2_error_loop\r
+ cmp x14, #0x140\r
+ bne reg2_error_loop\r
+ cmp x15, #0x150\r
+ bne reg2_error_loop\r
+ cmp x16, #0x160\r
+ bne reg2_error_loop\r
+ cmp x17, #0x170\r
+ bne reg2_error_loop\r
+ cmp x18, #0x180\r
+ bne reg2_error_loop\r
+ cmp x19, #0x190\r
+ bne reg2_error_loop\r
+ cmp x20, #0x200\r
+ bne reg2_error_loop\r
+ cmp x21, #0x210\r
+ bne reg2_error_loop\r
+ cmp x22, #0x220\r
+ bne reg2_error_loop\r
+ cmp x23, #0x230\r
+ bne reg2_error_loop\r
+ cmp x24, #0x240\r
+ bne reg2_error_loop\r
+ cmp x25, #0x250\r
+ bne reg2_error_loop\r
+ cmp x26, #0x260\r
+ bne reg2_error_loop\r
+ cmp x27, #0x270\r
+ bne reg2_error_loop\r
+ cmp x28, #0x280\r
+ bne reg2_error_loop\r
+ cmp x29, #0x290\r
+ bne reg2_error_loop\r
+ cmp x30, #0x300\r
+ bne reg2_error_loop\r
+\r
+ /* Check every floating point register to ensure it contains the expected\r
+ value. First save the registers clobbered by the test. */\r
+ stp x0, x1, [sp,#-0x10]!\r
+\r
+ fmov x0, d0\r
+ cmp x0, 0xff0\r
+ bne reg1_error_loop\r
+ fmov x0, d1\r
+ cmp x0, 0x010\r
+ bne reg1_error_loop\r
+ fmov x0, d2\r
+ cmp x0, 0x020\r
+ bne reg1_error_loop\r
+ fmov x0, d3\r
+ cmp x0, 0x030\r
+ bne reg1_error_loop\r
+ fmov x0, d4\r
+ cmp x0, 0x040\r
+ bne reg1_error_loop\r
+ fmov x0, d5\r
+ cmp x0, 0x050\r
+ bne reg1_error_loop\r
+ fmov x0, d6\r
+ cmp x0, 0x060\r
+ bne reg1_error_loop\r
+ fmov x0, d7\r
+ cmp x0, 0x070\r
+ bne reg1_error_loop\r
+ fmov x0, d8\r
+ cmp x0, 0x080\r
+ bne reg1_error_loop\r
+ fmov x0, d9\r
+ cmp x0, 0x090\r
+ bne reg1_error_loop\r
+ fmov x0, v10.d[1]\r
+ cmp x0, 0x100\r
+ bne reg1_error_loop\r
+ fmov x0, d11\r
+ cmp x0, 0x110\r
+ bne reg1_error_loop\r
+ fmov x0, d12\r
+ cmp x0, 0x120\r
+ bne reg1_error_loop\r
+ fmov x0, d13\r
+ cmp x0, 0x130\r
+ bne reg1_error_loop\r
+ fmov x0, d14\r
+ cmp x0, 0x140\r
+ bne reg1_error_loop\r
+ fmov x0, d15\r
+ cmp x0, 0x150\r
+ bne reg1_error_loop\r
+ fmov x0, d16\r
+ cmp x0, 0x160\r
+ bne reg1_error_loop\r
+ fmov x0, d17\r
+ cmp x0, 0x170\r
+ bne reg1_error_loop\r
+ fmov x0, d18\r
+ cmp x0, 0x180\r
+ bne reg1_error_loop\r
+ fmov x0, d19\r
+ cmp x0, 0x190\r
+ bne reg1_error_loop\r
+ fmov x0, d20\r
+ cmp x0, 0x200\r
+ bne reg1_error_loop\r
+ fmov x0, d21\r
+ cmp x0, 0x210\r
+ bne reg1_error_loop\r
+ fmov x0, d22\r
+ cmp x0, 0x220\r
+ bne reg1_error_loop\r
+ fmov x0, d23\r
+ cmp x0, 0x230\r
+ bne reg1_error_loop\r
+ fmov x0, d24\r
+ cmp x0, 0x240\r
+ bne reg1_error_loop\r
+ fmov x0, d25\r
+ cmp x0, 0x250\r
+ bne reg1_error_loop\r
+ fmov x0, d26\r
+ cmp x0, 0x260\r
+ bne reg1_error_loop\r
+ fmov x0, v27.d[1]\r
+ cmp x0, 0x270\r
+ bne reg1_error_loop\r
+ fmov x0, d28\r
+ cmp x0, 0x280\r
+ bne reg1_error_loop\r
+ fmov x0, d29\r
+ cmp x0, 0x290\r
+ bne reg1_error_loop\r
+ fmov x0, d30\r
+ cmp x0, 0x300\r
+ bne reg1_error_loop\r
+ fmov x0, d31\r
+ cmp x0, 0xff0\r
+ bne reg1_error_loop\r
+\r
+ /* Restore the registers clobbered by the test. */\r
+ ldp x0, x1, [sp], #0x10\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ stp x0, x1, [sp,#-0x10]!\r
+ ldr x0, =ullRegTest2LoopCounter\r
+ ldr x1, [x0]\r
+ adds x1, x1, #1\r
+ str x1, [x0]\r
+ ldp x0, x1, [sp], #0x10\r
+\r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+\r
+ .end\r
+\r
projects / freertos / blobdiff