/*\r
- FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
\r
+ ***************************************************************************\r
>>! NOTE: The modification to the GPL is included to allow you to !<<\r
>>! distribute a combined work that includes FreeRTOS without being !<<\r
>>! obliged to provide the source code for proprietary components !<<\r
>>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
link: http://www.freertos.org/a00114.html\r
\r
- 1 tab == 4 spaces!\r
-\r
***************************************************************************\r
* *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
* *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
* *\r
***************************************************************************\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
\r
http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
engineered and independently SIL3 certified version for use in safety and\r
/*\r
* This file initialises three timers as follows:\r
*\r
- * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ\r
+ * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ\r
* standard demo tasks, which test interrupt nesting and using queues from\r
- * interrupts. Both these interrupts operate below the maximum syscall\r
- * interrupt priority.\r
+ * interrupts. As the interrupt is shared the nesting achieved is not as deep\r
+ * as normal when this test is executed, but still worth while.\r
*\r
- * Timer 2 is a much higher frequency timer that tests the nesting of interrupts\r
- * that execute above the maximum syscall interrupt priority.\r
+ * TC2 channel 0 provides a much higher frequency timer that tests the nesting\r
+ * of interrupts that don't use the FreeRTOS API. For convenience, the high\r
+ * frequency timer also keeps a count of the number of time it executes, and the\r
+ * count is used as the time base for the run time stats (which can be viewed\r
+ * through the CLI).\r
*\r
* All the timers can nest with the tick interrupt - creating a maximum\r
- * interrupt nesting depth of 4.\r
+ * interrupt nesting depth of 3 (normally 4, if the first two timers used\r
+ * separate interrupts).\r
*\r
- * For convenience, the high frequency timer is also used to provide the time\r
- * base for the run time stats.\r
*/\r
\r
/* Scheduler includes. */\r
#include "IntQueueTimer.h"\r
#include "IntQueue.h"\r
\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
/* The frequencies at which the first two timers expire are slightly offset to\r
-ensure they don't remain synchronised. The frequency of the interrupt that\r
-operates above the max syscall interrupt priority is 10 times faster so really\r
-hammers the interrupt entry and exit code. */\r
-#define tmrTIMERS_USED 3\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_1_FREQUENCY ( 2001UL )\r
+#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
\r
-/*-----------------------------------------------------------*/\r
+/* The channels used in TC0 for generating the three interrupts. */\r
+#define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */\r
\r
-/*\r
- * The single interrupt service routines that is used to service all three\r
- * timers.\r
- */\r
-static void prvTimerHandler( void *CallBackRef );\r
+/* The bit within the RC_SR register that indicates an RC compare. */\r
+#define tmrRC_COMPARE ( 1UL << 4UL )\r
\r
+/* The high frequency interrupt given the highest priority or all. The priority\r
+of the lower frequency timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY 1\r
+#define tmrHIGHER_PRIORITY 5\r
/*-----------------------------------------------------------*/\r
\r
+/* Handlers for the two timer peripherals - two channels are used in the TC0\r
+timer. */\r
+static void prvTC0_Handler( void );\r
+static void prvTC1_Handler( void );\r
+\r
/* Used to provide a means of ensuring the intended interrupt nesting depth is\r
actually being reached. */\r
extern uint32_t ulPortInterruptNesting;\r
\r
void vInitialiseTimerForIntQueueTest( void )\r
{\r
+const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;\r
+\r
+ /* Enable the TC clocks. */\r
+ PMC->PMC_PCER0 = 1 << ID_TC0;\r
+ PMC->PMC_PCER0 = 1 << ID_TC1;\r
+\r
+ /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger\r
+ on RC compare. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_0_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger\r
+ on RC compare. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = BOARD_MCK / ( tmrTIMER_1_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on\r
+ RC compare. */\r
+ TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = BOARD_MCK / ( tmrTIMER_2_FREQUENCY * ulDivider );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Enable interrupts and start the timers. */\r
+ IRQ_ConfigureIT( ID_TC0, tmrLOWER_PRIORITY, prvTC0_Handler );\r
+ IRQ_ConfigureIT( ID_TC1, tmrHIGHER_PRIORITY, prvTC1_Handler );\r
+ IRQ_EnableIT( ID_TC0 );\r
+ IRQ_EnableIT( ID_TC1 );\r
+ TC_Start( TC0, tmrTC0_CHANNEL_0 );\r
+ TC_Start( TC0, tmrTC0_CHANNEL_1 );\r
+ TC_Start( TC1, tmrTC1_CHANNEL_0 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvTimerHandler( void *pvCallBackRef )\r
+static void prvTC0_Handler( void )\r
{\r
- ( void ) pvCallBackRef;\r
+ /* Read will clear the status bit. */\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTC1_Handler( void )\r
+{\r
+volatile uint32_t ulDummy;\r
+\r
+ /* Dummy read to clear status bit. */\r
+ ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR;\r
+\r
+ /* Latch the maximum nesting count. */\r
+ if( ulPortInterruptNesting > ulMaxRecordedNesting )\r
+ {\r
+ ulMaxRecordedNesting = ulPortInterruptNesting;\r
+ }\r
+\r
+ /* Keep a count of the number of interrupts to use as a time base for the\r
+ run-time stats. */\r
+ ulHighFrequencyTimerCounts++;\r
}\r
\r
projects / freertos / blobdiff