Carry on working on SAMA5D3 demo:

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D3x_Xplained_IAR / Full_Demo / main_full.c

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c
index eb60eed62c869f7b1070220fd74e06c798d1ff71..1eff84509612a2ad97c9fb1b8f0c9800e1a91c72 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c
@@ -233,7 +233,7 @@ void main_full( void )
        /* Start all the other standard demo/test tasks.  They have not particular\r
        functionality, but do demonstrate how to use the FreeRTOS API and test the\r
        kernel port. */\r
-//_RB_ vStartInterruptQueueTasks();\r
+       vStartInterruptQueueTasks();\r
        vStartDynamicPriorityTasks();\r
        vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
        vCreateBlockTimeTasks();\r
@@ -251,7 +251,7 @@ void main_full( void )
        vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
 \r
        /* Register the standard CLI commands. */\r
-//     vRegisterSampleCLICommands();\r
+       vRegisterSampleCLICommands();\r
 \r
        /* Create the register check tasks, as described at the top of this     file */\r
        xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
@@ -313,7 +313,7 @@ unsigned long ulErrorFound = pdFALSE;
                that they are all still running, and that none have detected an error. */\r
                if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
                {\r
-//_RB_                 ulErrorFound = pdTRUE;\r
+                       ulErrorFound = pdTRUE;\r
                }\r
 \r
                if( xAreMathsTaskStillRunning() != pdTRUE )\r
@@ -455,9 +455,41 @@ static void prvRegTestTaskEntry2( void *pvParameters )
 \r
 static void prvPseudoRandomiser( void *pvParameters )\r
 {\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ), ulIBit = ( 1UL << 7UL );\r
 volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
 \r
+       /* A few minor port tests before entering the randomiser loop.\r
+\r
+       At this point interrupts should be enabled. */\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
+       /* The CPU does not have an interrupt mask register, so critical sections\r
+       have to globally disable interrupts.  Therefore entering a critical section\r
+       should leave the I bit set. */\r
+       taskENTER_CRITICAL();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+       /* Nest the critical sections. */\r
+       taskENTER_CRITICAL();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+       /* After yielding the I bit should still be set.  Note yielding is possible\r
+       in a critical section as each task maintains its own critical section\r
+       nesting count so some tasks are in critical sections and others are not -\r
+       however this is *not* something task code should do! */\r
+       taskYIELD();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+       /* The I bit should not be cleared again until both critical sections have\r
+       been exited. */\r
+       taskEXIT_CRITICAL();\r
+       taskYIELD();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+       taskEXIT_CRITICAL();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+       taskYIELD();\r
+       configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
        /* This task does nothing other than ensure there is a little bit of\r
        disruption in the scheduling pattern of the other tasks.  Normally this is\r
        done by generating interrupts at pseudo random times. */\r