Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the...

[freertos] / FreeRTOS / Demo / CORTEX_A9_Zynq_ZC702 / RTOSDemo_bsp / ps7_cortexa9_0 / include / xparameters.h

diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h
index 06f11000051e82ac1193efca2065c5382cff7929..cfa88870ecc7ae4425d6fd77b01b22c28191e748 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -1,5 +1,8 @@
+#ifndef XPARAMETERS_H   /* prevent circular inclusions */\r
+#define XPARAMETERS_H   /* by using protection macros */\r
+\r
 /* Definition for CPU ID */\r
-#define XPAR_CPU_ID 0\r
+#define XPAR_CPU_ID 0U\r
 \r
 /* Definitions for peripheral PS7_CORTEXA9_0 */\r
 #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687\r
@@ -20,6 +23,14 @@
 \r
 /******************************************************************/\r
 \r
+/* Platform specific definitions */\r
+#define PLATFORM_ZYNQ\r
+ \r
+/* Definitions for sleep timer configuration */\r
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER\r
+ \r
+ \r
+/******************************************************************/\r
 /* Definitions for driver CANPS */\r
 #define XPAR_XCANPS_NUM_INSTANCES 1\r
 \r
@@ -50,20 +61,20 @@
 /******************************************************************/\r
 \r
 /* Definitions for driver DEVCFG */\r
-#define XPAR_XDCFG_NUM_INSTANCES 1\r
+#define XPAR_XDCFG_NUM_INSTANCES 1U\r
 \r
 /* Definitions for peripheral PS7_DEV_CFG_0 */\r
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0\r
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000\r
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF\r
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U\r
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U\r
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PS7_DEV_CFG_0 */\r
 #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID\r
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000\r
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF\r
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U\r
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU\r
 \r
 \r
 /******************************************************************/\r
@@ -112,10 +123,12 @@
 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5\r
 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8\r
 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50\r
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0\r
 \r
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PS7_ETHERNET_0 */\r
 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID\r
 #define XPAR_XEMACPS_0_BASEADDR 0xE000B000\r
@@ -127,6 +140,7 @@
 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5\r
 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8\r
 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50\r
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0\r
 \r
 \r
 /******************************************************************/\r
@@ -275,6 +289,7 @@
 #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF\r
 #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000\r
 #define XPAR_PS7_QSPI_0_QSPI_MODE 0\r
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2\r
 \r
 \r
 /******************************************************************/\r
@@ -285,27 +300,28 @@
 #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF\r
 #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000\r
 #define XPAR_XQSPIPS_0_QSPI_MODE 0\r
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Definitions for driver SCUGIC */\r
-#define XPAR_XSCUGIC_NUM_INSTANCES 1\r
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U\r
 \r
 /* Definitions for peripheral PS7_SCUGIC_0 */\r
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0\r
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100\r
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF\r
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000\r
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U\r
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U\r
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU\r
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PS7_SCUGIC_0 */\r
-#define XPAR_SCUGIC_0_DEVICE_ID 0\r
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100\r
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF\r
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000\r
+#define XPAR_SCUGIC_0_DEVICE_ID 0U\r
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U\r
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU\r
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U\r
 \r
 \r
 /******************************************************************/\r
@@ -358,10 +374,14 @@
 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000\r
 #define XPAR_PS7_SD_0_HAS_CD 1\r
 #define XPAR_PS7_SD_0_HAS_WP 1\r
+#define XPAR_PS7_SD_0_BUS_WIDTH 0\r
+#define XPAR_PS7_SD_0_MIO_BANK 0\r
+#define XPAR_PS7_SD_0_HAS_EMIO 0\r
 \r
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PS7_SD_0 */\r
 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID\r
 #define XPAR_XSDPS_0_BASEADDR 0xE0100000\r
@@ -369,45 +389,48 @@
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000\r
 #define XPAR_XSDPS_0_HAS_CD 1\r
 #define XPAR_XSDPS_0_HAS_WP 1\r
+#define XPAR_XSDPS_0_BUS_WIDTH 0\r
+#define XPAR_XSDPS_0_MIO_BANK 0\r
+#define XPAR_XSDPS_0_HAS_EMIO 0\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Definitions for driver TTCPS */\r
-#define XPAR_XTTCPS_NUM_INSTANCES 3\r
+#define XPAR_XTTCPS_NUM_INSTANCES 3U\r
 \r
 /* Definitions for peripheral PS7_TTC_0 */\r
-#define XPAR_PS7_TTC_0_DEVICE_ID 0\r
-#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000\r
-#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0\r
-#define XPAR_PS7_TTC_1_DEVICE_ID 1\r
-#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004\r
-#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0\r
-#define XPAR_PS7_TTC_2_DEVICE_ID 2\r
-#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008\r
-#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0\r
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U\r
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U\r
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U\r
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U\r
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U\r
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U\r
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PS7_TTC_0 */\r
 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID\r
-#define XPAR_XTTCPS_0_BASEADDR 0xF8001000\r
-#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U\r
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID\r
-#define XPAR_XTTCPS_1_BASEADDR 0xF8001004\r
-#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U\r
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID\r
-#define XPAR_XTTCPS_2_BASEADDR 0xF8001008\r
-#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115\r
-#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U\r
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U\r
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /******************************************************************/\r
@@ -473,3 +496,4 @@
 \r
 /******************************************************************/\r
 \r
+#endif  /* end of protection macro */\r