Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full float...

[freertos] / FreeRTOS / Demo / CORTEX_A9_Zynq_ZC702 / RTOSDemo_bsp / ps7_cortexa9_0 / libsrc / uartps_v3_1 / src / xuartps_g.c

diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c
index f7deaf320f727a134f1dbbfbaade537ecfbc1a68..d0ed617c486e65101625ec45559d3170aa9ed582 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c
@@ -5,7 +5,7 @@
 * Version: \r
 * DO NOT EDIT.\r
 *\r
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*\r
 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
 *of this software and associated documentation files (the Software), to deal\r
 *in the Software without restriction, including without limitation the rights\r