Add files necessary to create a Pearl Gecko build configuration in the new EFM32...

[freertos] / FreeRTOS / Demo / CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio / Source / SilLabs_Code / emlib / inc / em_mpu.h

diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/emlib/inc/em_mpu.h b/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/emlib/inc/em_mpu.h
index 300a98984f6deefa66e2a50faf9a29e0274d14ce..689efa1e08dc66c14530b09a5d00916907834632 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/emlib/inc/em_mpu.h
+++ b/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/emlib/inc/em_mpu.h
@@ -1,10 +1,10 @@
 /***************************************************************************//**\r
  * @file em_mpu.h\r
  * @brief Memory protection unit (MPU) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
  *******************************************************************************\r
  * @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
  *******************************************************************************\r
  *\r
  * Permission is granted to anyone to use this software for any purpose,\r
@@ -30,9 +30,8 @@
  *\r
  ******************************************************************************/\r
 \r
-\r
-#ifndef __SILICON_LABS_EM_MPU_H_\r
-#define __SILICON_LABS_EM_MPU_H_\r
+#ifndef __SILICON_LABS_EM_MPU_H__\r
+#define __SILICON_LABS_EM_MPU_H__\r
 \r
 #include "em_device.h"\r
 \r
@@ -139,54 +138,54 @@ typedef struct
 } MPU_RegionInit_TypeDef;\r
 \r
 /** Default configuration of MPU region init structure for flash memory.     */\r
-#define MPU_INIT_FLASH_DEFAULT                                  \\r
-  {                                                             \\r
-    true,                   /* Enable MPU region.            */ \\r
-    0,                      /* MPU Region number.            */ \\r
-    FLASH_MEM_BASE,         /* Flash base address.           */ \\r
-    mpuRegionSize1Mb,       /* Size - Set to max. */ \\r
-    mpuRegionApFullAccess,  /* Access permissions.           */ \\r
-    false,                  /* Execution allowed.            */ \\r
-    false,                  /* Not shareable.                */ \\r
-    true,                   /* Cacheable.                    */ \\r
-    false,                  /* Not bufferable.               */ \\r
-    0,                      /* No subregions.                */ \\r
-    0                       /* No TEX attributes.            */ \\r
-  }\r
+#define MPU_INIT_FLASH_DEFAULT                                \\r
+{                                                             \\r
+  true,                   /* Enable MPU region.            */ \\r
+  0,                      /* MPU Region number.            */ \\r
+  FLASH_MEM_BASE,         /* Flash base address.           */ \\r
+  mpuRegionSize1Mb,       /* Size - Set to max. */            \\r
+  mpuRegionApFullAccess,  /* Access permissions.           */ \\r
+  false,                  /* Execution allowed.            */ \\r
+  false,                  /* Not shareable.                */ \\r
+  true,                   /* Cacheable.                    */ \\r
+  false,                  /* Not bufferable.               */ \\r
+  0,                      /* No subregions.                */ \\r
+  0                       /* No TEX attributes.            */ \\r
+}\r
 \r
 \r
 /** Default configuration of MPU region init structure for sram memory.      */\r
-#define MPU_INIT_SRAM_DEFAULT                                   \\r
-  {                                                             \\r
-    true,                   /* Enable MPU region.            */ \\r
-    1,                      /* MPU Region number.            */ \\r
-    RAM_MEM_BASE,           /* SRAM base address.            */ \\r
-    mpuRegionSize128Kb,     /* Size - Set to max. */ \\r
-    mpuRegionApFullAccess,  /* Access permissions.           */ \\r
-    false,                  /* Execution allowed.            */ \\r
-    true,                   /* Shareable.                    */ \\r
-    true,                   /* Cacheable.                    */ \\r
-    false,                  /* Not bufferable.               */ \\r
-    0,                      /* No subregions.                */ \\r
-    0                       /* No TEX attributes.            */ \\r
-  }\r
+#define MPU_INIT_SRAM_DEFAULT                                 \\r
+{                                                             \\r
+  true,                   /* Enable MPU region.            */ \\r
+  1,                      /* MPU Region number.            */ \\r
+  RAM_MEM_BASE,           /* SRAM base address.            */ \\r
+  mpuRegionSize128Kb,     /* Size - Set to max. */            \\r
+  mpuRegionApFullAccess,  /* Access permissions.           */ \\r
+  false,                  /* Execution allowed.            */ \\r
+  true,                   /* Shareable.                    */ \\r
+  true,                   /* Cacheable.                    */ \\r
+  false,                  /* Not bufferable.               */ \\r
+  0,                      /* No subregions.                */ \\r
+  0                       /* No TEX attributes.            */ \\r
+}\r
 \r
 \r
 /** Default configuration of MPU region init structure for onchip peripherals.*/\r
-#define MPU_INIT_PERIPHERAL_DEFAULT                             \\r
-  {                                                             \\r
-    true,                   /* Enable MPU region.            */ \\r
-    0,                      /* MPU Region number.            */ \\r
-    0,                      /* Region base address.          */ \\r
-    mpuRegionSize32b,       /* Size - Set to minimum         */ \\r
-    mpuRegionApFullAccess,  /* Access permissions.           */ \\r
-    true,                   /* Execution not allowed.        */ \\r
-    true,                   /* Shareable.                    */ \\r
-    false,                  /* Not cacheable.                */ \\r
-    true,                   /* Bufferable.                   */ \\r
-    0,                      /* No subregions.                */ \\r
-    0                       /* No TEX attributes.            */ \\r
-  }\r
+#define MPU_INIT_PERIPHERAL_DEFAULT                           \\r
+{                                                             \\r
+  true,                   /* Enable MPU region.            */ \\r
+  0,                      /* MPU Region number.            */ \\r
+  0,                      /* Region base address.          */ \\r
+  mpuRegionSize32b,       /* Size - Set to minimum         */ \\r
+  mpuRegionApFullAccess,  /* Access permissions.           */ \\r
+  true,                   /* Execution not allowed.        */ \\r
+  true,                   /* Shareable.                    */ \\r
+  false,                  /* Not cacheable.                */ \\r
+  true,                   /* Bufferable.                   */ \\r
+  0,                      /* No subregions.                */ \\r
+  0                       /* No TEX attributes.            */ \\r
+}\r
 \r
 \r
 /*******************************************************************************\r
@@ -221,9 +220,9 @@ __STATIC_INLINE void MPU_Disable(void)
  ******************************************************************************/\r
 __STATIC_INLINE void MPU_Enable(uint32_t flags)\r
 {\r
-  EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk |\r
-                         MPU_CTRL_HFNMIENA_Msk |\r
-                         MPU_CTRL_ENABLE_Msk)));\r
+  EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk\r
+                         | MPU_CTRL_HFNMIENA_Msk\r
+                         | MPU_CTRL_ENABLE_Msk)));\r
 \r
   MPU->CTRL   = flags | MPU_CTRL_ENABLE_Msk;     /* Enable the MPU */\r
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;       /* Enable fault exceptions */\r
@@ -239,4 +238,4 @@ __STATIC_INLINE void MPU_Enable(uint32_t flags)
 \r
 #endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */\r
 \r
-#endif /* __SILICON_LABS_EM_MPU_H_ */\r
+#endif /* __SILICON_LABS_EM_MPU_H__ */\r