/***************************************************************************//**\r
* @file em_timer.h\r
* @brief Timer/counter (TIMER) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_TIMER_H_\r
-#define __SILICON_LABS_EM_TIMER_H_\r
+#ifndef __SILICON_LABS_EM_TIMER_H__\r
+#define __SILICON_LABS_EM_TIMER_H__\r
\r
#include "em_device.h"\r
#if defined(TIMER_COUNT) && (TIMER_COUNT > 0)\r
#elif (TIMER_COUNT == 2)\r
#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || ((ref) == TIMER1))\r
#elif (TIMER_COUNT == 3)\r
-#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || \\r
- ((ref) == TIMER1) || \\r
- ((ref) == TIMER2))\r
+#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \\r
+ || ((ref) == TIMER1) \\r
+ || ((ref) == TIMER2))\r
#elif (TIMER_COUNT == 4)\r
-#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || \\r
- ((ref) == TIMER1) || \\r
- ((ref) == TIMER2) || \\r
- ((ref) == TIMER3))\r
+#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \\r
+ || ((ref) == TIMER1) \\r
+ || ((ref) == TIMER2) \\r
+ || ((ref) == TIMER3))\r
#else\r
-#error Undefined number of timers.\r
+#error "Undefined number of timers."\r
#endif\r
\r
/** Validation of TIMER compare/capture channel number */\r
+#if defined(_SILICON_LABS_32B_PLATFORM_1)\r
#define TIMER_CH_VALID(ch) ((ch) < 3)\r
+#elif defined(_SILICON_LABS_32B_PLATFORM_2)\r
+#define TIMER_CH_VALID(ch) ((ch) < 4)\r
+#else\r
+#error "Unknown platform. Undefined number of channels."\r
+#endif\r
\r
/** @endcond */\r
\r
timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
timerPRSSELCh3 = _TIMER_CC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH4 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH4)\r
timerPRSSELCh4 = _TIMER_CC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH5 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH5)\r
timerPRSSELCh5 = _TIMER_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH6 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH6)\r
timerPRSSELCh6 = _TIMER_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH7 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH7)\r
timerPRSSELCh7 = _TIMER_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH8 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH8)\r
timerPRSSELCh8 = _TIMER_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH9 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH9)\r
timerPRSSELCh9 = _TIMER_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH10 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH10)\r
timerPRSSELCh10 = _TIMER_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH11 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH11)\r
timerPRSSELCh11 = _TIMER_CC_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */\r
#endif\r
} TIMER_PRSSEL_TypeDef;\r
\r
-#ifdef _TIMER_DTFC_DTFA_NONE\r
+#if defined(_TIMER_DTFC_DTFA_NONE)\r
/** DT (Dead Time) Fault Actions. */\r
typedef enum\r
{\r
/** Clock selection. */\r
TIMER_ClkSel_TypeDef clkSel;\r
\r
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )\r
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)\r
/** 2x Count mode, counter increments/decrements by 2, meant for PWN mode. */\r
bool count2x;\r
\r
} TIMER_Init_TypeDef;\r
\r
/** Default config for TIMER init structure. */\r
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )\r
-#define TIMER_INIT_DEFAULT \\r
- { true, /* Enable timer when init complete. */ \\r
- false, /* Stop counter during debug halt. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
- false, /* Not 2x count mode. */ \\r
- false, /* No ATI. */ \\r
- timerInputActionNone, /* No action on falling input edge. */ \\r
- timerInputActionNone, /* No action on rising input edge. */ \\r
- timerModeUp, /* Up-counting. */ \\r
- false, /* Do not clear DMA requests when DMA channel is active. */ \\r
- false, /* Select X2 quadrature decode mode (if used). */ \\r
- false, /* Disable one shot. */ \\r
- false /* Not started/stopped/reloaded by other timers. */ \\r
- }\r
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)\r
+#define TIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
+ false, /* Not 2x count mode. */ \\r
+ false, /* No ATI. */ \\r
+ timerInputActionNone, /* No action on falling input edge. */ \\r
+ timerInputActionNone, /* No action on rising input edge. */ \\r
+ timerModeUp, /* Up-counting. */ \\r
+ false, /* Do not clear DMA requests when DMA channel is active. */ \\r
+ false, /* Select X2 quadrature decode mode (if used). */ \\r
+ false, /* Disable one shot. */ \\r
+ false /* Not started/stopped/reloaded by other timers. */ \\r
+}\r
#else\r
-#define TIMER_INIT_DEFAULT \\r
- { true, /* Enable timer when init complete. */ \\r
- false, /* Stop counter during debug halt. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
- timerInputActionNone, /* No action on falling input edge. */ \\r
- timerInputActionNone, /* No action on rising input edge. */ \\r
- timerModeUp, /* Up-counting. */ \\r
- false, /* Do not clear DMA requests when DMA channel is active. */ \\r
- false, /* Select X2 quadrature decode mode (if used). */ \\r
- false, /* Disable one shot. */ \\r
- false /* Not started/stopped/reloaded by other timers. */ \\r
- }\r
+#define TIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
+ timerInputActionNone, /* No action on falling input edge. */ \\r
+ timerInputActionNone, /* No action on rising input edge. */ \\r
+ timerModeUp, /* Up-counting. */ \\r
+ false, /* Do not clear DMA requests when DMA channel is active. */ \\r
+ false, /* Select X2 quadrature decode mode (if used). */ \\r
+ false, /* Disable one shot. */ \\r
+ false /* Not started/stopped/reloaded by other timers. */ \\r
+}\r
#endif\r
\r
/** TIMER compare/capture initialization structure. */\r
} TIMER_InitCC_TypeDef;\r
\r
/** Default config for TIMER compare/capture init structure. */\r
-#define TIMER_INITCC_DEFAULT \\r
- { timerEventEveryEdge, /* Event on every capture. */ \\r
- timerEdgeRising, /* Input capture edge on rising edge. */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerOutputActionNone, /* No action on underflow. */ \\r
- timerOutputActionNone, /* No action on overflow. */ \\r
- timerOutputActionNone, /* No action on match. */ \\r
- timerCCModeOff, /* Disable compare/capture channel. */ \\r
- false, /* Disable filter. */ \\r
- false, /* Select TIMERnCCx input. */ \\r
- false, /* Clear output when counter disabled. */ \\r
- false /* Do not invert output. */ \\r
- }\r
+#define TIMER_INITCC_DEFAULT \\r
+{ \\r
+ timerEventEveryEdge, /* Event on every capture. */ \\r
+ timerEdgeRising, /* Input capture edge on rising edge. */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerOutputActionNone, /* No action on underflow. */ \\r
+ timerOutputActionNone, /* No action on overflow. */ \\r
+ timerOutputActionNone, /* No action on match. */ \\r
+ timerCCModeOff, /* Disable compare/capture channel. */ \\r
+ false, /* Disable filter. */ \\r
+ false, /* Select TIMERnCCx input. */ \\r
+ false, /* Clear output when counter disabled. */ \\r
+ false /* Do not invert output. */ \\r
+}\r
\r
-#ifdef _TIMER_DTCTRL_MASK\r
+#if defined(_TIMER_DTCTRL_MASK)\r
/** TIMER Dead Time Insertion (DTI) initialization structure. */\r
typedef struct\r
{\r
\r
\r
/** Default config for TIMER DTI init structure. */\r
-#define TIMER_INITDTI_DEFAULT \\r
- { true, /* Enable the DTI. */ \\r
- false, /* CC[0|1|2] outputs are active high. */ \\r
- false, /* CDTI[0|1|2] outputs are not inverted. */ \\r
- false, /* No auto restart when debugger exits. */ \\r
- false, /* No PRS source selected. */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- 0, /* No rise time. */ \\r
- 0, /* No fall time. */ \\r
- TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\\r
- true, /* Enable core lockup as fault source */ \\r
- true, /* Enable debugger as fault source */ \\r
- false, /* Disable PRS fault source 0 */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- false, /* Disable PRS fault source 1 */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerDtiFaultActionInactive, /* No fault action. */ \\r
- }\r
+#define TIMER_INITDTI_DEFAULT \\r
+{ \\r
+ true, /* Enable the DTI. */ \\r
+ false, /* CC[0|1|2] outputs are active high. */ \\r
+ false, /* CDTI[0|1|2] outputs are not inverted. */ \\r
+ false, /* No auto restart when debugger exits. */ \\r
+ false, /* No PRS source selected. */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ 0, /* No rise time. */ \\r
+ 0, /* No fall time. */ \\r
+ TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\\r
+ true, /* Enable core lockup as fault source */ \\r
+ true, /* Enable debugger as fault source */ \\r
+ false, /* Disable PRS fault source 0 */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ false, /* Disable PRS fault source 1 */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerDtiFaultActionInactive, /* No fault action. */ \\r
+}\r
#endif /* _TIMER_DTCTRL_MASK */\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)\r
{\r
- return(timer->CC[ch].CCV);\r
+ return timer->CC[ch].CCV;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->CNT);\r
+ return timer->CNT;\r
}\r
\r
\r
unsigned int ch,\r
const TIMER_InitCC_TypeDef *init);\r
\r
-#ifdef _TIMER_DTCTRL_MASK\r
+#if defined(_TIMER_DTCTRL_MASK)\r
void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init);\r
\r
/***************************************************************************//**\r
__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)\r
{\r
EFM_ASSERT(TIMER0 == timer);\r
- return(timer->DTFAULT);\r
+ return timer->DTFAULT;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)\r
{\r
- timer->IEN &= ~(flags);\r
+ timer->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->IF);\r
+ return timer->IF;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)\r
{\r
- uint32_t tmp;\r
+ uint32_t ien;\r
\r
/* Store TIMER->IEN in temporary variable in order to define explicit order\r
* of volatile accesses. */\r
- tmp = timer->IEN;\r
+ ien = timer->IEN;\r
\r
/* Bitwise AND of pending and enabled interrupts */\r
- return timer->IF & tmp;\r
+ return timer->IF & ien;\r
}\r
\r
\r
timer->IFS = flags;\r
}\r
\r
-#ifdef TIMER_DTLOCK_LOCKKEY_LOCK\r
+#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK)\r
/***************************************************************************//**\r
* @brief\r
* Lock some of the TIMER registers in order to protect them from being\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->TOP);\r
+ return timer->TOP;\r
}\r
\r
\r
}\r
\r
\r
-#ifdef TIMER_DTLOCK_LOCKKEY_UNLOCK\r
+#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)\r
/***************************************************************************//**\r
* @brief\r
* Unlock the TIMER so that writing to locked registers again is possible.\r
#endif\r
\r
#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_TIMER_H_ */\r
+#endif /* __SILICON_LABS_EM_TIMER_H__ */\r
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