/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/* Standard includes. */\r
#include <limits.h>\r
\r
/* Library includes. */\r
#include "common_lib.h"\r
+#include "peripheral_library/interrupt/interrupt.h"\r
+#include "peripheral_library/basic_timer/btimer.h"\r
\r
/* This file contains functions that will override the default implementations\r
in the RTOS port layer. Therefore only build this file if the low power demo\r
allowing an additional paths through the code to be tested. */\r
#define lpINCLUDE_TEST_TIMER 0\r
\r
-/* Some registers are accessed directly as the library is not compatible with\r
-all the compilers used. */\r
+/* Registers and bits required to use the htimer in aggregated mode. */\r
#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )\r
#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )\r
#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )\r
#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )\r
-#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )\r
+#define lpEC_GIRQ17_SOURCE ( * ( volatile uint32_t * ) 0x4000C0B4 )\r
+#define lpEC_GIRQ17_ENABLE_CLEAR ( * ( volatile uint32_t * ) 0x4000C0C0 )\r
+#define lpBLOCK_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000c200 )\r
+#define lpGIRQ17_BIT_HTIMER ( 1UL << 20UL )\r
+#define lpHTIMER_GIRQ_BLOCK ( 1Ul << 17UL )\r
+\r
+/* Registers and bits required to use btimer 0 in aggregated mode. */\r
+#define lpGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+#define lpEC_GIRQ23_SOURCE ( * ( volatile uint32_t * ) 0x4000C12C )\r
+#define lpEC_GIRQ23_ENABLE_CLEAR ( * ( volatile uint32_t * ) 0x4000C138 )\r
+#define lpGIRQ23_BIT_TIMER0 ( 1UL << 0UL )\r
+#define lpBTIMER_GIRQ_BLOCK ( 1UL << 23UL )\r
\r
/*\r
* The low power demo does not use the SysTick, so override the\r
\r
/*-----------------------------------------------------------*/\r
\r
-void NVIC_Handler_HIB_TMR( void )\r
+void NVIC_Handler_GIRQ17( void )\r
{\r
- lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
+ /* The low power demo is using aggregated interrupts, so although in the\r
+ demo the htimer is the only peripheral that will generate interrupts on\r
+ this vector, in a real application it would be necessary to first check the\r
+ interrupt source. */\r
+ if( ( lpEC_GIRQ17_SOURCE & lpGIRQ17_BIT_HTIMER ) != 0 )\r
+ {\r
+ /* The htimer interrupted. Clear the interrupt. */\r
+ lpEC_GIRQ17_SOURCE = lpGIRQ17_BIT_HTIMER;\r
+ lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulHighResolutionReloadValue;\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
+ /* The CPU woke because of a tick. */\r
+ ulTickFlag = pdTRUE;\r
+ }\r
+ else\r
{\r
- /* A context switch is required. Context switching is performed in\r
- the PendSV interrupt. Pend the PendSV interrupt. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ /* Don't expect any other interrupts to use this vector in this\r
+ demo. Force an assert. */\r
+ configASSERT( lpEC_GIRQ17_SOURCE == 0 );\r
}\r
-\r
- /* The CPU woke because of a tick. */\r
- ulTickFlag = pdTRUE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( lpINCLUDE_TEST_TIMER == 1 )\r
\r
- #define lpGIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )\r
-\r
static void prvSetupBasicTimer( void )\r
{\r
const uint8_t ucTimerChannel = 0;\r
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;\r
\r
- lpGIRQ23_ENABLE_SET = 0x03;\r
+ /* Enable btimer 0 interrupt in the aggregated GIRQ23 block. */\r
+ lpEC_GIRQ23_SOURCE = lpGIRQ23_BIT_TIMER0;\r
+ lpEC_GIRQ23_ENABLE_CLEAR = lpGIRQ23_BIT_TIMER0;\r
+ lpBLOCK_ENABLE_SET = lpBTIMER_GIRQ_BLOCK;\r
+ lpGIRQ23_ENABLE_SET = lpGIRQ23_BIT_TIMER0;\r
\r
/* To fully test the low power tick processing it is necessary to sometimes\r
bring the MCU out of its sleep state by a method other than the tick\r
purpose. */\r
btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
btimer_interrupt_status_get_clr( ucTimerChannel );\r
- enable_timer0_irq();\r
- NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );\r
- NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
- NVIC_EnableIRQ( TIMER0_IRQn );\r
+ NVIC_SetPriority( GIRQ23_IRQn, ucTimerChannel );\r
+ NVIC_ClearPendingIRQ( GIRQ23_IRQn );\r
+ NVIC_EnableIRQ( GIRQ23_IRQn );\r
btimer_start( ucTimerChannel );\r
}\r
\r
\r
void vPortSetupTimerInterrupt( void )\r
{\r
- ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
+ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
\r
/* Set up the hibernation timer to start at the value required by the\r
tick interrupt. */\r
lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION;\r
\r
- /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */\r
- lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT;\r
+ /* Enable the HTIMER interrupt in the aggregated GIR17 block. */\r
+ lpEC_GIRQ17_SOURCE = lpGIRQ17_BIT_HTIMER;\r
+ lpEC_GIRQ17_ENABLE_CLEAR = lpGIRQ17_BIT_HTIMER;\r
+ lpBLOCK_ENABLE_SET = lpHTIMER_GIRQ_BLOCK;\r
+ lpEC_GIRQ17_ENABLE_SET = lpGIRQ17_BIT_HTIMER;\r
\r
/* The hibernation timer is not an auto-reload timer, so gets reset\r
from within the ISR itself. For that reason it's interrupt is set\r
to the highest possible priority to ensure clock slippage is minimised. */\r
- NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
- NVIC_ClearPendingIRQ( HTIMER_IRQn );\r
- NVIC_EnableIRQ( HTIMER_IRQn );\r
+ NVIC_SetPriority( GIRQ17_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_ClearPendingIRQ( GIRQ17_IRQn );\r
+ NVIC_EnableIRQ( GIRQ17_IRQn );\r
\r
/* A basic timer is also started, purely for test purposes. Its only\r
purpose is to bring the CPU out of its sleep mode by an interrupt other\r
/* Allow the application to define some post sleep processing. */\r
configPOST_SLEEP_PROCESSING( xModifiableIdleTime );\r
\r
- /* Stop the hibernation timer. Again, the time the tiemr is stopped\r
+ /* Stop the hibernation timer. Again, the time the timer is stopped\r
for is accounted for as best it can be, but using the tickless mode\r
will inevitably result in some tiny drift of the time maintained by the\r
kernel with respect to calendar time. Take the count value first as\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void NVIC_Handler_TMR0( void )\r
+void NVIC_Handler_GIRQ23( void )\r
{\r
- /* This timer is used for test purposes. Its only function is to\r
- generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
- brought out of sleep by a means other than the tick interrupt. */\r
-}\r
-/*-----------------------------------------------------------*/\r
+static volatile uint32_t ulTimerCounts = 0;\r
\r
+ /* The low power demo is using aggregated interrupts, so although in the\r
+ demo btimer 0 is the only peripheral that will generate interrupts on\r
+ this vector, in a real application it would be necessary to first check the\r
+ interrupt source. */\r
+ if( ( lpEC_GIRQ23_SOURCE & lpGIRQ23_BIT_TIMER0 ) != 0 )\r
+ {\r
+ /* Btimer0 interrupted. Clear the interrupt. */\r
+ lpEC_GIRQ23_SOURCE = lpGIRQ23_BIT_TIMER0;\r
\r
-#endif /* configCREATE_LOW_POWER_DEMO */\r
+ /* This timer is used for test purposes. Its only function is to\r
+ generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
+ brought out of sleep by a means other than the tick interrupt. */\r
+ ulTimerCounts++;\r
+ }\r
+ else\r
+ {\r
+ /* Don't expect any other interrupts to use this vector in this\r
+ demo. Force an assert. */\r
+ configASSERT( lpEC_GIRQ23_SOURCE == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
+#endif /* configCREATE_LOW_POWER_DEMO == 1 */\r
projects / freertos / blobdiff