--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * Basic timer channels 0 and 1 provide the interrupts that are used with the\r
+ * IntQ standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. The interrupts use slightly different frequencies so will\r
+ * occasionally nest.\r
+ *\r
+ * Basic timer channel 2 provides a much higher frequency timer that tests the\r
+ * nesting of interrupts that don't use the FreeRTOS API.\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the\r
+ * tick interrupt does not increment the nesting count variable).\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Library includes. */\r
+#include "btimer.h"\r
+#include "interrupt.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
+#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
+\r
+/* The basic timer channels used for generating the three interrupts. */\r
+#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */\r
+\r
+/* The high frequency interrupt is given a priority above the maximum at which\r
+interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
+timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )\r
+#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )\r
+#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )\r
+\r
+/* Hardware register locations. */\r
+#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+\r
+#define tmrRECORD_NESTING_DEPTH() \\r
+ ulNestingDepth++; \\r
+ if( ulNestingDepth > ulMaxRecordedNestingDepth ) \\r
+ { \\r
+ ulMaxRecordedNestingDepth = ulNestingDepth; \\r
+ }\r
+\r
+/* Used to count the nesting depth, and record the maximum nesting depth. */\r
+volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;\r
+const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;\r
+const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
+const uint8_t ucEnable = 1;\r
+\r
+ tmrGIRQ23_ENABLE_SET = 0x03;\r
+\r
+ /* Initialise the three timers as described at the top of this file, and\r
+ enable their interrupts in the NVIC. */\r
+ btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );\r
+ interrupt_device_enable( BTMR0_IROUTE );\r
+ interrupt_device_nvic_priority_set( BTMR0_IROUTE, tmrLOWER_PRIORITY );\r
+ interrupt_device_nvic_pending_clear( BTMR0_IROUTE );\r
+ interrupt_device_nvic_enable( BTMR0_IROUTE, ucEnable );\r
+ btimer_start( tmrTIMER_CHANNEL_0 );\r
+\r
+ btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );\r
+ interrupt_device_enable( BTMR1_IROUTE );\r
+ interrupt_device_nvic_priority_set( BTMR1_IROUTE, tmrMEDIUM_PRIORITY );\r
+ interrupt_device_nvic_pending_clear( BTMR1_IROUTE );\r
+ interrupt_device_nvic_enable( BTMR1_IROUTE, ucEnable );\r
+ btimer_start( tmrTIMER_CHANNEL_1 );\r
+\r
+ btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );\r
+ interrupt_device_enable( BTMR2_IROUTE );\r
+ interrupt_device_nvic_priority_set( BTMR2_IROUTE, tmrHIGHER_PRIORITY );\r
+ interrupt_device_nvic_pending_clear( BTMR2_IROUTE );\r
+ interrupt_device_nvic_enable( BTMR2_IROUTE, ucEnable );\r
+ btimer_start( tmrTIMER_CHANNEL_2 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The TMR0 interrupt is used for different purposes by the low power and full\r
+demos respectively. */\r
+#if( configCREATE_LOW_POWER_DEMO == 0 )\r
+\r
+ void NVIC_Handler_TMR0( void ) iv IVT_INT_TIMER0 ics ICS_AUTO\r
+ {\r
+ tmrRECORD_NESTING_DEPTH();\r
+\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+\r
+ ulNestingDepth--;\r
+ }\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_TMR1( void ) iv IVT_INT_TIMER1 ics ICS_AUTO\r
+{\r
+ tmrRECORD_NESTING_DEPTH();\r
+\r
+ /* Just testing the xPortIsInsideInterrupt() functionality. */\r
+ configASSERT( xPortIsInsideInterrupt() == pdTRUE );\r
+\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+\r
+ ulNestingDepth--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_TMR2( void ) iv IVT_INT_TIMER2 ics ICS_AUTO\r
+{\r
+ tmrRECORD_NESTING_DEPTH();\r
+ ulNestingDepth--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
projects / freertos / blobdiff