-/******************************************************************************\r
+/**************************************************************************//**\r
* @file system_XMC4500.c\r
- * @brief Device specific initialization for the XMC4500-Series according to CMSIS\r
- * @version V2.2\r
- * @date 20. January 2012\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
*\r
* @note\r
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
-\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
*\r
* @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
- * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
-\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
*\r
* @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
*\r
- *\r
******************************************************************************/\r
\r
#include "system_XMC4500.h"\r
#include <XMC4500.h>\r
\r
-/*----------------------------------------------------------------------------\r
- Define clocks is located in System_XMC4500.h\r
- *----------------------------------------------------------------------------*/\r
-\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock = CLOCK_OSC_HP;\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1 \r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
\r
-/*----------------------------------------------------------------------------\r
- Keil pragma to prevent warnings\r
- *----------------------------------------------------------------------------*/\r
-#if defined(__ARMCC_VERSION)\r
-#pragma diag_suppress 177\r
-#endif\r
\r
/*\r
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
#define SCU_CPUCLKCR_DIV 0x00000000\r
#define SCU_PBCLKCR_DIV 0x00000000\r
#define SCU_CCUCLKCR_DIV 0x00000000\r
-\r
-\r
+/* not avalible in config wizzard*/\r
+/* \r
+* mandatory clock parameters ************************************************** \r
+* \r
+* source for clock generation \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+* \r
+**************************************************************************************/ \r
+// Selection of imput lock for PLL \r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define CLOCK_BACK_UP 24000000 \r
+ \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */ \r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2 \r
+ \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */ \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+ \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1 \r
+//#define SCU_PLL_K2DIV 3 \r
+//#define SCU_PLL_PDIV 3 \r
+//#define SCU_PLL_NDIV 79 \r
+/*************************************************************************************/\r
\r
/*--------------------- USB CLOCK Configuration ---------------------------\r
//\r
*/\r
\r
#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0 \r
+#define SCU_USBPLL_NDIV 31 \r
+#define SCU_USBDIV 3 \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS \r
+// <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
\r
\r
/*--------------------- CLOCKOUT Configuration -------------------------------\r
// <e> Clock OUT Configuration\r
// <o1.0..1> Clockout Source Selection\r
// <0=> System Clock\r
-// <2=> USB Clock\r
+// <2=> Divided value of USB PLL output\r
// <3=> Divided value of PLL Clock\r
-// <o2.0..1> Clockout Pin Selection\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
// <0=> P1.15\r
// <1=> P0.8\r
// \r
// \r
*/\r
\r
-#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled\r
-#define SCU_CLOCKOUT_SOURCE 0x00000000\r
-#define SCU_CLOCKOUT_PIN 0x00000000\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000003\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
\r
/*----------------------------------------------------------------------------\r
static functions declarations\r
#endif\r
\r
#if (SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void);\r
+static int USBClockSetup(void);\r
#endif\r
\r
+\r
/**\r
* @brief Setup the microcontroller system.\r
* Initialize the PLL and update the \r
*/\r
void SystemInit(void)\r
{\r
-/* Setup the WDT */\r
-#if (WDT_SETUP == 1)\r
-WDT->CTR &= ~WDTENB_nVal; \r
-#endif\r
-\r
+int temp;\r
+ \r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
(3UL << 11*2) ); /* set CP11 Full Access */\r
#endif\r
\r
-/* Disable branch prediction - PCON.PBS = 1 */\r
-PREF->PCON |= (PREF_PCON_PBS_Msk);\r
-\r
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+ \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+ \r
/* Setup the clockout */\r
-/* README README README README README README README README README README */\r
-/*\r
- * Please use the CLOCKOUT feature with diligence. Use this only if you know\r
- * what you are doing.\r
- *\r
- * You must be aware that the settings below can potentially be in conflict\r
- * with DAVE code generation engine preferences.\r
- *\r
- * Even worse, the setting below configures the ports as output ports while in\r
- * reality, the board on which this chip is mounted may have a source driving\r
- * the ports.\r
- *\r
- * So use this feature only when you are absolutely sure that the port must \r
- * indeed be configured as an output AND you are NOT linking this startup code\r
- * with code that was generated by DAVE code engine.\r
- */\r
-#if (SCU_CLOCKOUT_SETUP == 1)\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
\r
if (SCU_CLOCKOUT_PIN) {\r
- PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
- PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
- }\r
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
#endif\r
\r
+\r
/* Setup the System clock */ \r
-#if (SCU_CLOCK_SETUP == 1)\r
+#if SCU_CLOCK_SETUP\r
SystemClockSetup();\r
#endif\r
\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
/* Setup the USB PL */ \r
-#if (SCU_USB_CLOCK_SETUP == 1)\r
+#if SCU_USB_CLOCK_SETUP\r
USBClockSetup();\r
#endif\r
\r
+\r
+\r
}\r
\r
\r
*/\r
void SystemCoreClockUpdate(void)\r
{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */ \r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ } \r
+ \r
+ \r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
\r
}\r
\r
#if (SCU_CLOCK_SETUP == 1)\r
static int SystemClockSetup(void)\r
{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV; \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
/* enable PLL first */\r
- SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | \r
- SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
\r
-/* Enable OSC_HP */\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
{\r
- /* Enable the OSC_HP*/\r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); \r
- /* Setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* Select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
- /* Restart OSC Watchdog */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
-\r
- do \r
- {\r
- ; /* here a timeout need to be added */\r
- }while(!( (SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |\r
- SCU_PLL_PLLSTAT_PLLSP_Msk)\r
- )\r
- ); \r
-\r
- }\r
-\r
-/* Setup Main PLL */\r
- /* Select FOFI as system clock */\r
- if(SCU_CLK->SYSCLKCR != 0X000000)\r
- SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
\r
- /* Go to bypass the Main PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
-\r
- /* disconnect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));\r
-\r
- /* we may have to set OSCDISCDIS */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
-\r
- /* connect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
- /* restart PLL Lock detection */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
\r
- /* wait for PLL Lock */\r
- while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
\r
- /* Go back to the Main PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
\r
- /*********************************************************\r
- here we need to setup the system clock divider\r
- *********************************************************/\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ } \r
+ // now OSCULP is running and can be used \r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ }\r
+ }\r
\r
- SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
- SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
- SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/24000000)-1; \r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ \r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+ \r
+ \r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+ \r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ \r
\r
- /* Switch system clock to PLL */\r
- SCU_CLK->SYSCLKCR |= 0x00010000; \r
- \r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ \r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/60000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
/*********************************************************\r
- here the ramp up of the system clock starts\r
- *********************************************************/\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- /* Set reload register */\r
- SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_ENABLE_Msk; \r
- \r
- /* wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0;\r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | \r
- (PLL_PDIV<<24));\r
-\r
- /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
- SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | \r
- SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; \r
-\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ \r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
return(1);\r
\r
}\r
* @param None\r
* @retval None\r
*/\r
-#if(SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void)\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
{\r
-/* enable PLL first */\r
- SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | \r
- SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+\r
+ /* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
\r
/* check and if not already running enable OSC_HP */\r
- if(!((SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))\r
- {\r
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
- {\r
- \r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
/* setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
/* restart OSC Watchdog */\r
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
do \r
{\r
- ; /* here a timeout need to be added */\r
- }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
\r
- }\r
}\r
\r
\r
/* disconnect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
/* Setup devider settings for main PLL */\r
- SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
/* we may have to set OSCDISCDIS */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
/* connect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
/* wait for PLL Lock */\r
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
- }\r
+ \r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
#endif\r
+\r
projects / freertos / blobdiff