/*\r
- FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems, who sell the code with commercial support,\r
- indemnification and middleware, under the OpenRTOS brand.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-*/\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/* Standard includes. */\r
#include "limits.h"\r
/* Constants required to pend a PendSV interrupt from the tick ISR if the\r
preemptive scheduler is being used. These are just standard bits and registers\r
within the Cortex-M core itself. */\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
\r
/* The alarm used to generate interrupts in the asynchronous timer. */\r
*/\r
void AST_ALARM_Handler(void);\r
\r
+/*\r
+ * Functions that disable and enable the AST respectively, not returning until\r
+ * the operation is known to have taken effect.\r
+ */\r
+static void prvDisableAST( void );\r
+static void prvEnableAST( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* Calculate how many clock increments make up a single tick period. */\r
/* Holds the maximum number of ticks that can be suppressed - which is\r
basically how far into the future an interrupt can be generated. Set\r
during initialisation. */\r
-static portTickType xMaximumPossibleSuppressedTicks = 0;\r
+static TickType_t xMaximumPossibleSuppressedTicks = 0;\r
\r
/* Flag set from the tick interrupt to allow the sleep processing to know if\r
sleep mode was exited because of an AST interrupt or a different interrupt. */\r
following variable offsets the AST counter alarm value by the number of AST\r
counts that would typically be missed while the counter was stopped to compensate\r
for the lost time. _RB_ Value needs calculating correctly. */\r
-static uint32_t ulStoppedTimerCompensation = 10 / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+static uint32_t ulStoppedTimerCompensation = 2 / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
\r
/*-----------------------------------------------------------*/\r
\r
tick. */\r
void AST_ALARM_Handler(void)\r
{\r
- /* If using preemption, also force a context switch by pending the PendSV\r
- interrupt. */\r
- #if configUSE_PREEMPTION == 1\r
- {\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
- }\r
- #endif\r
-\r
/* Protect incrementing the tick with an interrupt safe critical section. */\r
( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
{\r
- vTaskIncrementTick();\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
\r
/* Just completely clear the interrupt mask on exit by passing 0 because\r
it is known that this interrupt will only ever execute with the lowest\r
/*-----------------------------------------------------------*/\r
\r
/* Override the default definition of vPortSetupTimerInterrupt() that is weakly\r
-defined in the FreeRTOS Cortex-M3 port layer layer with a version that\r
-configures the asynchronous timer (AST) to generate the tick interrupt. */\r
+defined in the FreeRTOS Cortex-M3 port layer with a version that configures the\r
+asynchronous timer (AST) to generate the tick interrupt. */\r
void vPortSetupTimerInterrupt( void )\r
{\r
struct ast_config ast_conf;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void prvDisableAST( void )\r
+static void prvDisableAST( void )\r
{\r
while( ast_is_busy( AST ) )\r
{\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void prvEnableAST( void )\r
+static void prvEnableAST( void )\r
{\r
while( ast_is_busy( AST ) )\r
{\r
/*-----------------------------------------------------------*/\r
\r
/* Override the default definition of vPortSuppressTicksAndSleep() that is weakly\r
-defined in the FreeRTOS Cortex-M3 port layer layer with a version that manages\r
-the asynchronous timer (AST), as the tick is generated from the low power AST\r
-and not the SysTick as would normally be the case on a Cortex-M. */\r
-void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+defined in the FreeRTOS Cortex-M3 port layer with a version that manages the\r
+asynchronous timer (AST), as the tick is generated from the low power AST and\r
+not the SysTick as would normally be the case on a Cortex-M. */\r
+void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
-uint32_t ulAlarmValue, ulCompleteTickPeriods;\r
+uint32_t ulAlarmValue, ulCompleteTickPeriods, ulInterruptStatus;\r
eSleepModeStatus eSleepAction;\r
-portTickType xModifiableIdleTime;\r
+TickType_t xModifiableIdleTime;\r
+enum sleepmgr_mode xSleepMode;\r
\r
/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */\r
\r
}\r
\r
/* Calculate the reload value required to wait xExpectedIdleTime tick\r
- periods. -1 is used because this code will execute part way through one of\r
- the tick periods, and the fraction of a tick period is accounted for\r
- later. */\r
- ulAlarmValue = ( ulAlarmValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ periods. */\r
+ ulAlarmValue = ulAlarmValueForOneTick * xExpectedIdleTime;\r
if( ulAlarmValue > ulStoppedTimerCompensation )\r
{\r
/* Compensate for the fact that the AST is going to be stopped\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL() method as\r
that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i \n\t"\r
- "dsb \n\t" );\r
+ ulInterruptStatus = cpu_irq_save();\r
\r
/* The tick flag is set to false before sleeping. If it is true when sleep\r
mode is exited then sleep mode was probably exited because the tick was\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ cpu_irq_restore( ulInterruptStatus );\r
}\r
else\r
{\r
instruction. */\r
if( xModifiableIdleTime > 0 )\r
{\r
- /* Sleep until something happens. */\r
- sleepmgr_enter_sleep();\r
+ /* Find the deepest allowable sleep mode. */\r
+ xSleepMode = sleepmgr_get_sleep_mode();\r
+\r
+ if( xSleepMode != SLEEPMGR_ACTIVE )\r
+ {\r
+ /* Sleep until something happens. */\r
+ bpm_sleep( BPM, xSleepMode );\r
+ }\r
}\r
\r
/* Allow the application to define some post sleep processing. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
-#warning The sleep manager will have re-enabled interrupts already, does this matter?\r
- __asm volatile( "cpsie i" );\r
+ cpu_irq_restore( ulInterruptStatus );\r
\r
if( ulTickFlag != pdFALSE )\r
{\r
/* The alarm value is set to whatever fraction of a single tick\r
period remains. */\r
ulAlarmValue = ast_read_counter_value( AST ) - ( ulCompleteTickPeriods * ulAlarmValueForOneTick );\r
+ if( ulAlarmValue == 0 )\r
+ {\r
+ /* There is no fraction remaining. */\r
+ ulAlarmValue = ulAlarmValueForOneTick;\r
+ ulCompleteTickPeriods++;\r
+ }\r
+ ast_write_counter_value( AST, 0 );\r
ast_write_alarm0_value( AST, ulAlarmValue );\r
}\r
\r
projects / freertos / blobdiff