Change version numbers ready for V8.0.0 release candidate 1 tag.

[freertos] / FreeRTOS / Demo / CORTEX_M4_ATSAM4L_Atmel_Studio / src / SAM4L_low_power_tick_management.c

diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c
index 0d840a5a3832af757609d2f4b47f4ff0e78d37c3..8be7dcf68ab811440d9888c20f56ce6ed8792a23 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c
+++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c
@@ -1,5 +1,6 @@
 /*\r
-    FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+    FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+    All rights reserved\r
 \r
     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
 \r
@@ -87,7 +88,6 @@
 /* Constants required to pend a PendSV interrupt from the tick ISR if the\r
 preemptive scheduler is being used.  These are just standard bits and registers\r
 within the Cortex-M core itself. */\r
-#define portNVIC_INT_CTRL_REG  ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
 \r
 /* The alarm used to generate interrupts in the asynchronous timer. */\r
@@ -247,12 +247,12 @@ static void prvEnableAST( void )
 /*-----------------------------------------------------------*/\r
 \r
 /* Override the default definition of vPortSuppressTicksAndSleep() that is weakly\r
-defined in the FreeRTOS Cortex-M3 port layet with a version that manages the\r
+defined in the FreeRTOS Cortex-M3 port layer with a version that manages the\r
 asynchronous timer (AST), as the tick is generated from the low power AST and\r
 not the SysTick as would normally be the case on a Cortex-M. */\r
 void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 {\r
-uint32_t ulAlarmValue, ulCompleteTickPeriods;\r
+uint32_t ulAlarmValue, ulCompleteTickPeriods, ulInterruptStatus;\r
 eSleepModeStatus eSleepAction;\r
 portTickType xModifiableIdleTime;\r
 enum sleepmgr_mode xSleepMode;\r
@@ -283,8 +283,7 @@ enum sleepmgr_mode xSleepMode;
 \r
        /* Enter a critical section but don't use the taskENTER_CRITICAL() method as\r
        that will mask interrupts that should exit sleep mode. */\r
-       __asm volatile( "cpsid i                \n\t"\r
-                                       "dsb                    \n\t" );\r
+       ulInterruptStatus = cpu_irq_save();\r
 \r
        /* The tick flag is set to false before sleeping.  If it is true when sleep\r
        mode is exited then sleep mode was probably exited because the tick was\r
@@ -302,7 +301,7 @@ enum sleepmgr_mode xSleepMode;
 \r
                /* Re-enable interrupts - see comments above the cpsid instruction()\r
                above. */\r
-               __asm volatile( "cpsie i" );\r
+               cpu_irq_restore( ulInterruptStatus );\r
        }\r
        else\r
        {\r
@@ -344,7 +343,7 @@ enum sleepmgr_mode xSleepMode;
 \r
                /* Re-enable interrupts - see comments above the cpsid instruction()\r
                above. */\r
-               __asm volatile( "cpsie i" );\r
+               cpu_irq_restore( ulInterruptStatus );\r
 \r
                if( ulTickFlag != pdFALSE )\r
                {\r
@@ -372,6 +371,12 @@ enum sleepmgr_mode xSleepMode;
                        /* The alarm value is set to whatever fraction of a single tick\r
                        period remains. */\r
                        ulAlarmValue = ast_read_counter_value( AST ) - ( ulCompleteTickPeriods * ulAlarmValueForOneTick );\r
+                       if( ulAlarmValue == 0 )\r
+                       {\r
+                               /* There is no fraction remaining. */\r
+                               ulAlarmValue = ulAlarmValueForOneTick;\r
+                               ulCompleteTickPeriods++;\r
+                       }\r
                        ast_write_alarm0_value( AST, ulAlarmValue );\r
                }\r
 \r