/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+ FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
***************************************************************************\r
* *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
* *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
* *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * Thank you! *\r
* *\r
***************************************************************************\r
\r
-\r
This file is part of the FreeRTOS distribution.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
\r
1 tab == 4 spaces!\r
\r
* *\r
***************************************************************************\r
\r
-\r
http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
\r
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems, who sell the code with commercial support,\r
- indemnification and middleware, under the OpenRTOS brand.\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
\r
http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
*/\r
\r
/* Standard includes. */\r
/* Constants required to pend a PendSV interrupt from the tick ISR if the\r
preemptive scheduler is being used. These are just standard bits and registers\r
within the Cortex-M core itself. */\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
\r
/* The alarm used to generate interrupts in the asynchronous timer. */\r
*/\r
void AST_ALARM_Handler(void);\r
\r
-/* \r
+/*\r
* Functions that disable and enable the AST respectively, not returning until\r
* the operation is known to have taken effect.\r
*/\r
tick. */\r
void AST_ALARM_Handler(void)\r
{\r
- /* If using preemption, also force a context switch by pending the PendSV\r
- interrupt. */\r
- #if configUSE_PREEMPTION == 1\r
- {\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
- }\r
- #endif\r
-\r
/* Protect incrementing the tick with an interrupt safe critical section. */\r
( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
{\r
- vTaskIncrementTick();\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
\r
/* Just completely clear the interrupt mask on exit by passing 0 because\r
it is known that this interrupt will only ever execute with the lowest\r
/*-----------------------------------------------------------*/\r
\r
/* Override the default definition of vPortSuppressTicksAndSleep() that is weakly\r
-defined in the FreeRTOS Cortex-M3 port layet with a version that manages the \r
-asynchronous timer (AST), as the tick is generated from the low power AST and \r
+defined in the FreeRTOS Cortex-M3 port layer with a version that manages the\r
+asynchronous timer (AST), as the tick is generated from the low power AST and\r
not the SysTick as would normally be the case on a Cortex-M. */\r
void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
{\r
-uint32_t ulAlarmValue, ulCompleteTickPeriods;\r
+uint32_t ulAlarmValue, ulCompleteTickPeriods, ulInterruptStatus;\r
eSleepModeStatus eSleepAction;\r
portTickType xModifiableIdleTime;\r
enum sleepmgr_mode xSleepMode;\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL() method as\r
that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i \n\t"\r
- "dsb \n\t" );\r
+ ulInterruptStatus = cpu_irq_save();\r
\r
/* The tick flag is set to false before sleeping. If it is true when sleep\r
mode is exited then sleep mode was probably exited because the tick was\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ cpu_irq_restore( ulInterruptStatus );\r
}\r
else\r
{\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ cpu_irq_restore( ulInterruptStatus );\r
\r
if( ulTickFlag != pdFALSE )\r
{\r
/* The alarm value is set to whatever fraction of a single tick\r
period remains. */\r
ulAlarmValue = ast_read_counter_value( AST ) - ( ulCompleteTickPeriods * ulAlarmValueForOneTick );\r
+ if( ulAlarmValue == 0 )\r
+ {\r
+ /* There is no fraction remaining. */\r
+ ulAlarmValue = ulAlarmValueForOneTick;\r
+ ulCompleteTickPeriods++;\r
+ }\r
ast_write_alarm0_value( AST, ulAlarmValue );\r
}\r
\r
projects / freertos / blobdiff