--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ ISR(foo_irq_handler)\r
+ {\r
+ // Function definition\r
+ ...\r
+ }\r
+\endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ irq_initialize_vectors();\r
+ irq_register_handler(foo_irq_handler);\r
+\endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(int_num, int_prio) \\r
+ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \\r
+ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \\r
+ NVIC_EnableIRQ( (IRQn_Type)int_num); \\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+\r
+#if !defined(__DOXYGEN__)\r
+extern volatile bool g_interrupt_enabled;\r
+#endif\r
+\r
+#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)\r
+\r
+static volatile uint32_t cpu_irq_critical_section_counter;\r
+static volatile bool cpu_irq_prev_interrupt_state;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = cpu_irq_is_enabled();\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+void cpu_irq_enter_critical(void);\r
+void cpu_irq_leave_critical(void);\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
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