--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Matrix driver for SAM.\r
+ *\r
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#include "matrix.h"\r
+\r
+/* / @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* / @endcond */\r
+\r
+/**\r
+ * \defgroup sam_drivers_matrix_group Matrix (MATRIX)\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Bus Matrix implements a multi-layer AHB that enables parallel access\r
+ * paths between multiple AHB masters and slaves in a system, which increases\r
+ * the overall bandwidth.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if SAM4C\r
+#ifdef SAM4C_0\r
+#define MATRIX MATRIX0\r
+#else\r
+#define MATRIX MATRIX1\r
+#endif\r
+#endif\r
+\r
+#if SAM4CP\r
+#ifdef SAM4CP_0\r
+#define MATRIX MATRIX0\r
+#else\r
+#define MATRIX MATRIX1\r
+#endif\r
+#endif\r
+\r
+#if SAM4CM\r
+#ifdef SAM4CM_0\r
+#define MATRIX MATRIX0\r
+#else\r
+#define MATRIX MATRIX1\r
+#endif\r
+#endif\r
+\r
+#ifndef MATRIX_WPMR_WPKEY_PASSWD\r
+#define MATRIX_WPMR_WPKEY_PASSWD MATRIX_WPMR_WPKEY(0x4D4154U)\r
+#endif\r
+\r
+/**\r
+ * \brief Set undefined length burst type of the specified master.\r
+ *\r
+ * \param ul_id Master index.\r
+ * \param burst_type Undefined length burst type.\r
+ */\r
+void matrix_set_master_burst_type(uint32_t ul_id, burst_type_t burst_type)\r
+{\r
+#if (SAMV70 || SAMS70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_MCFG;\r
+ volatile uint32_t ul_reg;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_MCFG1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_MCFG0);\r
+\r
+ p_MCFG = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_MCFG0) +\r
+ ul_id * ul_dlt);\r
+\r
+ ul_reg = *p_MCFG & (~MATRIX_MCFG0_ULBT_Msk);\r
+ *p_MCFG = ul_reg | (uint32_t)burst_type;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (~MATRIX_MCFG_ULBT_Msk);\r
+ p_matrix->MATRIX_MCFG[ul_id] = ul_reg | (uint32_t)burst_type;\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Get undefined length burst type of the specified master.\r
+ *\r
+ * \param ul_id Master index.\r
+ *\r
+ * \return Undefined length burst type.\r
+ */\r
+burst_type_t matrix_get_master_burst_type(uint32_t ul_id)\r
+{\r
+#if (SAMV70 || SAMS70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_MCFG;\r
+ volatile uint32_t ul_reg;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_MCFG1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_MCFG0);\r
+\r
+ p_MCFG = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_MCFG0) +\r
+ ul_id * ul_dlt);\r
+\r
+ ul_reg = *p_MCFG & (~MATRIX_MCFG0_ULBT_Msk);\r
+ return (burst_type_t)ul_reg;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (MATRIX_MCFG_ULBT_Msk);\r
+ return (burst_type_t)ul_reg;\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set slot cycle of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param ul_slot_cycle Number of slot cycle.\r
+ */\r
+void matrix_set_slave_slot_cycle(uint32_t ul_id, uint32_t ul_slot_cycle)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_SLOT_CYCLE_Msk);\r
+ p_matrix->MATRIX_SCFG[ul_id] = ul_reg | MATRIX_SCFG_SLOT_CYCLE(\r
+ ul_slot_cycle);\r
+}\r
+\r
+/**\r
+ * \brief Get slot cycle of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Number of slot cycle.\r
+ */\r
+uint32_t matrix_get_slave_slot_cycle(uint32_t ul_id)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_SLOT_CYCLE_Msk);\r
+ return (ul_reg >> MATRIX_SCFG_SLOT_CYCLE_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Set default master type of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param type Default master type.\r
+ */\r
+void matrix_set_slave_default_master_type(uint32_t ul_id, defaut_master_t type)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_DEFMSTR_TYPE_Msk);\r
+ p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type;\r
+}\r
+\r
+/**\r
+ * \brief Get default master type of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Default master type.\r
+ */\r
+defaut_master_t matrix_get_slave_default_master_type(uint32_t ul_id)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_DEFMSTR_TYPE_Msk);\r
+ return (defaut_master_t)ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Set fixed default master of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param ul_fixed_id Fixed default master index.\r
+ */\r
+void matrix_set_slave_fixed_default_master(uint32_t ul_id, uint32_t ul_fixed_id)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] &\r
+ (~MATRIX_SCFG_FIXED_DEFMSTR_Msk);\r
+ p_matrix->MATRIX_SCFG[ul_id]\r
+ = ul_reg | MATRIX_SCFG_FIXED_DEFMSTR(ul_fixed_id);\r
+}\r
+\r
+/**\r
+ * \brief Get fixed default master of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Fixed default master index.\r
+ */\r
+uint32_t matrix_get_slave_fixed_default_master(uint32_t ul_id)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_FIXED_DEFMSTR_Msk);\r
+ return (ul_reg >> MATRIX_SCFG_FIXED_DEFMSTR_Pos);\r
+}\r
+\r
+#if !SAM4E && !SAM4C && !SAM4CP && !SAM4CM && \\r
+ !SAMV71 && !SAMV70 && !SAMS70 && !SAME70\r
+/**\r
+ * \brief Set slave arbitration type of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param type Arbitration type.\r
+ */\r
+void matrix_set_slave_arbitration_type(uint32_t ul_id, arbitration_type_t type)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_ARBT_Msk);\r
+ p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type;\r
+}\r
+\r
+/**\r
+ * \brief Get slave arbitration type of the specified slave.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Arbitration type.\r
+ */\r
+arbitration_type_t matrix_get_slave_arbitration_type(uint32_t ul_id)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_ARBT_Msk);\r
+ return (arbitration_type_t)ul_reg;\r
+}\r
+\r
+#endif\r
+\r
+/**\r
+ * \brief Set priority for the specified slave access.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param ul_prio Bitmask OR of priorities of master x.\r
+ */\r
+void matrix_set_slave_priority(uint32_t ul_id, uint32_t ul_prio)\r
+{\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ p_matrix->MATRIX_PR[ul_id].MATRIX_PRAS = ul_prio;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_PRAS;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0);\r
+\r
+ p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) +\r
+ ul_id * ul_dlt);\r
+\r
+ *p_PRAS = ul_prio;\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Get priority for the specified slave access.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Bitmask OR of priorities of master x.\r
+ */\r
+uint32_t matrix_get_slave_priority(uint32_t ul_id)\r
+{\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ return p_matrix->MATRIX_PR[ul_id].MATRIX_PRAS;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_PRAS;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0);\r
+\r
+ p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) +\r
+ ul_id * ul_dlt);\r
+\r
+ return (*p_PRAS);\r
+#endif\r
+}\r
+\r
+#if (SAMV71 || SAMV70|| SAME70 || SAMS70)\r
+/**\r
+ * \brief Set priority for the specified slave access.\r
+ *\r
+ * \param ul_id Slave index.\r
+ * \param ul_prio_b Bitmask OR of priorities of master x.\r
+ */\r
+void matrix_set_slave_priority_b(uint32_t ul_id, uint32_t ul_prio_b)\r
+{\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ p_matrix->MATRIX_PR[ul_id].MATRIX_PRBS = ul_prio_b;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_PRAS;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRBS1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRBS0);\r
+\r
+ p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRBS0) +\r
+ ul_id * ul_dlt);\r
+\r
+ *p_PRAS = ul_prio;\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Get priority for the specified slave access.\r
+ *\r
+ * \param ul_id Slave index.\r
+ *\r
+ * \return Bitmask OR of priorities of master x.\r
+ */\r
+uint32_t matrix_get_slave_priority_b(uint32_t ul_id)\r
+{\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+ Matrix *p_matrix = MATRIX;\r
+ return p_matrix->MATRIX_PR[ul_id].MATRIX_PRBS;\r
+#else\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t *p_PRAS;\r
+ uint32_t ul_dlt;\r
+\r
+ ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRBS1);\r
+ ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRBS0);\r
+\r
+ p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRBS0) +\r
+ ul_id * ul_dlt);\r
+\r
+ return (*p_PRAS);\r
+#endif\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U || SAM4E ||\\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+/**\r
+ * \brief Set bus matrix master remap.\r
+ *\r
+ * \param ul_remap Bitmask OR of RCBx: 0 for disable, 1 for enable.\r
+ */\r
+void matrix_set_master_remap(uint32_t ul_remap)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ p_matrix->MATRIX_MRCR = ul_remap;\r
+}\r
+\r
+/**\r
+ * \brief Get bus matrix master remap.\r
+ *\r
+ * \return Bitmask OR of RCBx: 0 for disable, 1 for enable.\r
+ */\r
+uint32_t matrix_get_master_remap(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ return (p_matrix->MATRIX_MRCR);\r
+}\r
+\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+/**\r
+ * \brief Set system IO.\r
+ *\r
+ * \param ul_io Bitmask OR of SYSIOx.\r
+ */\r
+void matrix_set_system_io(uint32_t ul_io)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+\r
+ p_matrix->MATRIX_SYSIO = ul_io;\r
+\r
+#elif (SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+ \r
+ p_matrix->CCFG_SYSIO &= 0xFFFF0000;\r
+ p_matrix->CCFG_SYSIO |= (ul_io & 0xFFFF);\r
+\r
+#else\r
+\r
+ p_matrix->CCFG_SYSIO = ul_io;\r
+\r
+#endif\r
+\r
+}\r
+\r
+/**\r
+ * \brief Get system IO.\r
+ *\r
+ * \return Bitmask OR of SYSIOx.\r
+ */\r
+uint32_t matrix_get_system_io(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+\r
+ return (p_matrix->MATRIX_SYSIO);\r
+\r
+#elif (SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+\r
+ return (p_matrix->CCFG_SYSIO & 0xFFFF);\r
+\r
+#else\r
+\r
+ return (p_matrix->CCFG_SYSIO);\r
+\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#if (SAM3S || SAM4S || SAM4E || SAM4C || SAM4CP || SAM4CM || \\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+/**\r
+ * \brief Set NAND Flash Chip Select configuration register.\r
+ *\r
+ * \param ul_cs Bitmask OR of SMC_NFCSx: 0 if NCSx is not assigned,\r
+ * 1 if NCSx is assigned.\r
+ */\r
+void matrix_set_nandflash_cs(uint32_t ul_cs)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+\r
+ p_matrix->MATRIX_SMCNFCS = ul_cs;\r
+\r
+#else\r
+\r
+ p_matrix->CCFG_SMCNFCS = ul_cs;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Get NAND Flash Chip Select configuration register.\r
+ *\r
+ * \return Bitmask OR of SMC_NFCSx.\r
+ */\r
+uint32_t matrix_get_nandflash_cs(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+\r
+ return (p_matrix->MATRIX_SMCNFCS);\r
+\r
+#else\r
+\r
+ return (p_matrix->CCFG_SMCNFCS);\r
+\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#if (!SAMG)\r
+/**\r
+ * \brief Enable or disable write protect of MATRIX registers.\r
+ *\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void matrix_set_writeprotect(uint32_t ul_enable)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ if (ul_enable) {\r
+ p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD | MATRIX_WPMR_WPEN;\r
+ } else {\r
+ p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get write protect status.\r
+ *\r
+ * \return Write protect status.\r
+ */\r
+uint32_t matrix_get_writeprotect_status(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ return (p_matrix->MATRIX_WPSR);\r
+}\r
+#endif\r
+\r
+#if SAMG55\r
+/**\r
+ * \brief Set USB device mode.\r
+ *\r
+ */\r
+void matrix_set_usb_device(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ p_matrix->CCFG_SYSIO &= ~(CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);\r
+\r
+ p_matrix->CCFG_USBMR |= CCFG_USBMR_DEVICE;\r
+}\r
+\r
+/**\r
+ * \brief Set USB device mode.\r
+ *\r
+ */\r
+void matrix_set_usb_host(void)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+\r
+ p_matrix->CCFG_SYSIO &= ~(CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);\r
+\r
+ p_matrix->CCFG_USBMR &= ~CCFG_USBMR_DEVICE;\r
+}\r
+#endif\r
+\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+/**\r
+ * \brief Set CAN0 DMA base address.\r
+ *\r
+ * \param base_addr the 16-bit MSB of the CAN0 DMA base address.\r
+ */\r
+void matrix_set_can0_addr(uint32_t base_addr)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ p_matrix->CCFG_CAN0 = CCFG_CAN0_CAN0DMABA(base_addr);\r
+}\r
+\r
+/**\r
+ * \brief Set CAN1 DMA base address.\r
+ *\r
+ * \param base_addr the 16-bit MSB of the CAN1 DMA base address.\r
+ */\r
+void matrix_set_can1_addr(uint32_t base_addr)\r
+{\r
+ Matrix *p_matrix = MATRIX;\r
+ volatile uint32_t ul_reg;\r
+\r
+ ul_reg = p_matrix->CCFG_SYSIO & (~CCFG_SYSIO_CAN1DMABA_Msk);\r
+ p_matrix->CCFG_SYSIO = ul_reg | CCFG_SYSIO_CAN1DMABA(base_addr);\r
+}\r
+#endif\r
+\r
+/* @} */\r
+\r
+/* / @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* / @endcond */\r
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