--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Matrix driver for SAM.\r
+ *\r
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef MATRIX_H_INCLUDED\r
+#define MATRIX_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/* / @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* / @endcond */\r
+\r
+#ifndef MATRIX_MCFG_ULBT\r
+#define MATRIX_MCFG_ULBT(value) MATRIX_MCFG0_ULBT(value)\r
+#endif\r
+/** \brief Matrix master: undefined length burst type */\r
+typedef enum {\r
+ MATRIX_ULBT_INFINITE_LENGTH_BURST = MATRIX_MCFG_ULBT(0),\r
+ MATRIX_ULBT_SINGLE_ACCESS = MATRIX_MCFG_ULBT(1),\r
+ MATRIX_ULBT_4_BEAT_BURST = MATRIX_MCFG_ULBT(2),\r
+ MATRIX_ULBT_8_BEAT_BURST = MATRIX_MCFG_ULBT(3),\r
+ MATRIX_ULBT_16_BEAT_BURST = MATRIX_MCFG_ULBT(4),\r
+#if SAM4C || SAM4CP || SAM4CM || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70\r
+ MATRIX_ULBT_32_BEAT_BURST = MATRIX_MCFG_ULBT(5),\r
+ MATRIX_ULBT_64_BEAT_BURST = MATRIX_MCFG_ULBT(6),\r
+ MATRIX_ULBT_128_BEAT_BURST = MATRIX_MCFG_ULBT(7),\r
+#endif\r
+} burst_type_t;\r
+\r
+/** \brief Matrix slave: default master type */\r
+typedef enum {\r
+ MATRIX_DEFMSTR_NO_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(0),\r
+ MATRIX_DEFMSTR_LAST_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(1),\r
+ MATRIX_DEFMSTR_FIXED_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(2)\r
+} defaut_master_t;\r
+\r
+#if !SAM4E && !SAM4C && !SAM4CP && !SAM4CM && \\r
+ !SAMV71 && !SAMV70 && !SAMS70 && !SAME70\r
+/** \brief Matrix slave: arbitration type */\r
+typedef enum {\r
+ MATRIX_ARBT_ROUND_ROBIN = MATRIX_SCFG_ARBT(0),\r
+ MATRIX_ARBT_FIXED_PRIORITY = MATRIX_SCFG_ARBT(1)\r
+} arbitration_type_t;\r
+#endif\r
+\r
+void matrix_set_master_burst_type(uint32_t ul_id, burst_type_t burst_type);\r
+burst_type_t matrix_get_master_burst_type(uint32_t ul_id);\r
+void matrix_set_slave_slot_cycle(uint32_t ul_id, uint32_t ul_slot_cycle);\r
+uint32_t matrix_get_slave_slot_cycle(uint32_t ul_id);\r
+void matrix_set_slave_default_master_type(uint32_t ul_id, defaut_master_t type);\r
+defaut_master_t matrix_get_slave_default_master_type(uint32_t ul_id);\r
+void matrix_set_slave_fixed_default_master(uint32_t ul_id,\r
+ uint32_t ul_fixed_id);\r
+uint32_t matrix_get_slave_fixed_default_master(uint32_t ul_id);\r
+\r
+#if !SAM4E && !SAM4C && !SAM4CP && !SAM4CM && \\r
+ !SAMV71 && !SAMV70 && !SAMS70 && !SAME70\r
+void matrix_set_slave_arbitration_type(uint32_t ul_id, arbitration_type_t type);\r
+arbitration_type_t matrix_get_slave_arbitration_type(uint32_t ul_id);\r
+#endif\r
+\r
+void matrix_set_slave_priority(uint32_t ul_id, uint32_t ul_prio);\r
+uint32_t matrix_get_slave_priority(uint32_t ul_id);\r
+#if (SAMV71 || SAMV70|| SAME70 || SAMS70)\r
+void matrix_set_slave_priority_b(uint32_t ul_id, uint32_t ul_prio_b);\r
+uint32_t matrix_get_slave_priority_b(uint32_t ul_id);\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U || SAM4E || \\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+void matrix_set_master_remap(uint32_t ul_remap);\r
+uint32_t matrix_get_master_remap(void);\r
+\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+void matrix_set_system_io(uint32_t ul_io);\r
+uint32_t matrix_get_system_io(void);\r
+\r
+#endif\r
+\r
+#if (SAM3S || SAM4S || SAM4E || SAM4C || SAM4CP || SAM4CM || \\r
+ SAMV71 || SAMV70 || SAMS70 || SAME70)\r
+void matrix_set_nandflash_cs(uint32_t ul_cs);\r
+uint32_t matrix_get_nandflash_cs(void);\r
+#endif\r
+\r
+#if (!SAMG)\r
+void matrix_set_writeprotect(uint32_t ul_enable);\r
+uint32_t matrix_get_writeprotect_status(void);\r
+#endif\r
+\r
+#if SAMG55\r
+void matrix_set_usb_device(void);\r
+void matrix_set_usb_host(void);\r
+#endif\r
+\r
+#if (SAMV71 || SAMV70|| SAME70)\r
+void matrix_set_can0_addr(uint32_t base_addr);\r
+void matrix_set_can1_addr(uint32_t base_addr);\r
+#endif\r
+/* / @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* / @endcond */\r
+\r
+#endif /* MATRIX_H_INCLUDED */\r
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