--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+#ifndef PIO_WPMR_WPKEY_PASSWD\r
+# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu)\r
+#endif\r
+\r
+/**\r
+ * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Parallel Input/Output Controller (PIO) manages up to 32 fully\r
+ * programmable input/output lines. Each I/O line may be dedicated as a\r
+ * general-purpose I/O or be assigned to a function of an embedded peripheral.\r
+ * This assures effective optimization of the pins of a product.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef FREQ_SLOW_CLOCK_EXT\r
+/* External slow clock frequency (hz) */\r
+#define FREQ_SLOW_CLOCK_EXT 32768\r
+#endif\r
+\r
+/**\r
+ * \brief Configure PIO internal pull-up.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (ul_pull_up_enable) {\r
+ p_pio->PIO_PUER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PUDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure Glitch or Debouncing filter for the specified input(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_cut_off Cuts off frequency for debouncing filter.\r
+ */\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off)\r
+{\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+#elif (SAM3XA || SAM3U)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_DIFSR = ul_mask;\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /*\r
+ * The debouncing filter can filter a pulse of less than 1/2 Period of a\r
+ * programmable Divided Slow Clock:\r
+ * Tdiv_slclk = ((DIV+1)*2).Tslow_clock\r
+ */\r
+ p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /\r
+ (2 * (ul_cut_off))) - 1);\r
+}\r
+\r
+/**\r
+ * \brief Set a high output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Set a low output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * pio_get_output_data_status() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ *\r
+ * \retval 1 at least one PIO currently has a high level.\r
+ * \retval 0 all PIOs have a low level.\r
+ */\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_reg;\r
+\r
+ if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {\r
+ ul_reg = p_pio->PIO_ODSR;\r
+ } else {\r
+ ul_reg = p_pio->PIO_PDSR;\r
+ }\r
+\r
+ if ((ul_reg & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure IO of a PIO controller as being controlled by a specific\r
+ * peripheral.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_sr;\r
+\r
+ /* Disable interrupts on the pin(s) */\r
+ p_pio->PIO_IDR = ul_mask;\r
+\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+#if (!SAMG)\r
+ case PIO_PERIPH_C:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+ case PIO_PERIPH_D:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+#endif\r
+ /* Other types are invalid in this function */\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* Remove the pins from under the control of PIO */\r
+ p_pio->PIO_PDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) or a PIO controller as inputs.\r
+ * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can\r
+ * be enabled.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).\r
+ * \param ul_attribute PIO attribute(s).\r
+ */\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);\r
+\r
+ /* Enable Input Filter if necessary */\r
+ if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {\r
+ p_pio->PIO_IFER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_IFDR = ul_mask;\r
+ }\r
+\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_IFSCDR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+ }\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_DIFSR = ul_mask;\r
+ }\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* Configure pin as input */\r
+ p_pio->PIO_ODR = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) of a PIO controller as outputs, with\r
+ * the given default value. Optionally, the multi-drive feature can be enabled\r
+ * on the pin(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure.\r
+ * \param ul_default_level Default level on the pin(s).\r
+ * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as\r
+ * open-drain.\r
+ * \param ul_pull_up_enable Indicates if the pin shall have its pull-up\r
+ * activated.\r
+ */\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);\r
+\r
+ /* Enable multi-drive if necessary */\r
+ if (ul_multidrive_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+\r
+ /* Set default value */\r
+ if (ul_default_level) {\r
+ p_pio->PIO_SODR = ul_mask;\r
+ } else {\r
+ p_pio->PIO_CODR = ul_mask;\r
+ }\r
+\r
+ /* Configure pin(s) as output(s) */\r
+ p_pio->PIO_OER = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_attribute Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ case PIO_PERIPH_B:\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ case PIO_PERIPH_C:\r
+ case PIO_PERIPH_D:\r
+#endif\r
+ pio_set_peripheral(p_pio, ul_type, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));\r
+ break;\r
+\r
+ case PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_attribute);\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),\r
+ (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin are configured to\r
+ * output a high level (even if they are not output).\r
+ * To get the actual value of the pin, use PIO_Get() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s).\r
+ *\r
+ * \retval 1 At least one PIO is configured to output a high level.\r
+ * \retval 0 All PIOs are configured to output a low level.\r
+ */\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask)\r
+{\r
+ if ((p_pio->PIO_ODSR & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure PIO pin multi-driver.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be\r
+ * configured.\r
+ */\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable)\r
+{\r
+ /* Enable the multi-driver if necessary */\r
+ if (ul_multi_driver_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get multi-driver status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The multi-driver mask value.\r
+ */\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_MDSR;\r
+}\r
+\r
+\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/**\r
+ * \brief Configure PIO pin internal pull-down.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall\r
+ * be configured.\r
+ */\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable)\r
+{\r
+ /* Enable the pull-down if necessary */\r
+ if (ul_pull_down_enable) {\r
+ p_pio->PIO_PPDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PPDDR = ul_mask;\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PIO output write for synchronous data output.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO output write.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO output write status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The output write mask value.\r
+ */\r
+uint32_t pio_get_output_write_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_OWSR;\r
+}\r
+\r
+/**\r
+ * \brief Synchronously write on output pins.\r
+ * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are\r
+ * written.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ODSR = ul_mask;\r
+}\r
+\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/**\r
+ * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is\r
+ * active.\r
+ * Disabling the Schmitt Trigger is requested when using the QTouch Library.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SCHMITT = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Get PIO pin schmitt trigger status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The schmitt trigger mask value.\r
+ */\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_SCHMITT;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure the given interrupt source.\r
+ * Interrupt can be configured to trigger on rising edge, falling edge,\r
+ * high level, low level or simply on level change.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt source bit map.\r
+ * \param ul_attr Interrupt source attributes.\r
+ */\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attr)\r
+{\r
+ /* Configure additional interrupt mode registers. */\r
+ if (ul_attr & PIO_IT_AIME) {\r
+ /* Enable additional interrupt mode. */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ Rising Edge/High level detection event. */\r
+ if (ul_attr & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ edge detection source. */\r
+ if (ul_attr & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode. */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source.\r
+ * The PIO must be configured as an NVIC interrupt source as well.\r
+ * The status register of the corresponding PIO controller is cleared\r
+ * prior to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ISR;\r
+ p_pio->PIO_IER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source, with no added side effects.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_IDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Set additional interrupt mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ * \param ul_attribute Pin(s) attributes.\r
+ */\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Enables additional interrupt mode if needed */\r
+ if (ul_attribute & PIO_IT_AIME) {\r
+ /* Enables additional interrupt mode */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* Configures the Polarity of the event detection */\r
+ /* (Rising/Falling Edge or High/Low Level) */\r
+ if (ul_attribute & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* Configures the type of event detection (Edge or Level) */\r
+ if (ul_attribute & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+#ifndef PIO_WPMR_WPKEY_PASSWD\r
+#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU)\r
+#endif\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PIO registers.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)\r
+{\r
+ p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN);\r
+}\r
+\r
+/**\r
+ * \brief Read write protect status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return Return write protect status.\r
+ */\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_WPSR;\r
+}\r
+\r
+/**\r
+ * \brief Return the value of a pin.\r
+ *\r
+ * \param ul_pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ *\r
+ * \note If pin is output: a pull-up or pull-down could hide the actual value.\r
+ * The function \ref pio_get can be called to get the actual pin output\r
+ * level.\r
+ * \note If pin is input: PIOx must be clocked to sample the signal.\r
+ * See PMC driver.\r
+ */\r
+uint32_t pio_get_pin_value(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 1.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called beforehand.\r
+ */\r
+void pio_set_pin_high(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ /* Value to be driven on the I/O line: 1. */\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 0.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_set_pin_low(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ /* Value to be driven on the I/O line: 0. */\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_toggle_pin(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {\r
+ /* Value to be driven on the I/O line: 0. */\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+ } else {\r
+ /* Value to be driven on the I/O line: 1. */\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param ul_pin Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+#endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 1.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ /* Value to be driven on the I/O line: 1. */\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 0.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ /* Value to be driven on the I/O line: 0. */\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO group.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ if (p_pio->PIO_ODSR & ul_mask) {\r
+ /* Value to be driven on the I/O line: 0. */\r
+ p_pio->PIO_CODR = ul_mask;\r
+ } else {\r
+ /* Value to be driven on the I/O line: 1. */\r
+ p_pio->PIO_SODR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pin(s) attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin_group(Pio *p_pio,\r
+ uint32_t ul_mask, const uint32_t ul_flags)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+#endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask,\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_enable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ p_pio->PIO_IER = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_disable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = pio_get_pin_group(ul_pin);\r
+\r
+ p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return Pointer to \ref Pio struct for GPIO port.\r
+ */\r
+Pio *pio_get_pin_group(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio;\r
+\r
+#if (SAM4C || SAM4CP)\r
+# ifdef ID_PIOD\r
+ if (ul_pin > PIO_PC9_IDX) {\r
+ p_pio = PIOD;\r
+ } else if (ul_pin > PIO_PB31_IDX) {\r
+# else\r
+ if (ul_pin > PIO_PB31_IDX) {\r
+# endif\r
+ p_pio = PIOC;\r
+ } else {\r
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ }\r
+#elif (SAM4CM)\r
+ if (ul_pin > PIO_PB21_IDX) {\r
+ p_pio = PIOC;\r
+ } else {\r
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ }\r
+#else\r
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+#endif\r
+ return p_pio;\r
+}\r
+\r
+/**\r
+ * \brief Return GPIO port peripheral ID for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port peripheral ID.\r
+ */\r
+uint32_t pio_get_pin_group_id(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_id;\r
+\r
+#if (SAM4C || SAM4CP)\r
+# ifdef ID_PIOD\r
+ if (ul_pin > PIO_PC9_IDX) {\r
+ ul_id = ID_PIOD;\r
+ } else if (ul_pin > PIO_PB31_IDX) {\r
+# else\r
+ if (ul_pin > PIO_PB31_IDX) {\r
+# endif\r
+ ul_id = ID_PIOC;\r
+ } else {\r
+ ul_id = ID_PIOA + (ul_pin >> 5);\r
+ }\r
+#elif (SAM4CM)\r
+ if (ul_pin > PIO_PB21_IDX) {\r
+ ul_id = ID_PIOC;\r
+ } else {\r
+ ul_id = ID_PIOA + (ul_pin >> 5);\r
+ }\r
+#elif (SAMV70 || SAMV71 || SAME70 || SAMS70)\r
+ if (ul_pin > PIO_PC31_IDX) {\r
+ if(ul_pin > PIO_PD31_IDX){\r
+ ul_id = ID_PIOE;\r
+ } else {\r
+ ul_id = ID_PIOD;\r
+ }\r
+ } else {\r
+ ul_id = ID_PIOA + (ul_pin >> 5);\r
+ }\r
+#else\r
+ ul_id = ID_PIOA + (ul_pin >> 5);\r
+#endif\r
+ return ul_id;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port pin mask for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port pin mask.\r
+ */\r
+uint32_t pio_get_pin_group_mask(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_mask = 1 << (ul_pin & 0x1F);\r
+ return ul_mask;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/* Capture mode enable flag */\r
+uint32_t pio_capture_enable_flag;\r
+\r
+/**\r
+ * \brief Configure PIO capture mode.\r
+ * \note PIO capture mode will be disabled automatically.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mode Bitmask of one or more modes.\r
+ */\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)\r
+{\r
+ ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */\r
+ p_pio->PIO_PCMR = ul_mode;\r
+}\r
+\r
+/**\r
+ * \brief Enable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_enable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR |= PIO_PCMR_PCEN;\r
+ pio_capture_enable_flag = true;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_disable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);\r
+ pio_capture_enable_flag = false;\r
+}\r
+\r
+/**\r
+ * \brief Read from Capture Reception Holding Register.\r
+ * \note Data presence should be tested before any read attempt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param pul_data Pointer to store the data.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, Capture data is not ready.\r
+ */\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)\r
+{\r
+ /* Check if the data is ready */\r
+ if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {\r
+ return 1;\r
+ }\r
+\r
+ /* Read data */\r
+ *pul_data = p_pio->PIO_PCRHR;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source of PIO capture. The status\r
+ * register of the corresponding PIO capture controller is cleared prior\r
+ * to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCISR;\r
+ p_pio->PIO_PCIER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCIDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCIMR;\r
+}\r
+#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/**\r
+ * \brief Get PDC registers base address.\r
+ *\r
+ * \param p_pio Pointer to an PIO peripheral.\r
+ *\r
+ * \return PIOA PDC register base address.\r
+ */\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio)\r
+{\r
+ UNUSED(p_pio); /* Stop warning */\r
+ return PDC_PIOA;\r
+}\r
+#endif\r
+#endif\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM || SAMG55)\r
+/**\r
+ * \brief Set PIO IO drive.\r
+ *\r
+ * \param p_pio Pointer to an PIO peripheral.\r
+ * \param ul_line Line index (0..31).\r
+ * \param mode IO drive mode.\r
+ */\r
+void pio_set_io_drive(Pio *p_pio, uint32_t ul_line,\r
+ enum pio_io_drive_mode mode)\r
+{\r
+ p_pio->PIO_DRIVER &= ~(1 << ul_line);\r
+ p_pio->PIO_DRIVER |= mode << ul_line;\r
+}\r
+#endif\r
+\r
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/**\r
+ * \brief Enable PIO keypad controller.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_keypad_enable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_KER |= PIO_KER_KCE;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO keypad controller.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_keypad_disable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_KER &= (~PIO_KER_KCE);\r
+}\r
+\r
+/**\r
+ * \brief Set PIO keypad controller row number.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param num Number of row of the keypad matrix.\r
+ */\r
+void pio_keypad_set_row_num(Pio *p_pio, uint8_t num)\r
+{\r
+ p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk);\r
+ p_pio->PIO_KRCR |= PIO_KRCR_NBR(num);\r
+}\r
+\r
+/**\r
+ * \brief Get PIO keypad controller row number.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \r
+ * \return Number of row of the keypad matrix.\r
+ */\r
+uint8_t pio_keypad_get_row_num(const Pio *p_pio)\r
+{\r
+ return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Set PIO keypad controller column number.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param num Number of column of the keypad matrix.\r
+ */\r
+void pio_keypad_set_column_num(Pio *p_pio, uint8_t num)\r
+{\r
+ p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk);\r
+ p_pio->PIO_KRCR |= PIO_KRCR_NBC(num);\r
+}\r
+\r
+/**\r
+ * \brief Get PIO keypad controller column number.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \r
+ * \return Number of column of the keypad matrix.\r
+ */\r
+uint8_t pio_keypad_get_column_num(const Pio *p_pio)\r
+{\r
+ return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Set PIO keypad matrix debouncing value.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param num Number of debouncing value.\r
+ */\r
+void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value)\r
+{\r
+ p_pio->PIO_KDR = PIO_KDR_DBC(value);\r
+}\r
+\r
+/**\r
+ * \brief Get PIO keypad matrix debouncing value.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The keypad debouncing value.\r
+ */\r
+uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio)\r
+{\r
+ return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Enable the interrupt source of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_KIER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable the interrupt source of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_KIDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Get interrupt mask of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_KIMR;\r
+}\r
+\r
+/**\r
+ * \brief Get key press status of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The status of key press.\r
+ * 0: No key press has been detected.\r
+ * 1: At least one key press has been detected.\r
+ */\r
+uint32_t pio_keypad_get_press_status(const Pio *p_pio)\r
+{\r
+ if (p_pio->PIO_KSR & PIO_KSR_KPR) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get key release status of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The status of key release.\r
+ * 0 No key release has been detected.\r
+ * 1 At least one key release has been detected.\r
+ */\r
+uint32_t pio_keypad_get_release_status(const Pio *p_pio)\r
+{\r
+ if (p_pio->PIO_KSR & PIO_KSR_KRL) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get simultaneous key press number of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The number of simultaneous key press.\r
+ */\r
+uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio)\r
+{\r
+ return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Get simultaneous key release number of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The number of simultaneous key release.\r
+ */\r
+uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio)\r
+{\r
+ return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Get detected key press row index of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param queue The queue of key press row\r
+ *\r
+ * \return The index of detected key press row.\r
+ */\r
+uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue)\r
+{\r
+ switch (queue) {\r
+ case 0:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos);\r
+ case 1:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos);\r
+ case 2:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos);\r
+ case 3:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos);\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get detected key press column index of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param queue The queue of key press column\r
+ *\r
+ * \return The index of detected key press column.\r
+ */\r
+uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue)\r
+{\r
+ switch (queue) {\r
+ case 0:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos);\r
+ case 1:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos);\r
+ case 2:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos);\r
+ case 3:\r
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos);\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get detected key release row index of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param queue The queue of key release row\r
+ *\r
+ * \return The index of detected key release row.\r
+ */\r
+uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue)\r
+{\r
+ switch (queue) {\r
+ case 0:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos);\r
+ case 1:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos);\r
+ case 2:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos);\r
+ case 3:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos);\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get detected key release column index of PIO keypad.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param queue The queue of key release column\r
+ *\r
+ * \return The index of detected key release column.\r
+ */\r
+uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue)\r
+{\r
+ switch (queue) {\r
+ case 0:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos);\r
+ case 1:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos);\r
+ case 2:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos);\r
+ case 3:\r
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos);\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+//@}\r
+\r
projects / freertos / blobdiff