--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#include "uart.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_uart_group Universal Asynchronous Receiver Transceiver (UART)\r
+ *\r
+ * The Universal Asynchronous Receiver Transmitter features a two-pin UART that\r
+ * can be used for communication and trace purposes and offers an ideal medium\r
+ * for in-situ programming solutions. Moreover, the association with two\r
+ * peripheral DMA controller (PDC) channels permits packet handling for these\r
+ * tasks with processor time reduced to a minimum.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Enable the UART peripheral clock in the PMC.\r
+ * -# Enable the required UART PIOs (see pio.h).\r
+ * -# Configure the UART by calling uart_init.\r
+ * -# Send data through the UART using the uart_write.\r
+ * -# Receive data from the UART using the uart_read; the availability of data\r
+ * can be polled with uart_is_rx_ready.\r
+ * -# Disable the transmitter and/or the receiver of the UART with\r
+ * uart_disable_tx and uart_disable_rx.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Configure UART with the specified parameters.\r
+ *\r
+ * \note The PMC and PIOs must be configured first.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param p_uart_opt Pointer to sam_uart_opt_t instance.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Bad baud rate generator value.\r
+ */\r
+uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt)\r
+{\r
+ uint32_t cd = 0;\r
+\r
+ /* Reset and disable receiver & transmitter */\r
+ p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX\r
+ | UART_CR_RXDIS | UART_CR_TXDIS;\r
+\r
+ /* Check and configure baudrate */\r
+ /* Asynchronous, no oversampling */\r
+ cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV;\r
+ if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR)\r
+ return 1;\r
+\r
+ p_uart->UART_BRGR = cd;\r
+ /* Configure mode */\r
+ p_uart->UART_MR = p_uart_opt->ul_mode;\r
+\r
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)\r
+ /* Disable PDC channel */\r
+ p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;\r
+#endif\r
+\r
+ /* Enable receiver and transmitter */\r
+ p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable UART transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_enable_tx(Uart *p_uart)\r
+{\r
+ /* Enable transmitter */\r
+ p_uart->UART_CR = UART_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable UART transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_disable_tx(Uart *p_uart)\r
+{\r
+ /* Disable transmitter */\r
+ p_uart->UART_CR = UART_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Reset UART transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_reset_tx(Uart *p_uart)\r
+{\r
+ /* Reset transmitter */\r
+ p_uart->UART_CR = UART_CR_RSTTX | UART_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable UART receiver.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_enable_rx(Uart *p_uart)\r
+{\r
+ /* Enable receiver */\r
+ p_uart->UART_CR = UART_CR_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable UART receiver.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_disable_rx(Uart *p_uart)\r
+{\r
+ /* Disable receiver */\r
+ p_uart->UART_CR = UART_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Reset UART receiver.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_reset_rx(Uart *p_uart)\r
+{\r
+ /* Reset receiver */\r
+ p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable UART receiver and transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_enable(Uart *p_uart)\r
+{\r
+ /* Enable receiver and transmitter */\r
+ p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable UART receiver and transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_disable(Uart *p_uart)\r
+{\r
+ /* Disable receiver and transmitter */\r
+ p_uart->UART_CR = UART_CR_RXDIS | UART_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Reset UART receiver and transmitter.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_reset(Uart *p_uart)\r
+{\r
+ /* Reset and disable receiver & transmitter */\r
+ p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX\r
+ | UART_CR_RXDIS | UART_CR_TXDIS;\r
+}\r
+\r
+/** \brief Enable UART interrupts.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param ul_sources Interrupts to be enabled.\r
+ */\r
+void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources)\r
+{\r
+ p_uart->UART_IER = ul_sources;\r
+}\r
+\r
+/** \brief Disable UART interrupts.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param ul_sources Interrupts to be disabled.\r
+ */\r
+void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources)\r
+{\r
+ p_uart->UART_IDR = ul_sources;\r
+}\r
+\r
+/** \brief Read UART interrupt mask.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t uart_get_interrupt_mask(Uart *p_uart)\r
+{\r
+ return p_uart->UART_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \return The current UART status.\r
+ */\r
+uint32_t uart_get_status(Uart *p_uart)\r
+{\r
+ return p_uart->UART_SR;\r
+}\r
+\r
+/**\r
+ * \brief Reset status bits.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_reset_status(Uart *p_uart)\r
+{\r
+ p_uart->UART_CR = UART_CR_RSTSTA;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit is Ready.\r
+ * Check if data has been loaded in UART_THR and is waiting to be loaded in the\r
+ * Transmit Shift Register (TSR).\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Data has been transmitted.\r
+ * \retval 0 Transmit is not ready, data pending.\r
+ */\r
+uint32_t uart_is_tx_ready(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_TXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit Hold Register is empty.\r
+ * Check if the last data written in UART_THR has been loaded in TSR and the\r
+ * last data loaded in TSR has been transmitted.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Transmitter is empty.\r
+ * \retval 0 Transmitter is not empty.\r
+ */\r
+uint32_t uart_is_tx_empty(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if Received data is ready.\r
+ * Check if data has been received and loaded in UART_RHR.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 One data has been received.\r
+ * \retval 0 No data has been received.\r
+ */\r
+uint32_t uart_is_rx_ready(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_RXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both transmit buffers are sent out.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Transmit buffer is empty.\r
+ * \retval 0 Transmit buffer is not empty.\r
+ */\r
+uint32_t uart_is_tx_buf_empty(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Set UART clock divisor value\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param us_divisor Value to be set.\r
+ *\r
+ */\r
+void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor)\r
+{\r
+ p_uart->UART_BRGR = us_divisor;\r
+}\r
+\r
+/**\r
+ * \brief Write to UART Transmit Holding Register\r
+ * Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param data Data to be sent.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, UART is not ready.\r
+ */\r
+uint32_t uart_write(Uart *p_uart, const uint8_t uc_data)\r
+{\r
+ /* Check if the transmitter is ready */\r
+ if (!(p_uart->UART_SR & UART_SR_TXRDY))\r
+ return 1;\r
+\r
+ /* Send character */\r
+ p_uart->UART_THR = uc_data;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Read from UART Receive Holding Register.\r
+ * Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, UART is not ready.\r
+ */\r
+uint32_t uart_read(Uart *p_uart, uint8_t *puc_data)\r
+{\r
+ /* Check if the receiver is ready */\r
+ if ((p_uart->UART_SR & UART_SR_RXRDY) == 0)\r
+ return 1;\r
+\r
+ /* Read character */\r
+ *puc_data = (uint8_t) p_uart->UART_RHR;\r
+ return 0;\r
+}\r
+\r
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)\r
+/**\r
+ * \brief Check if one receive buffer is filled.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Receive is completed.\r
+ * \retval 0 Receive is still pending.\r
+ */\r
+uint32_t uart_is_rx_buf_end(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_ENDRX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one transmit buffer is sent out.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Transmit is completed.\r
+ * \retval 0 Transmit is still pending.\r
+ */\r
+uint32_t uart_is_tx_buf_end(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_ENDTX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both receive buffers are full.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \retval 1 Receive buffers are full.\r
+ * \retval 0 Receive buffers are not full.\r
+ */\r
+uint32_t uart_is_rx_buf_full(Uart *p_uart)\r
+{\r
+ return (p_uart->UART_SR & UART_SR_RXBUFF) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Get UART PDC base address.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ *\r
+ * \return UART PDC registers base for PDC driver to access.\r
+ */\r
+Pdc *uart_get_pdc_base(Uart *p_uart)\r
+{\r
+ Pdc *p_pdc_base;\r
+\r
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)\r
+ if (p_uart == UART0)\r
+ p_pdc_base = PDC_UART0;\r
+#elif (SAM3XA || SAM3U)\r
+ if (p_uart == UART)\r
+ p_pdc_base = PDC_UART;\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+#if (SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)\r
+ if (p_uart == UART1)\r
+ p_pdc_base = PDC_UART1;\r
+#endif\r
+\r
+#if (SAM4N)\r
+ if (p_uart == UART2)\r
+ p_pdc_base = PDC_UART2;\r
+#endif\r
+\r
+ return p_pdc_base;\r
+}\r
+#endif\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+/**\r
+ * \brief Enable UART optical interface.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_enable_optical_interface(Uart *p_uart)\r
+{\r
+ Assert(p_uart == UART1);\r
+ p_uart->UART_MR |= UART_MR_OPT_EN;\r
+}\r
+\r
+/**\r
+ * \brief Disable UART optical interface.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ */\r
+void uart_disable_optical_interface(Uart *p_uart)\r
+{\r
+ Assert(p_uart == UART1);\r
+ p_uart->UART_MR &= ~UART_MR_OPT_EN;\r
+}\r
+\r
+/**\r
+ * \brief Enable UART optical interface.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param cfg Pointer to a UART optical interface configuration.\r
+ */\r
+void uart_config_optical_interface(Uart *p_uart,\r
+ struct uart_config_optical *cfg)\r
+{\r
+ Assert(p_uart == UART1);\r
+ uint32_t reg = p_uart->UART_MR;\r
+\r
+ reg &= ~(UART_MR_OPT_RXINV | UART_MR_OPT_MDINV | UART_MR_FILTER\r
+ | UART_MR_OPT_CLKDIV_Msk | UART_MR_OPT_DUTY_Msk\r
+ | UART_MR_OPT_CMPTH_Msk);\r
+ reg |= (cfg->rx_inverted ? UART_MR_OPT_RXINV : 0)\r
+ | (cfg->tx_inverted ? UART_MR_OPT_MDINV : 0)\r
+ | (cfg->rx_filter ? UART_MR_FILTER : 0)\r
+ | UART_MR_OPT_CLKDIV(cfg->clk_div)\r
+ | cfg->duty | cfg->threshold;\r
+\r
+ p_uart->UART_MR = reg;\r
+}\r
+#endif\r
+\r
+#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+/**\r
+ * \brief Set sleepwalking match mode.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param ul_low_value First comparison value for received character.\r
+ * \param ul_high_value Second comparison value for received character.\r
+ * \param cmpmode ture for start condition, false for flag only.\r
+ * \param cmppar ture for parity check, false for no.\r
+ */\r
+void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value,\r
+ bool cmpmode, bool cmppar, uint8_t ul_high_value)\r
+{\r
+ Assert(ul_low_value <= ul_high_value);\r
+\r
+ uint32_t temp = 0;\r
+\r
+ if (cmpmode) {\r
+ temp |= UART_CMPR_CMPMODE_START_CONDITION;\r
+ }\r
+\r
+ if (cmppar) {\r
+ temp |= UART_CMPR_CMPPAR;\r
+ }\r
+\r
+ temp |= UART_CMPR_VAL1(ul_low_value);\r
+\r
+ temp |= UART_CMPR_VAL2(ul_high_value);\r
+\r
+ p_uart->UART_CMPR= temp;\r
+}\r
+\r
+/**\r
+ * \brief Enables/Disables write protection mode.\r
+ *\r
+ * \param p_uart Pointer to a UART instance.\r
+ * \param flag ture for enable, false for disable.\r
+ */\r
+void uart_set_write_protection(Uart *p_uart, bool flag)\r
+{\r
+ if (flag) {\r
+ p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD | UART_WPMR_WPEN;\r
+ } else {\r
+ p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD;\r
+ }\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
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