--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef UART_H_INCLUDED\r
+#define UART_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/* UART internal div factor for sampling */\r
+#define UART_MCK_DIV 16\r
+/* Div factor to get the maximum baud rate */\r
+#define UART_MCK_DIV_MIN_FACTOR 1\r
+/* Div factor to get the minimum baud rate */\r
+#define UART_MCK_DIV_MAX_FACTOR 65535\r
+\r
+/*! \brief Option list for UART peripheral initialization */\r
+typedef struct sam_uart_opt {\r
+ /** MCK for UART */\r
+ uint32_t ul_mck;\r
+ /** Expected baud rate */\r
+ uint32_t ul_baudrate;\r
+ /** Initialize value for UART mode register */\r
+ uint32_t ul_mode;\r
+} sam_uart_opt_t;\r
+\r
+uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt);\r
+void uart_enable_tx(Uart *p_uart);\r
+void uart_disable_tx(Uart *p_uart);\r
+void uart_reset_tx(Uart *p_uart);\r
+void uart_enable_rx(Uart *p_uart);\r
+void uart_disable_rx(Uart *p_uart);\r
+void uart_reset_rx(Uart *p_uart);\r
+void uart_enable(Uart *p_uart);\r
+void uart_disable(Uart *p_uart);\r
+void uart_reset(Uart *p_uart);\r
+void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources);\r
+void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources);\r
+uint32_t uart_get_interrupt_mask(Uart *p_uart);\r
+uint32_t uart_get_status(Uart *p_uart);\r
+void uart_reset_status(Uart *p_uart);\r
+uint32_t uart_is_tx_ready(Uart *p_uart);\r
+uint32_t uart_is_tx_empty(Uart *p_uart);\r
+uint32_t uart_is_rx_ready(Uart *p_uart);\r
+uint32_t uart_is_tx_buf_empty(Uart *p_uart);\r
+void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor);\r
+uint32_t uart_write(Uart *p_uart, const uint8_t uc_data);\r
+uint32_t uart_read(Uart *p_uart, uint8_t *puc_data);\r
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)\r
+uint32_t uart_is_rx_buf_end(Uart *p_uart);\r
+uint32_t uart_is_tx_buf_end(Uart *p_uart);\r
+uint32_t uart_is_rx_buf_full(Uart *p_uart);\r
+Pdc *uart_get_pdc_base(Uart *p_uart);\r
+#endif\r
+#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70)\r
+void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value,\r
+ bool cmpmode, bool cmppar, uint8_t ul_high_value);\r
+void uart_set_write_protection(Uart *p_uart, bool flag);\r
+#endif\r
+\r
+#if (SAM4C || SAM4CP || SAM4CM)\r
+enum uart_optical_duty_cycle {\r
+ UART_MOD_CLK_DUTY_50_00 = UART_MR_OPT_DUTY_DUTY_50,\r
+ UART_MOD_CLK_DUTY_43_75 = UART_MR_OPT_DUTY_DUTY_43P75,\r
+ UART_MOD_CLK_DUTY_37_50 = UART_MR_OPT_DUTY_DUTY_37P5,\r
+ UART_MOD_CLK_DUTY_31_25 = UART_MR_OPT_DUTY_DUTY_31P25,\r
+ UART_MOD_CLK_DUTY_25_00 = UART_MR_OPT_DUTY_DUTY_25,\r
+ UART_MOD_CLK_DUTY_18_75 = UART_MR_OPT_DUTY_DUTY_18P75,\r
+ UART_MOD_CLK_DUTY_12_50 = UART_MR_OPT_DUTY_DUTY_12P5,\r
+ UART_MOD_CLK_DUTY_06_25 = UART_MR_OPT_DUTY_DUTY_6P25,\r
+};\r
+\r
+enum uart_optical_cmp_threshold {\r
+ UART_RX_CMP_THRESHOLD_VDDIO_DIV_10_0 = UART_MR_OPT_CMPTH_VDDIO_DIV10,\r
+ UART_RX_CMP_THRESHOLD_VDDIO_DIV_5_0 = UART_MR_OPT_CMPTH_VDDIO_DIV5,\r
+ UART_RX_CMP_THRESHOLD_VDDIO_DIV_3_3 = UART_MR_OPT_CMPTH_VDDIO_DIV3P3,\r
+ UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_5 = UART_MR_OPT_CMPTH_VDDIO_DIV2P5,\r
+ UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_0 = UART_MR_OPT_CMPTH_VDDIO_DIV2,\r
+};\r
+\r
+struct uart_config_optical {\r
+ /* UART Receive Data Inverted */\r
+ bool rx_inverted;\r
+ /* UART Modulated Data Inverted */\r
+ bool tx_inverted;\r
+ /* UART Receiver Digital Filter */\r
+ bool rx_filter;\r
+ /* Optical Link Clock Divider */\r
+ uint8_t clk_div;\r
+ /* Optical Link Modulation Clock Duty Cycle */\r
+ enum uart_optical_duty_cycle duty;\r
+ /* Receive Path Comparator Threshold */\r
+ enum uart_optical_cmp_threshold threshold;\r
+};\r
+\r
+void uart_enable_optical_interface(Uart *p_uart);\r
+void uart_disable_optical_interface(Uart *p_uart);\r
+void uart_config_optical_interface(Uart *p_uart,\r
+ struct uart_config_optical *cfg);\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* UART_H_INCLUDED */\r
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