Rename DummyTCB_t to StaticTCB_t.

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAME70_Xplained_AtmelStudio / src / ASF / sam / utils / cmsis / same70 / include / instance / qspi.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h
new file mode 100644 (file)
index 0000000..975c44c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/qspi.h
@@ -0,0 +1,85 @@
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ *    this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ *    this list of conditions and the following disclaimer in the documentation\r
+ *    and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ *    Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef _SAME70_QSPI_INSTANCE_\r
+#define _SAME70_QSPI_INSTANCE_\r
+\r
+/* ========== Register definition for QSPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_QSPI_CR                    (0x4007C000U) /**< \brief (QSPI) Control Register */\r
+  #define REG_QSPI_MR                    (0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+  #define REG_QSPI_RDR                   (0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+  #define REG_QSPI_TDR                   (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+  #define REG_QSPI_SR                    (0x4007C010U) /**< \brief (QSPI) Status Register */\r
+  #define REG_QSPI_IER                   (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+  #define REG_QSPI_IDR                   (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+  #define REG_QSPI_IMR                   (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+  #define REG_QSPI_SCR                   (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+  #define REG_QSPI_IAR                   (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+  #define REG_QSPI_ICR                   (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+  #define REG_QSPI_IFR                   (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+  #define REG_QSPI_SMR                   (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+  #define REG_QSPI_SKR                   (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+  #define REG_QSPI_WPMR                  (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+  #define REG_QSPI_WPSR                  (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+#else\r
+  #define REG_QSPI_CR   (*(__O  uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */\r
+  #define REG_QSPI_MR   (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+  #define REG_QSPI_RDR  (*(__I  uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+  #define REG_QSPI_TDR  (*(__O  uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+  #define REG_QSPI_SR   (*(__I  uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */\r
+  #define REG_QSPI_IER  (*(__O  uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+  #define REG_QSPI_IDR  (*(__O  uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+  #define REG_QSPI_IMR  (*(__I  uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+  #define REG_QSPI_SCR  (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+  #define REG_QSPI_IAR  (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+  #define REG_QSPI_ICR  (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+  #define REG_QSPI_IFR  (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+  #define REG_QSPI_SMR  (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+  #define REG_QSPI_SKR  (*(__O  uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+  #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+  #define REG_QSPI_WPSR (*(__I  uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAME70_QSPI_INSTANCE_ */\r