Rename DummyTCB_t to StaticTCB_t.

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAME70_Xplained_AtmelStudio / src / ASF / sam / utils / cmsis / same70 / include / instance / smc.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h
new file mode 100644 (file)
index 0000000..9f07c6d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/ASF/sam/utils/cmsis/same70/include/instance/smc.h
@@ -0,0 +1,95 @@
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ *    this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ *    this list of conditions and the following disclaimer in the documentation\r
+ *    and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ *    Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef _SAME70_SMC_INSTANCE_\r
+#define _SAME70_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_SMC_SETUP0                  (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+  #define REG_SMC_PULSE0                  (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+  #define REG_SMC_CYCLE0                  (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+  #define REG_SMC_MODE0                   (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */\r
+  #define REG_SMC_SETUP1                  (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+  #define REG_SMC_PULSE1                  (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+  #define REG_SMC_CYCLE1                  (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+  #define REG_SMC_MODE1                   (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */\r
+  #define REG_SMC_SETUP2                  (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+  #define REG_SMC_PULSE2                  (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+  #define REG_SMC_CYCLE2                  (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+  #define REG_SMC_MODE2                   (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */\r
+  #define REG_SMC_SETUP3                  (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+  #define REG_SMC_PULSE3                  (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+  #define REG_SMC_CYCLE3                  (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+  #define REG_SMC_MODE3                   (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */\r
+  #define REG_SMC_OCMS                    (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+  #define REG_SMC_KEY1                    (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+  #define REG_SMC_KEY2                    (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+  #define REG_SMC_WPMR                    (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */\r
+  #define REG_SMC_WPSR                    (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */\r
+#else\r
+  #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+  #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+  #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+  #define REG_SMC_MODE0  (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */\r
+  #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+  #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+  #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+  #define REG_SMC_MODE1  (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */\r
+  #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+  #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+  #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+  #define REG_SMC_MODE2  (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */\r
+  #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+  #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+  #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+  #define REG_SMC_MODE3  (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */\r
+  #define REG_SMC_OCMS   (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+  #define REG_SMC_KEY1   (*(__O  uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+  #define REG_SMC_KEY2   (*(__O  uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+  #define REG_SMC_WPMR   (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */\r
+  #define REG_SMC_WPSR   (*(__I  uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAME70_SMC_INSTANCE_ */\r