--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef _SAME70_USART1_INSTANCE_\r
+#define _SAME70_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */\r
+ #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */\r
+ #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+ #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+ #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+ #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+ #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */\r
+ #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */\r
+ #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+ #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+ #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+ #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */\r
+ #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */\r
+ #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */\r
+ #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */\r
+ #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */\r
+ #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */\r
+ #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */\r
+ #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */\r
+ #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */\r
+ #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */\r
+ #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */\r
+ #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */\r
+ #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */\r
+ #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */\r
+ #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */\r
+ #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */\r
+ #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */\r
+#else\r
+ #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */\r
+ #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */\r
+ #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+ #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+ #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+ #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+ #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */\r
+ #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */\r
+ #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+ #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+ #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+ #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */\r
+ #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */\r
+ #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */\r
+ #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */\r
+ #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */\r
+ #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */\r
+ #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */\r
+ #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */\r
+ #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */\r
+ #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */\r
+ #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */\r
+ #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */\r
+ #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */\r
+ #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */\r
+ #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */\r
+ #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */\r
+ #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAME70_USART1_INSTANCE_ */\r
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